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Commit | Line | Data |
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6b39ba77 TG |
1 | /* |
2 | * Common interrupt code for 32 and 64 bit | |
3 | */ | |
4 | #include <linux/cpu.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/kernel_stat.h> | |
4722d194 | 7 | #include <linux/of.h> |
6b39ba77 | 8 | #include <linux/seq_file.h> |
6a02e710 | 9 | #include <linux/smp.h> |
7c1d7cdc | 10 | #include <linux/ftrace.h> |
ca444564 | 11 | #include <linux/delay.h> |
69c60c88 | 12 | #include <linux/export.h> |
6b39ba77 | 13 | |
7b6aa335 | 14 | #include <asm/apic.h> |
6b39ba77 | 15 | #include <asm/io_apic.h> |
c3d80000 | 16 | #include <asm/irq.h> |
01ca79f1 | 17 | #include <asm/mce.h> |
2c1b284e | 18 | #include <asm/hw_irq.h> |
ac2a5539 | 19 | #include <asm/desc.h> |
83ab8514 SRRH |
20 | |
21 | #define CREATE_TRACE_POINTS | |
cf910e83 | 22 | #include <asm/trace/irq_vectors.h> |
6b39ba77 | 23 | |
c5bde906 BG |
24 | DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); |
25 | EXPORT_PER_CPU_SYMBOL(irq_stat); | |
26 | ||
27 | DEFINE_PER_CPU(struct pt_regs *, irq_regs); | |
28 | EXPORT_PER_CPU_SYMBOL(irq_regs); | |
29 | ||
6b39ba77 TG |
30 | atomic_t irq_err_count; |
31 | ||
acaabe79 | 32 | /* Function pointer for generic interrupt vector handling */ |
4a4de9c7 | 33 | void (*x86_platform_ipi_callback)(void) = NULL; |
acaabe79 | 34 | |
249f6d9e TG |
35 | /* |
36 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
37 | * each architecture has to answer this themselves. | |
38 | */ | |
39 | void ack_bad_irq(unsigned int irq) | |
40 | { | |
edea7148 CG |
41 | if (printk_ratelimit()) |
42 | pr_err("unexpected IRQ trap at vector %02x\n", irq); | |
249f6d9e | 43 | |
249f6d9e TG |
44 | /* |
45 | * Currently unexpected vectors happen only on SMP and APIC. | |
46 | * We _must_ ack these because every local APIC has only N | |
47 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
48 | * holds up an irq slot - in excessive cases (when multiple | |
49 | * unexpected vectors occur) that might lock up the APIC | |
50 | * completely. | |
51 | * But only ack when the APIC is enabled -AK | |
52 | */ | |
08306ce6 | 53 | ack_APIC_irq(); |
249f6d9e TG |
54 | } |
55 | ||
1b437c8c | 56 | #define irq_stats(x) (&per_cpu(irq_stat, x)) |
6b39ba77 | 57 | /* |
517e4981 | 58 | * /proc/interrupts printing for arch specific interrupts |
6b39ba77 | 59 | */ |
517e4981 | 60 | int arch_show_interrupts(struct seq_file *p, int prec) |
6b39ba77 TG |
61 | { |
62 | int j; | |
63 | ||
7a81d9a7 | 64 | seq_printf(p, "%*s: ", prec, "NMI"); |
6b39ba77 TG |
65 | for_each_online_cpu(j) |
66 | seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); | |
3736708f | 67 | seq_puts(p, " Non-maskable interrupts\n"); |
6b39ba77 | 68 | #ifdef CONFIG_X86_LOCAL_APIC |
7a81d9a7 | 69 | seq_printf(p, "%*s: ", prec, "LOC"); |
6b39ba77 TG |
70 | for_each_online_cpu(j) |
71 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | |
3736708f | 72 | seq_puts(p, " Local timer interrupts\n"); |
474e56b8 JSR |
73 | |
74 | seq_printf(p, "%*s: ", prec, "SPU"); | |
75 | for_each_online_cpu(j) | |
76 | seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); | |
3736708f | 77 | seq_puts(p, " Spurious interrupts\n"); |
89ccf465 | 78 | seq_printf(p, "%*s: ", prec, "PMI"); |
241771ef IM |
79 | for_each_online_cpu(j) |
80 | seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); | |
3736708f | 81 | seq_puts(p, " Performance monitoring interrupts\n"); |
e360adbe | 82 | seq_printf(p, "%*s: ", prec, "IWI"); |
b6276f35 | 83 | for_each_online_cpu(j) |
e360adbe | 84 | seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs); |
3736708f | 85 | seq_puts(p, " IRQ work interrupts\n"); |
346b46be FLVC |
86 | seq_printf(p, "%*s: ", prec, "RTR"); |
87 | for_each_online_cpu(j) | |
b49d7d87 | 88 | seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count); |
3736708f | 89 | seq_puts(p, " APIC ICR read retries\n"); |
6b39ba77 | 90 | #endif |
4a4de9c7 | 91 | if (x86_platform_ipi_callback) { |
59d13812 | 92 | seq_printf(p, "%*s: ", prec, "PLT"); |
acaabe79 | 93 | for_each_online_cpu(j) |
4a4de9c7 | 94 | seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis); |
3736708f | 95 | seq_puts(p, " Platform interrupts\n"); |
acaabe79 | 96 | } |
6b39ba77 | 97 | #ifdef CONFIG_SMP |
7a81d9a7 | 98 | seq_printf(p, "%*s: ", prec, "RES"); |
6b39ba77 TG |
99 | for_each_online_cpu(j) |
100 | seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); | |
3736708f | 101 | seq_puts(p, " Rescheduling interrupts\n"); |
7a81d9a7 | 102 | seq_printf(p, "%*s: ", prec, "CAL"); |
6b39ba77 | 103 | for_each_online_cpu(j) |
82ba4fac | 104 | seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); |
3736708f | 105 | seq_puts(p, " Function call interrupts\n"); |
7a81d9a7 | 106 | seq_printf(p, "%*s: ", prec, "TLB"); |
6b39ba77 TG |
107 | for_each_online_cpu(j) |
108 | seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); | |
3736708f | 109 | seq_puts(p, " TLB shootdowns\n"); |
6b39ba77 | 110 | #endif |
0444c9bd | 111 | #ifdef CONFIG_X86_THERMAL_VECTOR |
7a81d9a7 | 112 | seq_printf(p, "%*s: ", prec, "TRM"); |
6b39ba77 TG |
113 | for_each_online_cpu(j) |
114 | seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); | |
3736708f | 115 | seq_puts(p, " Thermal event interrupts\n"); |
0444c9bd JB |
116 | #endif |
117 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
7a81d9a7 | 118 | seq_printf(p, "%*s: ", prec, "THR"); |
6b39ba77 TG |
119 | for_each_online_cpu(j) |
120 | seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); | |
3736708f | 121 | seq_puts(p, " Threshold APIC interrupts\n"); |
01ca79f1 | 122 | #endif |
24fd78a8 AG |
123 | #ifdef CONFIG_X86_MCE_AMD |
124 | seq_printf(p, "%*s: ", prec, "DFR"); | |
125 | for_each_online_cpu(j) | |
126 | seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count); | |
127 | seq_puts(p, " Deferred Error APIC interrupts\n"); | |
128 | #endif | |
c1ebf835 | 129 | #ifdef CONFIG_X86_MCE |
01ca79f1 AK |
130 | seq_printf(p, "%*s: ", prec, "MCE"); |
131 | for_each_online_cpu(j) | |
132 | seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); | |
3736708f | 133 | seq_puts(p, " Machine check exceptions\n"); |
ca84f696 AK |
134 | seq_printf(p, "%*s: ", prec, "MCP"); |
135 | for_each_online_cpu(j) | |
136 | seq_printf(p, "%10u ", per_cpu(mce_poll_count, j)); | |
3736708f | 137 | seq_puts(p, " Machine check polls\n"); |
6b39ba77 | 138 | #endif |
f704a7d7 | 139 | #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN) |
9d87cd61 VK |
140 | if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) { |
141 | seq_printf(p, "%*s: ", prec, "HYP"); | |
142 | for_each_online_cpu(j) | |
143 | seq_printf(p, "%10u ", | |
144 | irq_stats(j)->irq_hv_callback_count); | |
145 | seq_puts(p, " Hypervisor callback interrupts\n"); | |
146 | } | |
929320e4 | 147 | #endif |
7a81d9a7 | 148 | seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); |
6b39ba77 | 149 | #if defined(CONFIG_X86_IO_APIC) |
7a81d9a7 | 150 | seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); |
501b3265 FW |
151 | #endif |
152 | #ifdef CONFIG_HAVE_KVM | |
153 | seq_printf(p, "%*s: ", prec, "PIN"); | |
154 | for_each_online_cpu(j) | |
155 | seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis); | |
156 | seq_puts(p, " Posted-interrupt notification event\n"); | |
157 | ||
158 | seq_printf(p, "%*s: ", prec, "PIW"); | |
159 | for_each_online_cpu(j) | |
160 | seq_printf(p, "%10u ", | |
161 | irq_stats(j)->kvm_posted_intr_wakeup_ipis); | |
162 | seq_puts(p, " Posted-interrupt wakeup event\n"); | |
6b39ba77 TG |
163 | #endif |
164 | return 0; | |
165 | } | |
166 | ||
6b39ba77 TG |
167 | /* |
168 | * /proc/stat helpers | |
169 | */ | |
170 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
171 | { | |
172 | u64 sum = irq_stats(cpu)->__nmi_count; | |
173 | ||
174 | #ifdef CONFIG_X86_LOCAL_APIC | |
175 | sum += irq_stats(cpu)->apic_timer_irqs; | |
474e56b8 | 176 | sum += irq_stats(cpu)->irq_spurious_count; |
241771ef | 177 | sum += irq_stats(cpu)->apic_perf_irqs; |
e360adbe | 178 | sum += irq_stats(cpu)->apic_irq_work_irqs; |
b49d7d87 | 179 | sum += irq_stats(cpu)->icr_read_retry_count; |
6b39ba77 | 180 | #endif |
4a4de9c7 DS |
181 | if (x86_platform_ipi_callback) |
182 | sum += irq_stats(cpu)->x86_platform_ipis; | |
6b39ba77 TG |
183 | #ifdef CONFIG_SMP |
184 | sum += irq_stats(cpu)->irq_resched_count; | |
185 | sum += irq_stats(cpu)->irq_call_count; | |
6b39ba77 | 186 | #endif |
0444c9bd | 187 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6b39ba77 | 188 | sum += irq_stats(cpu)->irq_thermal_count; |
0444c9bd JB |
189 | #endif |
190 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
6b39ba77 | 191 | sum += irq_stats(cpu)->irq_threshold_count; |
8051dbd2 | 192 | #endif |
c1ebf835 | 193 | #ifdef CONFIG_X86_MCE |
8051dbd2 HS |
194 | sum += per_cpu(mce_exception_count, cpu); |
195 | sum += per_cpu(mce_poll_count, cpu); | |
6b39ba77 TG |
196 | #endif |
197 | return sum; | |
198 | } | |
199 | ||
200 | u64 arch_irq_stat(void) | |
201 | { | |
202 | u64 sum = atomic_read(&irq_err_count); | |
6b39ba77 TG |
203 | return sum; |
204 | } | |
c3d80000 | 205 | |
7c1d7cdc JF |
206 | |
207 | /* | |
208 | * do_IRQ handles all normal device IRQ's (the special | |
209 | * SMP cross-CPU interrupts have their own specific | |
210 | * handlers). | |
211 | */ | |
1d9090e2 | 212 | __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs) |
7c1d7cdc JF |
213 | { |
214 | struct pt_regs *old_regs = set_irq_regs(regs); | |
a782a7e4 | 215 | struct irq_desc * desc; |
7c1d7cdc JF |
216 | /* high bit used in ret_from_ code */ |
217 | unsigned vector = ~regs->orig_ax; | |
7c1d7cdc | 218 | |
0333a209 AL |
219 | /* |
220 | * NB: Unlike exception entries, IRQ entries do not reliably | |
221 | * handle context tracking in the low-level entry code. This is | |
222 | * because syscall entries execute briefly with IRQs on before | |
223 | * updating context tracking state, so we can take an IRQ from | |
224 | * kernel mode with CONTEXT_USER. The low-level entry code only | |
225 | * updates the context if we came from user mode, so we won't | |
226 | * switch to CONTEXT_KERNEL. We'll fix that once the syscall | |
227 | * code is cleaned up enough that we can cleanly defer enabling | |
228 | * IRQs. | |
229 | */ | |
230 | ||
6af7faf6 | 231 | entering_irq(); |
7c1d7cdc | 232 | |
0333a209 | 233 | /* entering_irq() tells RCU that we're not quiescent. Check it. */ |
5778077d | 234 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU"); |
0333a209 | 235 | |
a782a7e4 | 236 | desc = __this_cpu_read(vector_irq[vector]); |
7c1d7cdc | 237 | |
a782a7e4 | 238 | if (!handle_irq(desc, regs)) { |
08306ce6 | 239 | ack_APIC_irq(); |
7c1d7cdc | 240 | |
a782a7e4 TG |
241 | if (desc != VECTOR_RETRIGGERED) { |
242 | pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n", | |
9345005f | 243 | __func__, smp_processor_id(), |
a782a7e4 | 244 | vector); |
9345005f | 245 | } else { |
7276c6a2 | 246 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
9345005f | 247 | } |
7c1d7cdc JF |
248 | } |
249 | ||
6af7faf6 | 250 | exiting_irq(); |
7c1d7cdc JF |
251 | |
252 | set_irq_regs(old_regs); | |
253 | return 1; | |
254 | } | |
255 | ||
acaabe79 | 256 | /* |
4a4de9c7 | 257 | * Handler for X86_PLATFORM_IPI_VECTOR. |
acaabe79 | 258 | */ |
eddc0e92 | 259 | void __smp_x86_platform_ipi(void) |
acaabe79 | 260 | { |
4a4de9c7 | 261 | inc_irq_stat(x86_platform_ipis); |
acaabe79 | 262 | |
4a4de9c7 DS |
263 | if (x86_platform_ipi_callback) |
264 | x86_platform_ipi_callback(); | |
eddc0e92 | 265 | } |
acaabe79 | 266 | |
1d9090e2 | 267 | __visible void smp_x86_platform_ipi(struct pt_regs *regs) |
eddc0e92 SA |
268 | { |
269 | struct pt_regs *old_regs = set_irq_regs(regs); | |
acaabe79 | 270 | |
eddc0e92 SA |
271 | entering_ack_irq(); |
272 | __smp_x86_platform_ipi(); | |
273 | exiting_irq(); | |
acaabe79 DS |
274 | set_irq_regs(old_regs); |
275 | } | |
276 | ||
d78f2664 | 277 | #ifdef CONFIG_HAVE_KVM |
f6b3c72c FW |
278 | static void dummy_handler(void) {} |
279 | static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler; | |
280 | ||
281 | void kvm_set_posted_intr_wakeup_handler(void (*handler)(void)) | |
282 | { | |
283 | if (handler) | |
284 | kvm_posted_intr_wakeup_handler = handler; | |
285 | else | |
286 | kvm_posted_intr_wakeup_handler = dummy_handler; | |
287 | } | |
288 | EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler); | |
289 | ||
d78f2664 YZ |
290 | /* |
291 | * Handler for POSTED_INTERRUPT_VECTOR. | |
292 | */ | |
1d9090e2 | 293 | __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs) |
d78f2664 YZ |
294 | { |
295 | struct pt_regs *old_regs = set_irq_regs(regs); | |
296 | ||
6af7faf6 | 297 | entering_ack_irq(); |
d78f2664 | 298 | inc_irq_stat(kvm_posted_intr_ipis); |
f6b3c72c FW |
299 | exiting_irq(); |
300 | set_irq_regs(old_regs); | |
301 | } | |
302 | ||
303 | /* | |
304 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
305 | */ | |
306 | __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs) | |
307 | { | |
308 | struct pt_regs *old_regs = set_irq_regs(regs); | |
309 | ||
310 | entering_ack_irq(); | |
311 | inc_irq_stat(kvm_posted_intr_wakeup_ipis); | |
312 | kvm_posted_intr_wakeup_handler(); | |
6af7faf6 | 313 | exiting_irq(); |
d78f2664 YZ |
314 | set_irq_regs(old_regs); |
315 | } | |
316 | #endif | |
317 | ||
1d9090e2 | 318 | __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs) |
cf910e83 SA |
319 | { |
320 | struct pt_regs *old_regs = set_irq_regs(regs); | |
321 | ||
322 | entering_ack_irq(); | |
323 | trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR); | |
324 | __smp_x86_platform_ipi(); | |
325 | trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR); | |
326 | exiting_irq(); | |
327 | set_irq_regs(old_regs); | |
328 | } | |
329 | ||
c3d80000 | 330 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |
7a7732bc SS |
331 | |
332 | #ifdef CONFIG_HOTPLUG_CPU | |
39424e89 PB |
333 | |
334 | /* These two declarations are only used in check_irq_vectors_for_cpu_disable() | |
335 | * below, which is protected by stop_machine(). Putting them on the stack | |
336 | * results in a stack frame overflow. Dynamically allocating could result in a | |
337 | * failure so declare these two cpumasks as global. | |
338 | */ | |
339 | static struct cpumask affinity_new, online_new; | |
340 | ||
da6139e4 PB |
341 | /* |
342 | * This cpu is going to be removed and its vectors migrated to the remaining | |
343 | * online cpus. Check to see if there are enough vectors in the remaining cpus. | |
344 | * This function is protected by stop_machine(). | |
345 | */ | |
346 | int check_irq_vectors_for_cpu_disable(void) | |
347 | { | |
da6139e4 PB |
348 | unsigned int this_cpu, vector, this_count, count; |
349 | struct irq_desc *desc; | |
350 | struct irq_data *data; | |
a782a7e4 | 351 | int cpu; |
da6139e4 PB |
352 | |
353 | this_cpu = smp_processor_id(); | |
354 | cpumask_copy(&online_new, cpu_online_mask); | |
020b37ac | 355 | cpumask_clear_cpu(this_cpu, &online_new); |
da6139e4 PB |
356 | |
357 | this_count = 0; | |
358 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
a782a7e4 TG |
359 | desc = __this_cpu_read(vector_irq[vector]); |
360 | if (IS_ERR_OR_NULL(desc)) | |
44825757 | 361 | continue; |
44825757 TG |
362 | /* |
363 | * Protect against concurrent action removal, affinity | |
364 | * changes etc. | |
365 | */ | |
366 | raw_spin_lock(&desc->lock); | |
367 | data = irq_desc_get_irq_data(desc); | |
a782a7e4 TG |
368 | cpumask_copy(&affinity_new, |
369 | irq_data_get_affinity_mask(data)); | |
44825757 | 370 | cpumask_clear_cpu(this_cpu, &affinity_new); |
da6139e4 | 371 | |
44825757 | 372 | /* Do not count inactive or per-cpu irqs. */ |
a782a7e4 | 373 | if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) { |
cbb24dc7 | 374 | raw_spin_unlock(&desc->lock); |
44825757 | 375 | continue; |
da6139e4 | 376 | } |
44825757 TG |
377 | |
378 | raw_spin_unlock(&desc->lock); | |
379 | /* | |
380 | * A single irq may be mapped to multiple cpu's | |
381 | * vector_irq[] (for example IOAPIC cluster mode). In | |
382 | * this case we have two possibilities: | |
383 | * | |
384 | * 1) the resulting affinity mask is empty; that is | |
385 | * this the down'd cpu is the last cpu in the irq's | |
386 | * affinity mask, or | |
387 | * | |
388 | * 2) the resulting affinity mask is no longer a | |
389 | * subset of the online cpus but the affinity mask is | |
390 | * not zero; that is the down'd cpu is the last online | |
391 | * cpu in a user set affinity mask. | |
392 | */ | |
393 | if (cpumask_empty(&affinity_new) || | |
394 | !cpumask_subset(&affinity_new, &online_new)) | |
395 | this_count++; | |
da6139e4 PB |
396 | } |
397 | ||
398 | count = 0; | |
399 | for_each_online_cpu(cpu) { | |
400 | if (cpu == this_cpu) | |
401 | continue; | |
ac2a5539 YL |
402 | /* |
403 | * We scan from FIRST_EXTERNAL_VECTOR to first system | |
404 | * vector. If the vector is marked in the used vectors | |
405 | * bitmap or an irq is assigned to it, we don't count | |
406 | * it as available. | |
cbb24dc7 TG |
407 | * |
408 | * As this is an inaccurate snapshot anyway, we can do | |
409 | * this w/o holding vector_lock. | |
ac2a5539 YL |
410 | */ |
411 | for (vector = FIRST_EXTERNAL_VECTOR; | |
412 | vector < first_system_vector; vector++) { | |
413 | if (!test_bit(vector, used_vectors) && | |
a782a7e4 TG |
414 | IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector])) |
415 | count++; | |
da6139e4 PB |
416 | } |
417 | } | |
418 | ||
419 | if (count < this_count) { | |
420 | pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n", | |
421 | this_cpu, this_count, count); | |
422 | return -ERANGE; | |
423 | } | |
424 | return 0; | |
425 | } | |
426 | ||
7a7732bc SS |
427 | /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ |
428 | void fixup_irqs(void) | |
429 | { | |
5231a686 | 430 | unsigned int irq, vector; |
7a7732bc SS |
431 | static int warned; |
432 | struct irq_desc *desc; | |
a3c08e5d | 433 | struct irq_data *data; |
51c43ac6 | 434 | struct irq_chip *chip; |
fb24da80 | 435 | int ret; |
7a7732bc SS |
436 | |
437 | for_each_irq_desc(irq, desc) { | |
438 | int break_affinity = 0; | |
439 | int set_affinity = 1; | |
440 | const struct cpumask *affinity; | |
441 | ||
442 | if (!desc) | |
443 | continue; | |
444 | if (irq == 2) | |
445 | continue; | |
446 | ||
447 | /* interrupt's are disabled at this point */ | |
239007b8 | 448 | raw_spin_lock(&desc->lock); |
7a7732bc | 449 | |
51c43ac6 | 450 | data = irq_desc_get_irq_data(desc); |
c149e4cd | 451 | affinity = irq_data_get_affinity_mask(data); |
b87ba87c | 452 | if (!irq_has_action(irq) || irqd_is_per_cpu(data) || |
58bff947 | 453 | cpumask_subset(affinity, cpu_online_mask)) { |
239007b8 | 454 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
455 | continue; |
456 | } | |
457 | ||
a5e74b84 SS |
458 | /* |
459 | * Complete the irq move. This cpu is going down and for | |
460 | * non intr-remapping case, we can't wait till this interrupt | |
461 | * arrives at this cpu before completing the irq move. | |
462 | */ | |
90a2282e | 463 | irq_force_complete_move(desc); |
a5e74b84 | 464 | |
7a7732bc SS |
465 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
466 | break_affinity = 1; | |
2530cd4f | 467 | affinity = cpu_online_mask; |
7a7732bc SS |
468 | } |
469 | ||
51c43ac6 | 470 | chip = irq_data_get_irq_chip(data); |
36f34c8c TG |
471 | /* |
472 | * The interrupt descriptor might have been cleaned up | |
473 | * already, but it is not yet removed from the radix tree | |
474 | */ | |
475 | if (!chip) { | |
476 | raw_spin_unlock(&desc->lock); | |
477 | continue; | |
478 | } | |
479 | ||
51c43ac6 TG |
480 | if (!irqd_can_move_in_process_context(data) && chip->irq_mask) |
481 | chip->irq_mask(data); | |
7a7732bc | 482 | |
fb24da80 PB |
483 | if (chip->irq_set_affinity) { |
484 | ret = chip->irq_set_affinity(data, affinity, true); | |
485 | if (ret == -ENOSPC) | |
486 | pr_crit("IRQ %d set affinity failed because there are no available vectors. The device assigned to this IRQ is unstable.\n", irq); | |
487 | } else { | |
488 | if (!(warned++)) | |
489 | set_affinity = 0; | |
490 | } | |
7a7732bc | 491 | |
99dd5497 LC |
492 | /* |
493 | * We unmask if the irq was not marked masked by the | |
494 | * core code. That respects the lazy irq disable | |
495 | * behaviour. | |
496 | */ | |
983bbf1a | 497 | if (!irqd_can_move_in_process_context(data) && |
99dd5497 | 498 | !irqd_irq_masked(data) && chip->irq_unmask) |
51c43ac6 | 499 | chip->irq_unmask(data); |
7a7732bc | 500 | |
239007b8 | 501 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
502 | |
503 | if (break_affinity && set_affinity) | |
c767a54b | 504 | pr_notice("Broke affinity for irq %i\n", irq); |
7a7732bc | 505 | else if (!set_affinity) |
c767a54b | 506 | pr_notice("Cannot set affinity for irq %i\n", irq); |
7a7732bc SS |
507 | } |
508 | ||
5231a686 SS |
509 | /* |
510 | * We can remove mdelay() and then send spuriuous interrupts to | |
511 | * new cpu targets for all the irqs that were handled previously by | |
512 | * this cpu. While it works, I have seen spurious interrupt messages | |
513 | * (nothing wrong but still...). | |
514 | * | |
515 | * So for now, retain mdelay(1) and check the IRR and then send those | |
516 | * interrupts to new targets as this cpu is already offlined... | |
517 | */ | |
7a7732bc | 518 | mdelay(1); |
5231a686 | 519 | |
09cf92b7 TG |
520 | /* |
521 | * We can walk the vector array of this cpu without holding | |
522 | * vector_lock because the cpu is already marked !online, so | |
523 | * nothing else will touch it. | |
524 | */ | |
5231a686 SS |
525 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
526 | unsigned int irr; | |
527 | ||
a782a7e4 | 528 | if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector]))) |
5231a686 SS |
529 | continue; |
530 | ||
531 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
532 | if (irr & (1 << (vector % 32))) { | |
a782a7e4 | 533 | desc = __this_cpu_read(vector_irq[vector]); |
5231a686 | 534 | |
09cf92b7 | 535 | raw_spin_lock(&desc->lock); |
51c43ac6 TG |
536 | data = irq_desc_get_irq_data(desc); |
537 | chip = irq_data_get_irq_chip(data); | |
9345005f | 538 | if (chip->irq_retrigger) { |
51c43ac6 | 539 | chip->irq_retrigger(data); |
9345005f PB |
540 | __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED); |
541 | } | |
239007b8 | 542 | raw_spin_unlock(&desc->lock); |
5231a686 | 543 | } |
9345005f | 544 | if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED) |
7276c6a2 | 545 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
5231a686 | 546 | } |
7a7732bc SS |
547 | } |
548 | #endif |