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Commit | Line | Data |
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6b39ba77 TG |
1 | /* |
2 | * Common interrupt code for 32 and 64 bit | |
3 | */ | |
4 | #include <linux/cpu.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/kernel_stat.h> | |
7 | #include <linux/seq_file.h> | |
6a02e710 | 8 | #include <linux/smp.h> |
7c1d7cdc | 9 | #include <linux/ftrace.h> |
6b39ba77 | 10 | |
7b6aa335 | 11 | #include <asm/apic.h> |
6b39ba77 | 12 | #include <asm/io_apic.h> |
c3d80000 | 13 | #include <asm/irq.h> |
7c1d7cdc | 14 | #include <asm/idle.h> |
01ca79f1 | 15 | #include <asm/mce.h> |
6b39ba77 TG |
16 | |
17 | atomic_t irq_err_count; | |
18 | ||
acaabe79 DS |
19 | /* Function pointer for generic interrupt vector handling */ |
20 | void (*generic_interrupt_extension)(void) = NULL; | |
21 | ||
249f6d9e TG |
22 | /* |
23 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
24 | * each architecture has to answer this themselves. | |
25 | */ | |
26 | void ack_bad_irq(unsigned int irq) | |
27 | { | |
edea7148 CG |
28 | if (printk_ratelimit()) |
29 | pr_err("unexpected IRQ trap at vector %02x\n", irq); | |
249f6d9e | 30 | |
249f6d9e TG |
31 | /* |
32 | * Currently unexpected vectors happen only on SMP and APIC. | |
33 | * We _must_ ack these because every local APIC has only N | |
34 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
35 | * holds up an irq slot - in excessive cases (when multiple | |
36 | * unexpected vectors occur) that might lock up the APIC | |
37 | * completely. | |
38 | * But only ack when the APIC is enabled -AK | |
39 | */ | |
08306ce6 | 40 | ack_APIC_irq(); |
249f6d9e TG |
41 | } |
42 | ||
1b437c8c | 43 | #define irq_stats(x) (&per_cpu(irq_stat, x)) |
6b39ba77 TG |
44 | /* |
45 | * /proc/interrupts printing: | |
46 | */ | |
7a81d9a7 | 47 | static int show_other_interrupts(struct seq_file *p, int prec) |
6b39ba77 TG |
48 | { |
49 | int j; | |
50 | ||
7a81d9a7 | 51 | seq_printf(p, "%*s: ", prec, "NMI"); |
6b39ba77 TG |
52 | for_each_online_cpu(j) |
53 | seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); | |
54 | seq_printf(p, " Non-maskable interrupts\n"); | |
55 | #ifdef CONFIG_X86_LOCAL_APIC | |
7a81d9a7 | 56 | seq_printf(p, "%*s: ", prec, "LOC"); |
6b39ba77 TG |
57 | for_each_online_cpu(j) |
58 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | |
59 | seq_printf(p, " Local timer interrupts\n"); | |
474e56b8 JSR |
60 | |
61 | seq_printf(p, "%*s: ", prec, "SPU"); | |
62 | for_each_online_cpu(j) | |
63 | seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); | |
64 | seq_printf(p, " Spurious interrupts\n"); | |
6b39ba77 | 65 | #endif |
acaabe79 | 66 | if (generic_interrupt_extension) { |
59d13812 | 67 | seq_printf(p, "%*s: ", prec, "PLT"); |
acaabe79 DS |
68 | for_each_online_cpu(j) |
69 | seq_printf(p, "%10u ", irq_stats(j)->generic_irqs); | |
70 | seq_printf(p, " Platform interrupts\n"); | |
71 | } | |
6b39ba77 | 72 | #ifdef CONFIG_SMP |
7a81d9a7 | 73 | seq_printf(p, "%*s: ", prec, "RES"); |
6b39ba77 TG |
74 | for_each_online_cpu(j) |
75 | seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); | |
76 | seq_printf(p, " Rescheduling interrupts\n"); | |
7a81d9a7 | 77 | seq_printf(p, "%*s: ", prec, "CAL"); |
6b39ba77 TG |
78 | for_each_online_cpu(j) |
79 | seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); | |
80 | seq_printf(p, " Function call interrupts\n"); | |
7a81d9a7 | 81 | seq_printf(p, "%*s: ", prec, "TLB"); |
6b39ba77 TG |
82 | for_each_online_cpu(j) |
83 | seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); | |
84 | seq_printf(p, " TLB shootdowns\n"); | |
85 | #endif | |
86 | #ifdef CONFIG_X86_MCE | |
7a81d9a7 | 87 | seq_printf(p, "%*s: ", prec, "TRM"); |
6b39ba77 TG |
88 | for_each_online_cpu(j) |
89 | seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); | |
90 | seq_printf(p, " Thermal event interrupts\n"); | |
4efc0670 | 91 | # ifdef CONFIG_X86_MCE_THRESHOLD |
7a81d9a7 | 92 | seq_printf(p, "%*s: ", prec, "THR"); |
6b39ba77 TG |
93 | for_each_online_cpu(j) |
94 | seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); | |
95 | seq_printf(p, " Threshold APIC interrupts\n"); | |
96 | # endif | |
01ca79f1 AK |
97 | #endif |
98 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
99 | seq_printf(p, "%*s: ", prec, "MCE"); | |
100 | for_each_online_cpu(j) | |
101 | seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); | |
102 | seq_printf(p, " Machine check exceptions\n"); | |
6b39ba77 | 103 | #endif |
7a81d9a7 | 104 | seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); |
6b39ba77 | 105 | #if defined(CONFIG_X86_IO_APIC) |
7a81d9a7 | 106 | seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); |
6b39ba77 TG |
107 | #endif |
108 | return 0; | |
109 | } | |
110 | ||
111 | int show_interrupts(struct seq_file *p, void *v) | |
112 | { | |
113 | unsigned long flags, any_count = 0; | |
7a81d9a7 | 114 | int i = *(loff_t *) v, j, prec; |
6b39ba77 TG |
115 | struct irqaction *action; |
116 | struct irq_desc *desc; | |
117 | ||
118 | if (i > nr_irqs) | |
119 | return 0; | |
120 | ||
7a81d9a7 JB |
121 | for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) |
122 | j *= 10; | |
123 | ||
6b39ba77 | 124 | if (i == nr_irqs) |
7a81d9a7 | 125 | return show_other_interrupts(p, prec); |
6b39ba77 TG |
126 | |
127 | /* print header */ | |
128 | if (i == 0) { | |
7a81d9a7 | 129 | seq_printf(p, "%*s", prec + 8, ""); |
6b39ba77 | 130 | for_each_online_cpu(j) |
e9f95e63 | 131 | seq_printf(p, "CPU%-8d", j); |
6b39ba77 TG |
132 | seq_putc(p, '\n'); |
133 | } | |
134 | ||
135 | desc = irq_to_desc(i); | |
0b8f1efa YL |
136 | if (!desc) |
137 | return 0; | |
138 | ||
6b39ba77 | 139 | spin_lock_irqsave(&desc->lock, flags); |
6b39ba77 TG |
140 | for_each_online_cpu(j) |
141 | any_count |= kstat_irqs_cpu(i, j); | |
6b39ba77 TG |
142 | action = desc->action; |
143 | if (!action && !any_count) | |
144 | goto out; | |
145 | ||
7a81d9a7 | 146 | seq_printf(p, "%*d: ", prec, i); |
6b39ba77 TG |
147 | for_each_online_cpu(j) |
148 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | |
6b39ba77 TG |
149 | seq_printf(p, " %8s", desc->chip->name); |
150 | seq_printf(p, "-%-8s", desc->name); | |
151 | ||
152 | if (action) { | |
153 | seq_printf(p, " %s", action->name); | |
154 | while ((action = action->next) != NULL) | |
155 | seq_printf(p, ", %s", action->name); | |
156 | } | |
157 | ||
158 | seq_putc(p, '\n'); | |
159 | out: | |
160 | spin_unlock_irqrestore(&desc->lock, flags); | |
161 | return 0; | |
162 | } | |
163 | ||
164 | /* | |
165 | * /proc/stat helpers | |
166 | */ | |
167 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
168 | { | |
169 | u64 sum = irq_stats(cpu)->__nmi_count; | |
170 | ||
01ca79f1 AK |
171 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) |
172 | sum += per_cpu(mce_exception_count, cpu); | |
173 | #endif | |
6b39ba77 TG |
174 | #ifdef CONFIG_X86_LOCAL_APIC |
175 | sum += irq_stats(cpu)->apic_timer_irqs; | |
474e56b8 | 176 | sum += irq_stats(cpu)->irq_spurious_count; |
6b39ba77 | 177 | #endif |
acaabe79 DS |
178 | if (generic_interrupt_extension) |
179 | sum += irq_stats(cpu)->generic_irqs; | |
6b39ba77 TG |
180 | #ifdef CONFIG_SMP |
181 | sum += irq_stats(cpu)->irq_resched_count; | |
182 | sum += irq_stats(cpu)->irq_call_count; | |
183 | sum += irq_stats(cpu)->irq_tlb_count; | |
184 | #endif | |
185 | #ifdef CONFIG_X86_MCE | |
186 | sum += irq_stats(cpu)->irq_thermal_count; | |
4efc0670 | 187 | # ifdef CONFIG_X86_MCE_THRESHOLD |
6b39ba77 | 188 | sum += irq_stats(cpu)->irq_threshold_count; |
edea7148 | 189 | # endif |
6b39ba77 TG |
190 | #endif |
191 | return sum; | |
192 | } | |
193 | ||
194 | u64 arch_irq_stat(void) | |
195 | { | |
196 | u64 sum = atomic_read(&irq_err_count); | |
197 | ||
198 | #ifdef CONFIG_X86_IO_APIC | |
199 | sum += atomic_read(&irq_mis_count); | |
200 | #endif | |
201 | return sum; | |
202 | } | |
c3d80000 | 203 | |
7c1d7cdc JF |
204 | |
205 | /* | |
206 | * do_IRQ handles all normal device IRQ's (the special | |
207 | * SMP cross-CPU interrupts have their own specific | |
208 | * handlers). | |
209 | */ | |
210 | unsigned int __irq_entry do_IRQ(struct pt_regs *regs) | |
211 | { | |
212 | struct pt_regs *old_regs = set_irq_regs(regs); | |
213 | ||
214 | /* high bit used in ret_from_ code */ | |
215 | unsigned vector = ~regs->orig_ax; | |
216 | unsigned irq; | |
217 | ||
218 | exit_idle(); | |
219 | irq_enter(); | |
220 | ||
221 | irq = __get_cpu_var(vector_irq)[vector]; | |
222 | ||
223 | if (!handle_irq(irq, regs)) { | |
08306ce6 | 224 | ack_APIC_irq(); |
7c1d7cdc JF |
225 | |
226 | if (printk_ratelimit()) | |
edea7148 CG |
227 | pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n", |
228 | __func__, smp_processor_id(), vector, irq); | |
7c1d7cdc JF |
229 | } |
230 | ||
231 | irq_exit(); | |
232 | ||
233 | set_irq_regs(old_regs); | |
234 | return 1; | |
235 | } | |
236 | ||
acaabe79 DS |
237 | /* |
238 | * Handler for GENERIC_INTERRUPT_VECTOR. | |
239 | */ | |
240 | void smp_generic_interrupt(struct pt_regs *regs) | |
241 | { | |
242 | struct pt_regs *old_regs = set_irq_regs(regs); | |
243 | ||
244 | ack_APIC_irq(); | |
245 | ||
246 | exit_idle(); | |
247 | ||
248 | irq_enter(); | |
249 | ||
250 | inc_irq_stat(generic_irqs); | |
251 | ||
252 | if (generic_interrupt_extension) | |
253 | generic_interrupt_extension(); | |
254 | ||
255 | irq_exit(); | |
256 | ||
257 | set_irq_regs(old_regs); | |
258 | } | |
259 | ||
c3d80000 | 260 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |