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CommitLineData
6b39ba77
TG
1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
4722d194 7#include <linux/of.h>
6b39ba77 8#include <linux/seq_file.h>
6a02e710 9#include <linux/smp.h>
7c1d7cdc 10#include <linux/ftrace.h>
ca444564 11#include <linux/delay.h>
69c60c88 12#include <linux/export.h>
6b39ba77 13
7b6aa335 14#include <asm/apic.h>
6b39ba77 15#include <asm/io_apic.h>
c3d80000 16#include <asm/irq.h>
01ca79f1 17#include <asm/mce.h>
2c1b284e 18#include <asm/hw_irq.h>
ac2a5539 19#include <asm/desc.h>
83ab8514
SRRH
20
21#define CREATE_TRACE_POINTS
cf910e83 22#include <asm/trace/irq_vectors.h>
6b39ba77 23
c5bde906
BG
24DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
25EXPORT_PER_CPU_SYMBOL(irq_stat);
26
27DEFINE_PER_CPU(struct pt_regs *, irq_regs);
28EXPORT_PER_CPU_SYMBOL(irq_regs);
29
6b39ba77
TG
30atomic_t irq_err_count;
31
249f6d9e
TG
32/*
33 * 'what should we do if we get a hw irq event on an illegal vector'.
34 * each architecture has to answer this themselves.
35 */
36void ack_bad_irq(unsigned int irq)
37{
edea7148
CG
38 if (printk_ratelimit())
39 pr_err("unexpected IRQ trap at vector %02x\n", irq);
249f6d9e 40
249f6d9e
TG
41 /*
42 * Currently unexpected vectors happen only on SMP and APIC.
43 * We _must_ ack these because every local APIC has only N
44 * irq slots per priority level, and a 'hanging, unacked' IRQ
45 * holds up an irq slot - in excessive cases (when multiple
46 * unexpected vectors occur) that might lock up the APIC
47 * completely.
48 * But only ack when the APIC is enabled -AK
49 */
08306ce6 50 ack_APIC_irq();
249f6d9e
TG
51}
52
1b437c8c 53#define irq_stats(x) (&per_cpu(irq_stat, x))
6b39ba77 54/*
517e4981 55 * /proc/interrupts printing for arch specific interrupts
6b39ba77 56 */
517e4981 57int arch_show_interrupts(struct seq_file *p, int prec)
6b39ba77
TG
58{
59 int j;
60
7a81d9a7 61 seq_printf(p, "%*s: ", prec, "NMI");
6b39ba77
TG
62 for_each_online_cpu(j)
63 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
3736708f 64 seq_puts(p, " Non-maskable interrupts\n");
6b39ba77 65#ifdef CONFIG_X86_LOCAL_APIC
7a81d9a7 66 seq_printf(p, "%*s: ", prec, "LOC");
6b39ba77
TG
67 for_each_online_cpu(j)
68 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
3736708f 69 seq_puts(p, " Local timer interrupts\n");
474e56b8
JSR
70
71 seq_printf(p, "%*s: ", prec, "SPU");
72 for_each_online_cpu(j)
73 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
3736708f 74 seq_puts(p, " Spurious interrupts\n");
89ccf465 75 seq_printf(p, "%*s: ", prec, "PMI");
241771ef
IM
76 for_each_online_cpu(j)
77 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
3736708f 78 seq_puts(p, " Performance monitoring interrupts\n");
e360adbe 79 seq_printf(p, "%*s: ", prec, "IWI");
b6276f35 80 for_each_online_cpu(j)
e360adbe 81 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
3736708f 82 seq_puts(p, " IRQ work interrupts\n");
346b46be
FLVC
83 seq_printf(p, "%*s: ", prec, "RTR");
84 for_each_online_cpu(j)
b49d7d87 85 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
3736708f 86 seq_puts(p, " APIC ICR read retries\n");
4a4de9c7 87 if (x86_platform_ipi_callback) {
59d13812 88 seq_printf(p, "%*s: ", prec, "PLT");
acaabe79 89 for_each_online_cpu(j)
4a4de9c7 90 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
3736708f 91 seq_puts(p, " Platform interrupts\n");
acaabe79 92 }
0428e01a 93#endif
6b39ba77 94#ifdef CONFIG_SMP
7a81d9a7 95 seq_printf(p, "%*s: ", prec, "RES");
6b39ba77
TG
96 for_each_online_cpu(j)
97 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
3736708f 98 seq_puts(p, " Rescheduling interrupts\n");
7a81d9a7 99 seq_printf(p, "%*s: ", prec, "CAL");
6b39ba77 100 for_each_online_cpu(j)
82ba4fac 101 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
3736708f 102 seq_puts(p, " Function call interrupts\n");
7a81d9a7 103 seq_printf(p, "%*s: ", prec, "TLB");
6b39ba77
TG
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
3736708f 106 seq_puts(p, " TLB shootdowns\n");
6b39ba77 107#endif
0444c9bd 108#ifdef CONFIG_X86_THERMAL_VECTOR
7a81d9a7 109 seq_printf(p, "%*s: ", prec, "TRM");
6b39ba77
TG
110 for_each_online_cpu(j)
111 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
3736708f 112 seq_puts(p, " Thermal event interrupts\n");
0444c9bd
JB
113#endif
114#ifdef CONFIG_X86_MCE_THRESHOLD
7a81d9a7 115 seq_printf(p, "%*s: ", prec, "THR");
6b39ba77
TG
116 for_each_online_cpu(j)
117 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
3736708f 118 seq_puts(p, " Threshold APIC interrupts\n");
01ca79f1 119#endif
24fd78a8
AG
120#ifdef CONFIG_X86_MCE_AMD
121 seq_printf(p, "%*s: ", prec, "DFR");
122 for_each_online_cpu(j)
123 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
124 seq_puts(p, " Deferred Error APIC interrupts\n");
125#endif
c1ebf835 126#ifdef CONFIG_X86_MCE
01ca79f1
AK
127 seq_printf(p, "%*s: ", prec, "MCE");
128 for_each_online_cpu(j)
129 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
3736708f 130 seq_puts(p, " Machine check exceptions\n");
ca84f696
AK
131 seq_printf(p, "%*s: ", prec, "MCP");
132 for_each_online_cpu(j)
133 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
3736708f 134 seq_puts(p, " Machine check polls\n");
6b39ba77 135#endif
f704a7d7 136#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
7854f822 137 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
9d87cd61
VK
138 seq_printf(p, "%*s: ", prec, "HYP");
139 for_each_online_cpu(j)
140 seq_printf(p, "%10u ",
141 irq_stats(j)->irq_hv_callback_count);
142 seq_puts(p, " Hypervisor callback interrupts\n");
143 }
929320e4 144#endif
7a81d9a7 145 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
6b39ba77 146#if defined(CONFIG_X86_IO_APIC)
7a81d9a7 147 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
501b3265
FW
148#endif
149#ifdef CONFIG_HAVE_KVM
150 seq_printf(p, "%*s: ", prec, "PIN");
151 for_each_online_cpu(j)
152 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
153 seq_puts(p, " Posted-interrupt notification event\n");
154
210f84b0
WV
155 seq_printf(p, "%*s: ", prec, "NPI");
156 for_each_online_cpu(j)
157 seq_printf(p, "%10u ",
158 irq_stats(j)->kvm_posted_intr_nested_ipis);
159 seq_puts(p, " Nested posted-interrupt event\n");
160
501b3265
FW
161 seq_printf(p, "%*s: ", prec, "PIW");
162 for_each_online_cpu(j)
163 seq_printf(p, "%10u ",
164 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
165 seq_puts(p, " Posted-interrupt wakeup event\n");
6b39ba77
TG
166#endif
167 return 0;
168}
169
6b39ba77
TG
170/*
171 * /proc/stat helpers
172 */
173u64 arch_irq_stat_cpu(unsigned int cpu)
174{
175 u64 sum = irq_stats(cpu)->__nmi_count;
176
177#ifdef CONFIG_X86_LOCAL_APIC
178 sum += irq_stats(cpu)->apic_timer_irqs;
474e56b8 179 sum += irq_stats(cpu)->irq_spurious_count;
241771ef 180 sum += irq_stats(cpu)->apic_perf_irqs;
e360adbe 181 sum += irq_stats(cpu)->apic_irq_work_irqs;
b49d7d87 182 sum += irq_stats(cpu)->icr_read_retry_count;
4a4de9c7
DS
183 if (x86_platform_ipi_callback)
184 sum += irq_stats(cpu)->x86_platform_ipis;
0428e01a 185#endif
6b39ba77
TG
186#ifdef CONFIG_SMP
187 sum += irq_stats(cpu)->irq_resched_count;
188 sum += irq_stats(cpu)->irq_call_count;
6b39ba77 189#endif
0444c9bd 190#ifdef CONFIG_X86_THERMAL_VECTOR
6b39ba77 191 sum += irq_stats(cpu)->irq_thermal_count;
0444c9bd
JB
192#endif
193#ifdef CONFIG_X86_MCE_THRESHOLD
6b39ba77 194 sum += irq_stats(cpu)->irq_threshold_count;
8051dbd2 195#endif
c1ebf835 196#ifdef CONFIG_X86_MCE
8051dbd2
HS
197 sum += per_cpu(mce_exception_count, cpu);
198 sum += per_cpu(mce_poll_count, cpu);
6b39ba77
TG
199#endif
200 return sum;
201}
202
203u64 arch_irq_stat(void)
204{
205 u64 sum = atomic_read(&irq_err_count);
6b39ba77
TG
206 return sum;
207}
c3d80000 208
7c1d7cdc
JF
209
210/*
211 * do_IRQ handles all normal device IRQ's (the special
212 * SMP cross-CPU interrupts have their own specific
213 * handlers).
214 */
1d9090e2 215__visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
7c1d7cdc
JF
216{
217 struct pt_regs *old_regs = set_irq_regs(regs);
a782a7e4 218 struct irq_desc * desc;
7c1d7cdc
JF
219 /* high bit used in ret_from_ code */
220 unsigned vector = ~regs->orig_ax;
7c1d7cdc 221
0333a209
AL
222 /*
223 * NB: Unlike exception entries, IRQ entries do not reliably
224 * handle context tracking in the low-level entry code. This is
225 * because syscall entries execute briefly with IRQs on before
226 * updating context tracking state, so we can take an IRQ from
227 * kernel mode with CONTEXT_USER. The low-level entry code only
228 * updates the context if we came from user mode, so we won't
229 * switch to CONTEXT_KERNEL. We'll fix that once the syscall
230 * code is cleaned up enough that we can cleanly defer enabling
231 * IRQs.
232 */
233
6af7faf6 234 entering_irq();
7c1d7cdc 235
0333a209 236 /* entering_irq() tells RCU that we're not quiescent. Check it. */
5778077d 237 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
0333a209 238
a782a7e4 239 desc = __this_cpu_read(vector_irq[vector]);
7c1d7cdc 240
a782a7e4 241 if (!handle_irq(desc, regs)) {
08306ce6 242 ack_APIC_irq();
7c1d7cdc 243
a782a7e4
TG
244 if (desc != VECTOR_RETRIGGERED) {
245 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
9345005f 246 __func__, smp_processor_id(),
a782a7e4 247 vector);
9345005f 248 } else {
7276c6a2 249 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
9345005f 250 }
7c1d7cdc
JF
251 }
252
6af7faf6 253 exiting_irq();
7c1d7cdc
JF
254
255 set_irq_regs(old_regs);
256 return 1;
257}
258
0428e01a
TG
259#ifdef CONFIG_X86_LOCAL_APIC
260/* Function pointer for generic interrupt vector handling */
261void (*x86_platform_ipi_callback)(void) = NULL;
acaabe79 262/*
4a4de9c7 263 * Handler for X86_PLATFORM_IPI_VECTOR.
acaabe79 264 */
c4158ff5 265__visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
eddc0e92
SA
266{
267 struct pt_regs *old_regs = set_irq_regs(regs);
acaabe79 268
eddc0e92 269 entering_ack_irq();
8a17116b
TG
270 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
271 inc_irq_stat(x86_platform_ipis);
272 if (x86_platform_ipi_callback)
273 x86_platform_ipi_callback();
274 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
eddc0e92 275 exiting_irq();
acaabe79
DS
276 set_irq_regs(old_regs);
277}
0428e01a 278#endif
acaabe79 279
d78f2664 280#ifdef CONFIG_HAVE_KVM
f6b3c72c
FW
281static void dummy_handler(void) {}
282static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
283
284void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
285{
286 if (handler)
287 kvm_posted_intr_wakeup_handler = handler;
288 else
289 kvm_posted_intr_wakeup_handler = dummy_handler;
290}
291EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
292
d78f2664
YZ
293/*
294 * Handler for POSTED_INTERRUPT_VECTOR.
295 */
1d9090e2 296__visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
d78f2664
YZ
297{
298 struct pt_regs *old_regs = set_irq_regs(regs);
299
6af7faf6 300 entering_ack_irq();
d78f2664 301 inc_irq_stat(kvm_posted_intr_ipis);
f6b3c72c
FW
302 exiting_irq();
303 set_irq_regs(old_regs);
304}
305
306/*
307 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
308 */
309__visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
310{
311 struct pt_regs *old_regs = set_irq_regs(regs);
312
313 entering_ack_irq();
314 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
315 kvm_posted_intr_wakeup_handler();
6af7faf6 316 exiting_irq();
d78f2664
YZ
317 set_irq_regs(old_regs);
318}
210f84b0
WV
319
320/*
321 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
322 */
323__visible void smp_kvm_posted_intr_nested_ipi(struct pt_regs *regs)
324{
325 struct pt_regs *old_regs = set_irq_regs(regs);
326
327 entering_ack_irq();
328 inc_irq_stat(kvm_posted_intr_nested_ipis);
329 exiting_irq();
330 set_irq_regs(old_regs);
331}
d78f2664
YZ
332#endif
333
cf910e83 334
7a7732bc
SS
335#ifdef CONFIG_HOTPLUG_CPU
336/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
337void fixup_irqs(void)
338{
ad7a929f 339 unsigned int irr, vector;
7a7732bc 340 struct irq_desc *desc;
a3c08e5d 341 struct irq_data *data;
51c43ac6 342 struct irq_chip *chip;
7a7732bc 343
ad7a929f 344 irq_migrate_all_off_this_cpu();
7a7732bc 345
5231a686
SS
346 /*
347 * We can remove mdelay() and then send spuriuous interrupts to
348 * new cpu targets for all the irqs that were handled previously by
349 * this cpu. While it works, I have seen spurious interrupt messages
350 * (nothing wrong but still...).
351 *
352 * So for now, retain mdelay(1) and check the IRR and then send those
353 * interrupts to new targets as this cpu is already offlined...
354 */
7a7732bc 355 mdelay(1);
5231a686 356
09cf92b7
TG
357 /*
358 * We can walk the vector array of this cpu without holding
359 * vector_lock because the cpu is already marked !online, so
360 * nothing else will touch it.
361 */
5231a686 362 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
a782a7e4 363 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
5231a686
SS
364 continue;
365
366 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
367 if (irr & (1 << (vector % 32))) {
a782a7e4 368 desc = __this_cpu_read(vector_irq[vector]);
5231a686 369
09cf92b7 370 raw_spin_lock(&desc->lock);
51c43ac6
TG
371 data = irq_desc_get_irq_data(desc);
372 chip = irq_data_get_irq_chip(data);
9345005f 373 if (chip->irq_retrigger) {
51c43ac6 374 chip->irq_retrigger(data);
9345005f
PB
375 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
376 }
239007b8 377 raw_spin_unlock(&desc->lock);
5231a686 378 }
9345005f 379 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
7276c6a2 380 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
5231a686 381 }
7a7732bc
SS
382}
383#endif