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perf_counter: generalize pending infrastructure
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CommitLineData
6b39ba77
TG
1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/seq_file.h>
6a02e710 8#include <linux/smp.h>
7c1d7cdc 9#include <linux/ftrace.h>
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TG
10
11#include <asm/apic.h>
12#include <asm/io_apic.h>
c3d80000 13#include <asm/irq.h>
7c1d7cdc 14#include <asm/idle.h>
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15
16atomic_t irq_err_count;
17
acaabe79
DS
18/* Function pointer for generic interrupt vector handling */
19void (*generic_interrupt_extension)(void) = NULL;
20
249f6d9e
TG
21/*
22 * 'what should we do if we get a hw irq event on an illegal vector'.
23 * each architecture has to answer this themselves.
24 */
25void ack_bad_irq(unsigned int irq)
26{
27 printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);
28
29#ifdef CONFIG_X86_LOCAL_APIC
30 /*
31 * Currently unexpected vectors happen only on SMP and APIC.
32 * We _must_ ack these because every local APIC has only N
33 * irq slots per priority level, and a 'hanging, unacked' IRQ
34 * holds up an irq slot - in excessive cases (when multiple
35 * unexpected vectors occur) that might lock up the APIC
36 * completely.
37 * But only ack when the APIC is enabled -AK
38 */
39 if (cpu_has_apic)
40 ack_APIC_irq();
41#endif
42}
43
1b437c8c 44#define irq_stats(x) (&per_cpu(irq_stat, x))
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45/*
46 * /proc/interrupts printing:
47 */
7a81d9a7 48static int show_other_interrupts(struct seq_file *p, int prec)
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49{
50 int j;
51
7a81d9a7 52 seq_printf(p, "%*s: ", prec, "NMI");
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53 for_each_online_cpu(j)
54 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
55 seq_printf(p, " Non-maskable interrupts\n");
56#ifdef CONFIG_X86_LOCAL_APIC
7a81d9a7 57 seq_printf(p, "%*s: ", prec, "LOC");
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58 for_each_online_cpu(j)
59 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
60 seq_printf(p, " Local timer interrupts\n");
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JSR
61
62 seq_printf(p, "%*s: ", prec, "SPU");
63 for_each_online_cpu(j)
64 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
65 seq_printf(p, " Spurious interrupts\n");
241771ef
IM
66 seq_printf(p, "CNT: ");
67 for_each_online_cpu(j)
68 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
69 seq_printf(p, " Performance counter interrupts\n");
6b39ba77 70#endif
acaabe79
DS
71 if (generic_interrupt_extension) {
72 seq_printf(p, "PLT: ");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->generic_irqs);
75 seq_printf(p, " Platform interrupts\n");
76 }
6b39ba77 77#ifdef CONFIG_SMP
7a81d9a7 78 seq_printf(p, "%*s: ", prec, "RES");
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79 for_each_online_cpu(j)
80 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
81 seq_printf(p, " Rescheduling interrupts\n");
7a81d9a7 82 seq_printf(p, "%*s: ", prec, "CAL");
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83 for_each_online_cpu(j)
84 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
85 seq_printf(p, " Function call interrupts\n");
7a81d9a7 86 seq_printf(p, "%*s: ", prec, "TLB");
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87 for_each_online_cpu(j)
88 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
89 seq_printf(p, " TLB shootdowns\n");
90#endif
91#ifdef CONFIG_X86_MCE
7a81d9a7 92 seq_printf(p, "%*s: ", prec, "TRM");
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93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
95 seq_printf(p, " Thermal event interrupts\n");
96# ifdef CONFIG_X86_64
7a81d9a7 97 seq_printf(p, "%*s: ", prec, "THR");
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98 for_each_online_cpu(j)
99 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
100 seq_printf(p, " Threshold APIC interrupts\n");
101# endif
102#endif
7a81d9a7 103 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
6b39ba77 104#if defined(CONFIG_X86_IO_APIC)
7a81d9a7 105 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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106#endif
107 return 0;
108}
109
110int show_interrupts(struct seq_file *p, void *v)
111{
112 unsigned long flags, any_count = 0;
7a81d9a7 113 int i = *(loff_t *) v, j, prec;
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114 struct irqaction *action;
115 struct irq_desc *desc;
116
117 if (i > nr_irqs)
118 return 0;
119
7a81d9a7
JB
120 for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
121 j *= 10;
122
6b39ba77 123 if (i == nr_irqs)
7a81d9a7 124 return show_other_interrupts(p, prec);
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125
126 /* print header */
127 if (i == 0) {
7a81d9a7 128 seq_printf(p, "%*s", prec + 8, "");
6b39ba77 129 for_each_online_cpu(j)
e9f95e63 130 seq_printf(p, "CPU%-8d", j);
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131 seq_putc(p, '\n');
132 }
133
134 desc = irq_to_desc(i);
0b8f1efa
YL
135 if (!desc)
136 return 0;
137
6b39ba77 138 spin_lock_irqsave(&desc->lock, flags);
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139 for_each_online_cpu(j)
140 any_count |= kstat_irqs_cpu(i, j);
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141 action = desc->action;
142 if (!action && !any_count)
143 goto out;
144
7a81d9a7 145 seq_printf(p, "%*d: ", prec, i);
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146 for_each_online_cpu(j)
147 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
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148 seq_printf(p, " %8s", desc->chip->name);
149 seq_printf(p, "-%-8s", desc->name);
150
151 if (action) {
152 seq_printf(p, " %s", action->name);
153 while ((action = action->next) != NULL)
154 seq_printf(p, ", %s", action->name);
155 }
156
157 seq_putc(p, '\n');
158out:
159 spin_unlock_irqrestore(&desc->lock, flags);
160 return 0;
161}
162
163/*
164 * /proc/stat helpers
165 */
166u64 arch_irq_stat_cpu(unsigned int cpu)
167{
168 u64 sum = irq_stats(cpu)->__nmi_count;
169
170#ifdef CONFIG_X86_LOCAL_APIC
171 sum += irq_stats(cpu)->apic_timer_irqs;
474e56b8 172 sum += irq_stats(cpu)->irq_spurious_count;
241771ef 173 sum += irq_stats(cpu)->apic_perf_irqs;
6b39ba77 174#endif
acaabe79
DS
175 if (generic_interrupt_extension)
176 sum += irq_stats(cpu)->generic_irqs;
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177#ifdef CONFIG_SMP
178 sum += irq_stats(cpu)->irq_resched_count;
179 sum += irq_stats(cpu)->irq_call_count;
180 sum += irq_stats(cpu)->irq_tlb_count;
181#endif
182#ifdef CONFIG_X86_MCE
183 sum += irq_stats(cpu)->irq_thermal_count;
184# ifdef CONFIG_X86_64
185 sum += irq_stats(cpu)->irq_threshold_count;
186#endif
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TG
187#endif
188 return sum;
189}
190
191u64 arch_irq_stat(void)
192{
193 u64 sum = atomic_read(&irq_err_count);
194
195#ifdef CONFIG_X86_IO_APIC
196 sum += atomic_read(&irq_mis_count);
197#endif
198 return sum;
199}
c3d80000 200
7c1d7cdc
JF
201
202/*
203 * do_IRQ handles all normal device IRQ's (the special
204 * SMP cross-CPU interrupts have their own specific
205 * handlers).
206 */
207unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
208{
209 struct pt_regs *old_regs = set_irq_regs(regs);
210
211 /* high bit used in ret_from_ code */
212 unsigned vector = ~regs->orig_ax;
213 unsigned irq;
214
215 exit_idle();
216 irq_enter();
217
218 irq = __get_cpu_var(vector_irq)[vector];
219
220 if (!handle_irq(irq, regs)) {
221#ifdef CONFIG_X86_64
222 if (!disable_apic)
223 ack_APIC_irq();
224#endif
225
226 if (printk_ratelimit())
227 printk(KERN_EMERG "%s: %d.%d No irq handler for vector (irq %d)\n",
228 __func__, smp_processor_id(), vector, irq);
229 }
230
231 irq_exit();
232
233 set_irq_regs(old_regs);
234 return 1;
235}
236
acaabe79
DS
237/*
238 * Handler for GENERIC_INTERRUPT_VECTOR.
239 */
240void smp_generic_interrupt(struct pt_regs *regs)
241{
242 struct pt_regs *old_regs = set_irq_regs(regs);
243
244 ack_APIC_irq();
245
246 exit_idle();
247
248 irq_enter();
249
250 inc_irq_stat(generic_irqs);
251
252 if (generic_interrupt_extension)
253 generic_interrupt_extension();
254
255 irq_exit();
256
257 set_irq_regs(old_regs);
258}
259
c3d80000 260EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);