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Merge tag 'ntb-4.13-bugfixes' of git://github.com/jonmason/ntb
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / irq.c
CommitLineData
6b39ba77
TG
1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
4722d194 7#include <linux/of.h>
6b39ba77 8#include <linux/seq_file.h>
6a02e710 9#include <linux/smp.h>
7c1d7cdc 10#include <linux/ftrace.h>
ca444564 11#include <linux/delay.h>
69c60c88 12#include <linux/export.h>
6b39ba77 13
7b6aa335 14#include <asm/apic.h>
6b39ba77 15#include <asm/io_apic.h>
c3d80000 16#include <asm/irq.h>
01ca79f1 17#include <asm/mce.h>
2c1b284e 18#include <asm/hw_irq.h>
ac2a5539 19#include <asm/desc.h>
83ab8514
SRRH
20
21#define CREATE_TRACE_POINTS
cf910e83 22#include <asm/trace/irq_vectors.h>
6b39ba77 23
c5bde906
BG
24DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
25EXPORT_PER_CPU_SYMBOL(irq_stat);
26
27DEFINE_PER_CPU(struct pt_regs *, irq_regs);
28EXPORT_PER_CPU_SYMBOL(irq_regs);
29
6b39ba77
TG
30atomic_t irq_err_count;
31
acaabe79 32/* Function pointer for generic interrupt vector handling */
4a4de9c7 33void (*x86_platform_ipi_callback)(void) = NULL;
acaabe79 34
249f6d9e
TG
35/*
36 * 'what should we do if we get a hw irq event on an illegal vector'.
37 * each architecture has to answer this themselves.
38 */
39void ack_bad_irq(unsigned int irq)
40{
edea7148
CG
41 if (printk_ratelimit())
42 pr_err("unexpected IRQ trap at vector %02x\n", irq);
249f6d9e 43
249f6d9e
TG
44 /*
45 * Currently unexpected vectors happen only on SMP and APIC.
46 * We _must_ ack these because every local APIC has only N
47 * irq slots per priority level, and a 'hanging, unacked' IRQ
48 * holds up an irq slot - in excessive cases (when multiple
49 * unexpected vectors occur) that might lock up the APIC
50 * completely.
51 * But only ack when the APIC is enabled -AK
52 */
08306ce6 53 ack_APIC_irq();
249f6d9e
TG
54}
55
1b437c8c 56#define irq_stats(x) (&per_cpu(irq_stat, x))
6b39ba77 57/*
517e4981 58 * /proc/interrupts printing for arch specific interrupts
6b39ba77 59 */
517e4981 60int arch_show_interrupts(struct seq_file *p, int prec)
6b39ba77
TG
61{
62 int j;
63
7a81d9a7 64 seq_printf(p, "%*s: ", prec, "NMI");
6b39ba77
TG
65 for_each_online_cpu(j)
66 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
3736708f 67 seq_puts(p, " Non-maskable interrupts\n");
6b39ba77 68#ifdef CONFIG_X86_LOCAL_APIC
7a81d9a7 69 seq_printf(p, "%*s: ", prec, "LOC");
6b39ba77
TG
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
3736708f 72 seq_puts(p, " Local timer interrupts\n");
474e56b8
JSR
73
74 seq_printf(p, "%*s: ", prec, "SPU");
75 for_each_online_cpu(j)
76 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
3736708f 77 seq_puts(p, " Spurious interrupts\n");
89ccf465 78 seq_printf(p, "%*s: ", prec, "PMI");
241771ef
IM
79 for_each_online_cpu(j)
80 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
3736708f 81 seq_puts(p, " Performance monitoring interrupts\n");
e360adbe 82 seq_printf(p, "%*s: ", prec, "IWI");
b6276f35 83 for_each_online_cpu(j)
e360adbe 84 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
3736708f 85 seq_puts(p, " IRQ work interrupts\n");
346b46be
FLVC
86 seq_printf(p, "%*s: ", prec, "RTR");
87 for_each_online_cpu(j)
b49d7d87 88 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
3736708f 89 seq_puts(p, " APIC ICR read retries\n");
6b39ba77 90#endif
4a4de9c7 91 if (x86_platform_ipi_callback) {
59d13812 92 seq_printf(p, "%*s: ", prec, "PLT");
acaabe79 93 for_each_online_cpu(j)
4a4de9c7 94 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
3736708f 95 seq_puts(p, " Platform interrupts\n");
acaabe79 96 }
6b39ba77 97#ifdef CONFIG_SMP
7a81d9a7 98 seq_printf(p, "%*s: ", prec, "RES");
6b39ba77
TG
99 for_each_online_cpu(j)
100 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
3736708f 101 seq_puts(p, " Rescheduling interrupts\n");
7a81d9a7 102 seq_printf(p, "%*s: ", prec, "CAL");
6b39ba77 103 for_each_online_cpu(j)
82ba4fac 104 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
3736708f 105 seq_puts(p, " Function call interrupts\n");
7a81d9a7 106 seq_printf(p, "%*s: ", prec, "TLB");
6b39ba77
TG
107 for_each_online_cpu(j)
108 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
3736708f 109 seq_puts(p, " TLB shootdowns\n");
6b39ba77 110#endif
0444c9bd 111#ifdef CONFIG_X86_THERMAL_VECTOR
7a81d9a7 112 seq_printf(p, "%*s: ", prec, "TRM");
6b39ba77
TG
113 for_each_online_cpu(j)
114 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
3736708f 115 seq_puts(p, " Thermal event interrupts\n");
0444c9bd
JB
116#endif
117#ifdef CONFIG_X86_MCE_THRESHOLD
7a81d9a7 118 seq_printf(p, "%*s: ", prec, "THR");
6b39ba77
TG
119 for_each_online_cpu(j)
120 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
3736708f 121 seq_puts(p, " Threshold APIC interrupts\n");
01ca79f1 122#endif
24fd78a8
AG
123#ifdef CONFIG_X86_MCE_AMD
124 seq_printf(p, "%*s: ", prec, "DFR");
125 for_each_online_cpu(j)
126 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
127 seq_puts(p, " Deferred Error APIC interrupts\n");
128#endif
c1ebf835 129#ifdef CONFIG_X86_MCE
01ca79f1
AK
130 seq_printf(p, "%*s: ", prec, "MCE");
131 for_each_online_cpu(j)
132 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
3736708f 133 seq_puts(p, " Machine check exceptions\n");
ca84f696
AK
134 seq_printf(p, "%*s: ", prec, "MCP");
135 for_each_online_cpu(j)
136 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
3736708f 137 seq_puts(p, " Machine check polls\n");
6b39ba77 138#endif
f704a7d7 139#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
9d87cd61
VK
140 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
141 seq_printf(p, "%*s: ", prec, "HYP");
142 for_each_online_cpu(j)
143 seq_printf(p, "%10u ",
144 irq_stats(j)->irq_hv_callback_count);
145 seq_puts(p, " Hypervisor callback interrupts\n");
146 }
929320e4 147#endif
7a81d9a7 148 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
6b39ba77 149#if defined(CONFIG_X86_IO_APIC)
7a81d9a7 150 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
501b3265
FW
151#endif
152#ifdef CONFIG_HAVE_KVM
153 seq_printf(p, "%*s: ", prec, "PIN");
154 for_each_online_cpu(j)
155 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
156 seq_puts(p, " Posted-interrupt notification event\n");
157
210f84b0
WV
158 seq_printf(p, "%*s: ", prec, "NPI");
159 for_each_online_cpu(j)
160 seq_printf(p, "%10u ",
161 irq_stats(j)->kvm_posted_intr_nested_ipis);
162 seq_puts(p, " Nested posted-interrupt event\n");
163
501b3265
FW
164 seq_printf(p, "%*s: ", prec, "PIW");
165 for_each_online_cpu(j)
166 seq_printf(p, "%10u ",
167 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
168 seq_puts(p, " Posted-interrupt wakeup event\n");
6b39ba77
TG
169#endif
170 return 0;
171}
172
6b39ba77
TG
173/*
174 * /proc/stat helpers
175 */
176u64 arch_irq_stat_cpu(unsigned int cpu)
177{
178 u64 sum = irq_stats(cpu)->__nmi_count;
179
180#ifdef CONFIG_X86_LOCAL_APIC
181 sum += irq_stats(cpu)->apic_timer_irqs;
474e56b8 182 sum += irq_stats(cpu)->irq_spurious_count;
241771ef 183 sum += irq_stats(cpu)->apic_perf_irqs;
e360adbe 184 sum += irq_stats(cpu)->apic_irq_work_irqs;
b49d7d87 185 sum += irq_stats(cpu)->icr_read_retry_count;
6b39ba77 186#endif
4a4de9c7
DS
187 if (x86_platform_ipi_callback)
188 sum += irq_stats(cpu)->x86_platform_ipis;
6b39ba77
TG
189#ifdef CONFIG_SMP
190 sum += irq_stats(cpu)->irq_resched_count;
191 sum += irq_stats(cpu)->irq_call_count;
6b39ba77 192#endif
0444c9bd 193#ifdef CONFIG_X86_THERMAL_VECTOR
6b39ba77 194 sum += irq_stats(cpu)->irq_thermal_count;
0444c9bd
JB
195#endif
196#ifdef CONFIG_X86_MCE_THRESHOLD
6b39ba77 197 sum += irq_stats(cpu)->irq_threshold_count;
8051dbd2 198#endif
c1ebf835 199#ifdef CONFIG_X86_MCE
8051dbd2
HS
200 sum += per_cpu(mce_exception_count, cpu);
201 sum += per_cpu(mce_poll_count, cpu);
6b39ba77
TG
202#endif
203 return sum;
204}
205
206u64 arch_irq_stat(void)
207{
208 u64 sum = atomic_read(&irq_err_count);
6b39ba77
TG
209 return sum;
210}
c3d80000 211
7c1d7cdc
JF
212
213/*
214 * do_IRQ handles all normal device IRQ's (the special
215 * SMP cross-CPU interrupts have their own specific
216 * handlers).
217 */
1d9090e2 218__visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
7c1d7cdc
JF
219{
220 struct pt_regs *old_regs = set_irq_regs(regs);
a782a7e4 221 struct irq_desc * desc;
7c1d7cdc
JF
222 /* high bit used in ret_from_ code */
223 unsigned vector = ~regs->orig_ax;
7c1d7cdc 224
0333a209
AL
225 /*
226 * NB: Unlike exception entries, IRQ entries do not reliably
227 * handle context tracking in the low-level entry code. This is
228 * because syscall entries execute briefly with IRQs on before
229 * updating context tracking state, so we can take an IRQ from
230 * kernel mode with CONTEXT_USER. The low-level entry code only
231 * updates the context if we came from user mode, so we won't
232 * switch to CONTEXT_KERNEL. We'll fix that once the syscall
233 * code is cleaned up enough that we can cleanly defer enabling
234 * IRQs.
235 */
236
6af7faf6 237 entering_irq();
7c1d7cdc 238
0333a209 239 /* entering_irq() tells RCU that we're not quiescent. Check it. */
5778077d 240 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
0333a209 241
a782a7e4 242 desc = __this_cpu_read(vector_irq[vector]);
7c1d7cdc 243
a782a7e4 244 if (!handle_irq(desc, regs)) {
08306ce6 245 ack_APIC_irq();
7c1d7cdc 246
a782a7e4
TG
247 if (desc != VECTOR_RETRIGGERED) {
248 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
9345005f 249 __func__, smp_processor_id(),
a782a7e4 250 vector);
9345005f 251 } else {
7276c6a2 252 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
9345005f 253 }
7c1d7cdc
JF
254 }
255
6af7faf6 256 exiting_irq();
7c1d7cdc
JF
257
258 set_irq_regs(old_regs);
259 return 1;
260}
261
acaabe79 262/*
4a4de9c7 263 * Handler for X86_PLATFORM_IPI_VECTOR.
acaabe79 264 */
eddc0e92 265void __smp_x86_platform_ipi(void)
acaabe79 266{
4a4de9c7 267 inc_irq_stat(x86_platform_ipis);
acaabe79 268
4a4de9c7
DS
269 if (x86_platform_ipi_callback)
270 x86_platform_ipi_callback();
eddc0e92 271}
acaabe79 272
c4158ff5 273__visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
eddc0e92
SA
274{
275 struct pt_regs *old_regs = set_irq_regs(regs);
acaabe79 276
eddc0e92
SA
277 entering_ack_irq();
278 __smp_x86_platform_ipi();
279 exiting_irq();
acaabe79
DS
280 set_irq_regs(old_regs);
281}
282
d78f2664 283#ifdef CONFIG_HAVE_KVM
f6b3c72c
FW
284static void dummy_handler(void) {}
285static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
286
287void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
288{
289 if (handler)
290 kvm_posted_intr_wakeup_handler = handler;
291 else
292 kvm_posted_intr_wakeup_handler = dummy_handler;
293}
294EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
295
d78f2664
YZ
296/*
297 * Handler for POSTED_INTERRUPT_VECTOR.
298 */
1d9090e2 299__visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
d78f2664
YZ
300{
301 struct pt_regs *old_regs = set_irq_regs(regs);
302
6af7faf6 303 entering_ack_irq();
d78f2664 304 inc_irq_stat(kvm_posted_intr_ipis);
f6b3c72c
FW
305 exiting_irq();
306 set_irq_regs(old_regs);
307}
308
309/*
310 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
311 */
312__visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
313{
314 struct pt_regs *old_regs = set_irq_regs(regs);
315
316 entering_ack_irq();
317 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
318 kvm_posted_intr_wakeup_handler();
6af7faf6 319 exiting_irq();
d78f2664
YZ
320 set_irq_regs(old_regs);
321}
210f84b0
WV
322
323/*
324 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
325 */
326__visible void smp_kvm_posted_intr_nested_ipi(struct pt_regs *regs)
327{
328 struct pt_regs *old_regs = set_irq_regs(regs);
329
330 entering_ack_irq();
331 inc_irq_stat(kvm_posted_intr_nested_ipis);
332 exiting_irq();
333 set_irq_regs(old_regs);
334}
d78f2664
YZ
335#endif
336
c4158ff5 337__visible void __irq_entry smp_trace_x86_platform_ipi(struct pt_regs *regs)
cf910e83
SA
338{
339 struct pt_regs *old_regs = set_irq_regs(regs);
340
341 entering_ack_irq();
342 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
343 __smp_x86_platform_ipi();
344 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
345 exiting_irq();
346 set_irq_regs(old_regs);
347}
348
c3d80000 349EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
7a7732bc
SS
350
351#ifdef CONFIG_HOTPLUG_CPU
39424e89
PB
352
353/* These two declarations are only used in check_irq_vectors_for_cpu_disable()
354 * below, which is protected by stop_machine(). Putting them on the stack
355 * results in a stack frame overflow. Dynamically allocating could result in a
356 * failure so declare these two cpumasks as global.
357 */
358static struct cpumask affinity_new, online_new;
359
da6139e4
PB
360/*
361 * This cpu is going to be removed and its vectors migrated to the remaining
362 * online cpus. Check to see if there are enough vectors in the remaining cpus.
363 * This function is protected by stop_machine().
364 */
365int check_irq_vectors_for_cpu_disable(void)
366{
da6139e4
PB
367 unsigned int this_cpu, vector, this_count, count;
368 struct irq_desc *desc;
369 struct irq_data *data;
a782a7e4 370 int cpu;
da6139e4
PB
371
372 this_cpu = smp_processor_id();
373 cpumask_copy(&online_new, cpu_online_mask);
020b37ac 374 cpumask_clear_cpu(this_cpu, &online_new);
da6139e4
PB
375
376 this_count = 0;
377 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
a782a7e4
TG
378 desc = __this_cpu_read(vector_irq[vector]);
379 if (IS_ERR_OR_NULL(desc))
44825757 380 continue;
44825757
TG
381 /*
382 * Protect against concurrent action removal, affinity
383 * changes etc.
384 */
385 raw_spin_lock(&desc->lock);
386 data = irq_desc_get_irq_data(desc);
a782a7e4
TG
387 cpumask_copy(&affinity_new,
388 irq_data_get_affinity_mask(data));
44825757 389 cpumask_clear_cpu(this_cpu, &affinity_new);
da6139e4 390
44825757 391 /* Do not count inactive or per-cpu irqs. */
a782a7e4 392 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
cbb24dc7 393 raw_spin_unlock(&desc->lock);
44825757 394 continue;
da6139e4 395 }
44825757
TG
396
397 raw_spin_unlock(&desc->lock);
398 /*
399 * A single irq may be mapped to multiple cpu's
400 * vector_irq[] (for example IOAPIC cluster mode). In
401 * this case we have two possibilities:
402 *
403 * 1) the resulting affinity mask is empty; that is
404 * this the down'd cpu is the last cpu in the irq's
405 * affinity mask, or
406 *
407 * 2) the resulting affinity mask is no longer a
408 * subset of the online cpus but the affinity mask is
409 * not zero; that is the down'd cpu is the last online
410 * cpu in a user set affinity mask.
411 */
412 if (cpumask_empty(&affinity_new) ||
413 !cpumask_subset(&affinity_new, &online_new))
414 this_count++;
da6139e4 415 }
c0edbd4a
CY
416 /* No need to check any further. */
417 if (!this_count)
418 return 0;
da6139e4
PB
419
420 count = 0;
421 for_each_online_cpu(cpu) {
422 if (cpu == this_cpu)
423 continue;
ac2a5539
YL
424 /*
425 * We scan from FIRST_EXTERNAL_VECTOR to first system
426 * vector. If the vector is marked in the used vectors
427 * bitmap or an irq is assigned to it, we don't count
428 * it as available.
cbb24dc7
TG
429 *
430 * As this is an inaccurate snapshot anyway, we can do
431 * this w/o holding vector_lock.
ac2a5539
YL
432 */
433 for (vector = FIRST_EXTERNAL_VECTOR;
434 vector < first_system_vector; vector++) {
435 if (!test_bit(vector, used_vectors) &&
c0edbd4a
CY
436 IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector])) {
437 if (++count == this_count)
438 return 0;
439 }
da6139e4
PB
440 }
441 }
442
443 if (count < this_count) {
444 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
445 this_cpu, this_count, count);
446 return -ERANGE;
447 }
448 return 0;
449}
450
7a7732bc
SS
451/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
452void fixup_irqs(void)
453{
ad7a929f 454 unsigned int irr, vector;
7a7732bc 455 struct irq_desc *desc;
a3c08e5d 456 struct irq_data *data;
51c43ac6 457 struct irq_chip *chip;
7a7732bc 458
ad7a929f 459 irq_migrate_all_off_this_cpu();
7a7732bc 460
5231a686
SS
461 /*
462 * We can remove mdelay() and then send spuriuous interrupts to
463 * new cpu targets for all the irqs that were handled previously by
464 * this cpu. While it works, I have seen spurious interrupt messages
465 * (nothing wrong but still...).
466 *
467 * So for now, retain mdelay(1) and check the IRR and then send those
468 * interrupts to new targets as this cpu is already offlined...
469 */
7a7732bc 470 mdelay(1);
5231a686 471
09cf92b7
TG
472 /*
473 * We can walk the vector array of this cpu without holding
474 * vector_lock because the cpu is already marked !online, so
475 * nothing else will touch it.
476 */
5231a686 477 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
a782a7e4 478 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
5231a686
SS
479 continue;
480
481 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
482 if (irr & (1 << (vector % 32))) {
a782a7e4 483 desc = __this_cpu_read(vector_irq[vector]);
5231a686 484
09cf92b7 485 raw_spin_lock(&desc->lock);
51c43ac6
TG
486 data = irq_desc_get_irq_data(desc);
487 chip = irq_data_get_irq_chip(data);
9345005f 488 if (chip->irq_retrigger) {
51c43ac6 489 chip->irq_retrigger(data);
9345005f
PB
490 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
491 }
239007b8 492 raw_spin_unlock(&desc->lock);
5231a686 493 }
9345005f 494 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
7276c6a2 495 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
5231a686 496 }
7a7732bc
SS
497}
498#endif