]>
Commit | Line | Data |
---|---|---|
77883860 | 1 | #include <linux/linkage.h> |
1da177e4 LT |
2 | #include <linux/errno.h> |
3 | #include <linux/signal.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/ioport.h> | |
6 | #include <linux/interrupt.h> | |
77883860 | 7 | #include <linux/timex.h> |
1da177e4 LT |
8 | #include <linux/slab.h> |
9 | #include <linux/random.h> | |
47f16ca7 | 10 | #include <linux/kprobes.h> |
1da177e4 LT |
11 | #include <linux/init.h> |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/sysdev.h> | |
14 | #include <linux/bitops.h> | |
77883860 | 15 | #include <linux/acpi.h> |
aa09e6cd JSR |
16 | #include <linux/io.h> |
17 | #include <linux/delay.h> | |
1da177e4 | 18 | |
1da177e4 LT |
19 | #include <asm/atomic.h> |
20 | #include <asm/system.h> | |
1da177e4 | 21 | #include <asm/timer.h> |
77883860 | 22 | #include <asm/hw_irq.h> |
1da177e4 | 23 | #include <asm/pgtable.h> |
1da177e4 LT |
24 | #include <asm/desc.h> |
25 | #include <asm/apic.h> | |
8e6dafd6 | 26 | #include <asm/setup.h> |
1da177e4 | 27 | #include <asm/i8259.h> |
aa09e6cd | 28 | #include <asm/traps.h> |
1da177e4 | 29 | |
77883860 PE |
30 | /* |
31 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: | |
32 | * (these are usually mapped to vectors 0x30-0x3f) | |
33 | */ | |
34 | ||
35 | /* | |
36 | * The IO-APIC gives us many more interrupt sources. Most of these | |
37 | * are unused but an SMP system is supposed to have enough memory ... | |
38 | * sometimes (mostly wrt. hw bugs) we get corrupted vectors all | |
39 | * across the spectrum, so we really want to be prepared to get all | |
40 | * of these. Plus, more powerful systems might have more than 64 | |
41 | * IO-APIC registers. | |
42 | * | |
43 | * (these are usually mapped into the 0x30-0xff vector range) | |
44 | */ | |
1da177e4 | 45 | |
320fd996 | 46 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
47 | /* |
48 | * Note that on a 486, we don't want to do a SIGFPE on an irq13 | |
49 | * as the irq is unreliable, and exception 16 works correctly | |
50 | * (ie as explained in the intel literature). On a 386, you | |
51 | * can't use exception 16 due to bad IBM design, so we have to | |
52 | * rely on the less exact irq13. | |
53 | * | |
54 | * Careful.. Not only is IRQ13 unreliable, but it is also | |
55 | * leads to races. IBM designers who came up with it should | |
56 | * be shot. | |
57 | */ | |
1da177e4 | 58 | |
7d12e780 | 59 | static irqreturn_t math_error_irq(int cpl, void *dev_id) |
1da177e4 | 60 | { |
aa09e6cd | 61 | outb(0, 0xF0); |
1da177e4 LT |
62 | if (ignore_fpu_irq || !boot_cpu_data.hard_math) |
63 | return IRQ_NONE; | |
65ea5b03 | 64 | math_error((void __user *)get_irq_regs()->ip); |
1da177e4 LT |
65 | return IRQ_HANDLED; |
66 | } | |
67 | ||
68 | /* | |
69 | * New motherboards sometimes make IRQ 13 be a PCI interrupt, | |
70 | * so allow interrupt sharing. | |
71 | */ | |
6a61f6a5 TG |
72 | static struct irqaction fpu_irq = { |
73 | .handler = math_error_irq, | |
6a61f6a5 TG |
74 | .name = "fpu", |
75 | }; | |
1da177e4 | 76 | #endif |
1da177e4 | 77 | |
2ae111cd CG |
78 | /* |
79 | * IRQ2 is cascade interrupt to second interrupt controller | |
80 | */ | |
81 | static struct irqaction irq2 = { | |
82 | .handler = no_action, | |
2ae111cd CG |
83 | .name = "cascade", |
84 | }; | |
85 | ||
497c9a19 | 86 | DEFINE_PER_CPU(vector_irq_t, vector_irq) = { |
97943390 | 87 | [0 ... NR_VECTORS - 1] = -1, |
497c9a19 YL |
88 | }; |
89 | ||
b77b881f YL |
90 | int vector_used_by_percpu_irq(unsigned int vector) |
91 | { | |
92 | int cpu; | |
93 | ||
94 | for_each_online_cpu(cpu) { | |
95 | if (per_cpu(vector_irq, cpu)[vector] != -1) | |
96 | return 1; | |
97 | } | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
97943390 SS |
102 | /* Number of legacy interrupts */ |
103 | int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY; | |
104 | ||
d9112f43 | 105 | void __init init_ISA_irqs(void) |
1da177e4 LT |
106 | { |
107 | int i; | |
108 | ||
598c73d2 | 109 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) |
7371d9fc PE |
110 | init_bsp_APIC(); |
111 | #endif | |
b81bb373 | 112 | legacy_pic->init(0); |
1da177e4 LT |
113 | |
114 | /* | |
7371d9fc | 115 | * 16 old-style INTA-cycle interrupts: |
1da177e4 | 116 | */ |
7371d9fc PE |
117 | for (i = 0; i < NR_IRQS_LEGACY; i++) { |
118 | struct irq_desc *desc = irq_to_desc(i); | |
119 | ||
120 | desc->status = IRQ_DISABLED; | |
121 | desc->action = NULL; | |
122 | desc->depth = 1; | |
123 | ||
124 | set_irq_chip_and_handler_name(i, &i8259A_chip, | |
125 | handle_level_irq, "XT"); | |
1da177e4 | 126 | } |
7371d9fc | 127 | } |
1da177e4 | 128 | |
54e2603f | 129 | void __init init_IRQ(void) |
66bcaf0b | 130 | { |
97943390 SS |
131 | int i; |
132 | ||
133 | /* | |
134 | * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15. | |
135 | * If these IRQ's are handled by legacy interrupt-controllers like PIC, | |
136 | * then this configuration will likely be static after the boot. If | |
137 | * these IRQ's are handled by more mordern controllers like IO-APIC, | |
138 | * then this vector space can be freed and re-used dynamically as the | |
139 | * irq's migrate etc. | |
140 | */ | |
141 | for (i = 0; i < nr_legacy_irqs; i++) | |
142 | per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i; | |
143 | ||
66bcaf0b TG |
144 | x86_init.irqs.intr_init(); |
145 | } | |
2ae111cd | 146 | |
36290d87 PE |
147 | static void __init smp_intr_init(void) |
148 | { | |
b0096bb0 PE |
149 | #ifdef CONFIG_SMP |
150 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) | |
2ae111cd CG |
151 | /* |
152 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
153 | * IPI, driven by wakeup. | |
154 | */ | |
155 | alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
156 | ||
02cf94c3 TH |
157 | /* IPIs for invalidation */ |
158 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0); | |
159 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1); | |
160 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2); | |
161 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3); | |
162 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4); | |
163 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5); | |
164 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6); | |
165 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7); | |
2ae111cd CG |
166 | |
167 | /* IPI for generic function call */ | |
168 | alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
169 | ||
b0096bb0 | 170 | /* IPI for generic single function call */ |
b77b881f | 171 | alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, |
b0096bb0 | 172 | call_function_single_interrupt); |
497c9a19 YL |
173 | |
174 | /* Low priority IPI to cleanup after moving an irq */ | |
175 | set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt); | |
b77b881f | 176 | set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors); |
4ef702c1 AK |
177 | |
178 | /* IPI used for rebooting/stopping */ | |
179 | alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt); | |
2ae111cd | 180 | #endif |
b0096bb0 | 181 | #endif /* CONFIG_SMP */ |
36290d87 PE |
182 | } |
183 | ||
22813c45 | 184 | static void __init apic_intr_init(void) |
1da177e4 | 185 | { |
36290d87 | 186 | smp_intr_init(); |
2ae111cd | 187 | |
48b1fddb | 188 | #ifdef CONFIG_X86_THERMAL_VECTOR |
ab19c25a | 189 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
48b1fddb | 190 | #endif |
6effa8f6 | 191 | #ifdef CONFIG_X86_MCE_THRESHOLD |
ab19c25a PE |
192 | alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); |
193 | #endif | |
c1ebf835 | 194 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC) |
ccc3c319 AK |
195 | alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt); |
196 | #endif | |
ab19c25a PE |
197 | |
198 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) | |
2ae111cd CG |
199 | /* self generated IPI for local APIC timer */ |
200 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
201 | ||
4a4de9c7 DS |
202 | /* IPI for X86 platform specific use */ |
203 | alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi); | |
acaabe79 | 204 | |
2ae111cd CG |
205 | /* IPI vectors for APIC spurious and error interrupts */ |
206 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
207 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
2ae111cd | 208 | |
47f16ca7 | 209 | /* Performance monitoring interrupts: */ |
cdd6c482 | 210 | # ifdef CONFIG_PERF_EVENTS |
47f16ca7 IM |
211 | alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt); |
212 | # endif | |
213 | ||
2ae111cd | 214 | #endif |
22813c45 | 215 | } |
2ae111cd | 216 | |
22813c45 PE |
217 | void __init native_init_IRQ(void) |
218 | { | |
219 | int i; | |
220 | ||
221 | /* Execute any quirks before the call gates are initialised: */ | |
d9112f43 | 222 | x86_init.irqs.pre_vector_init(); |
22813c45 | 223 | |
77857dc0 YL |
224 | apic_intr_init(); |
225 | ||
22813c45 PE |
226 | /* |
227 | * Cover the whole vector space, no vector can escape | |
228 | * us. (some of these will be overridden and become | |
229 | * 'special' SMP interrupts) | |
230 | */ | |
d3496c85 | 231 | for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) { |
77857dc0 YL |
232 | /* IA32_SYSCALL_VECTOR could be used in trap_init already. */ |
233 | if (!test_bit(i, used_vectors)) | |
320fd996 | 234 | set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]); |
22813c45 | 235 | } |
7856f6cc | 236 | |
2ae111cd CG |
237 | if (!acpi_ioapic) |
238 | setup_irq(2, &irq2); | |
239 | ||
320fd996 | 240 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
241 | /* |
242 | * External FPU? Set up irq13 if so, for | |
243 | * original braindamaged IBM FERR coupling. | |
244 | */ | |
245 | if (boot_cpu_data.hard_math && !cpu_has_fpu) | |
246 | setup_irq(FPU_IRQ, &fpu_irq); | |
247 | ||
248 | irq_ctx_init(smp_processor_id()); | |
320fd996 | 249 | #endif |
1da177e4 | 250 | } |