[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / irqinit.c

#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/kprobes.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/setup.h>
#include <asm/i8259.h>
#include <asm/traps.h>

/*
 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
 * (these are usually mapped to vectors 0x30-0x3f)
 */

/*
 * The IO-APIC gives us many more interrupt sources. Most of these
 * are unused but an SMP system is supposed to have enough memory ...
 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
 * across the spectrum, so we really want to be prepared to get all
 * of these. Plus, more powerful systems might have more than 64
 * IO-APIC registers.
 *
 * (these are usually mapped into the 0x30-0xff vector range)
 */

#ifdef CONFIG_X86_32
/*
 * Note that on a 486, we don't want to do a SIGFPE on an irq13
 * as the irq is unreliable, and exception 16 works correctly
 * (ie as explained in the intel literature). On a 386, you
 * can't use exception 16 due to bad IBM design, so we have to
 * rely on the less exact irq13.
 *
 * Careful.. Not only is IRQ13 unreliable, but it is also
 * leads to races. IBM designers who came up with it should
 * be shot.
 */

static irqreturn_t math_error_irq(int cpl, void *dev_id)
{
	outb(0, 0xF0);
	if (ignore_fpu_irq || !boot_cpu_data.hard_math)
		return IRQ_NONE;
	math_error(get_irq_regs(), 0, 16);
	return IRQ_HANDLED;
}

/*
 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
 * so allow interrupt sharing.
 */
static struct irqaction fpu_irq = {
	.handler = math_error_irq,
	.name = "fpu",
};
#endif

/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.name = "cascade",
};

DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
	[0 ... NR_VECTORS - 1] = -1,
};

int vector_used_by_percpu_irq(unsigned int vector)
{
	int cpu;

	for_each_online_cpu(cpu) {
		if (per_cpu(vector_irq, cpu)[vector] != -1)
			return 1;
	}

	return 0;
}

void __init init_ISA_irqs(void)
{
	struct irq_chip *chip = legacy_pic->chip;
	const char *name = chip->name;
	int i;

#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
	init_bsp_APIC();
#endif
	legacy_pic->init(0);

	for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
		set_irq_chip_and_handler_name(i, chip, handle_level_irq, name);
}

void __init init_IRQ(void)
{
	int i;

	/*
	 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
	 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
	 * then this configuration will likely be static after the boot. If
	 * these IRQ's are handled by more mordern controllers like IO-APIC,
	 * then this vector space can be freed and re-used dynamically as the
	 * irq's migrate etc.
	 */
	for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
		per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;

	x86_init.irqs.intr_init();
}

/*
 * Setup the vector to irq mappings.
 */
void setup_vector_irq(int cpu)
{
#ifndef CONFIG_X86_IO_APIC
	int irq;

	/*
	 * On most of the platforms, legacy PIC delivers the interrupts on the
	 * boot cpu. But there are certain platforms where PIC interrupts are
	 * delivered to multiple cpu's. If the legacy IRQ is handled by the
	 * legacy PIC, for the new cpu that is coming online, setup the static
	 * legacy vector to irq mapping:
	 */
	for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
		per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
#endif

	__setup_vector_irq(cpu);
}

static void __init smp_intr_init(void)
{
#ifdef CONFIG_SMP
#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
	/*
	 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
	 * IPI, driven by wakeup.
	 */
	alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);

	/* IPIs for invalidation */
#define ALLOC_INVTLB_VEC(NR) \
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+NR, \
		invalidate_interrupt##NR)

	switch (NUM_INVALIDATE_TLB_VECTORS) {
	default:
		ALLOC_INVTLB_VEC(31);
	case 31:
		ALLOC_INVTLB_VEC(30);
	case 30:
		ALLOC_INVTLB_VEC(29);
	case 29:
		ALLOC_INVTLB_VEC(28);
	case 28:
		ALLOC_INVTLB_VEC(27);
	case 27:
		ALLOC_INVTLB_VEC(26);
	case 26:
		ALLOC_INVTLB_VEC(25);
	case 25:
		ALLOC_INVTLB_VEC(24);
	case 24:
		ALLOC_INVTLB_VEC(23);
	case 23:
		ALLOC_INVTLB_VEC(22);
	case 22:
		ALLOC_INVTLB_VEC(21);
	case 21:
		ALLOC_INVTLB_VEC(20);
	case 20:
		ALLOC_INVTLB_VEC(19);
	case 19:
		ALLOC_INVTLB_VEC(18);
	case 18:
		ALLOC_INVTLB_VEC(17);
	case 17:
		ALLOC_INVTLB_VEC(16);
	case 16:
		ALLOC_INVTLB_VEC(15);
	case 15:
		ALLOC_INVTLB_VEC(14);
	case 14:
		ALLOC_INVTLB_VEC(13);
	case 13:
		ALLOC_INVTLB_VEC(12);
	case 12:
		ALLOC_INVTLB_VEC(11);
	case 11:
		ALLOC_INVTLB_VEC(10);
	case 10:
		ALLOC_INVTLB_VEC(9);
	case 9:
		ALLOC_INVTLB_VEC(8);
	case 8:
		ALLOC_INVTLB_VEC(7);
	case 7:
		ALLOC_INVTLB_VEC(6);
	case 6:
		ALLOC_INVTLB_VEC(5);
	case 5:
		ALLOC_INVTLB_VEC(4);
	case 4:
		ALLOC_INVTLB_VEC(3);
	case 3:
		ALLOC_INVTLB_VEC(2);
	case 2:
		ALLOC_INVTLB_VEC(1);
	case 1:
		ALLOC_INVTLB_VEC(0);
		break;
	}

	/* IPI for generic function call */
	alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);

	/* IPI for generic single function call */
	alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
			call_function_single_interrupt);

	/* Low priority IPI to cleanup after moving an irq */
	set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
	set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);

	/* IPI used for rebooting/stopping */
	alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
#endif
#endif /* CONFIG_SMP */
}

static void __init apic_intr_init(void)
{
	smp_intr_init();

#ifdef CONFIG_X86_THERMAL_VECTOR
	alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
	alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
#endif
#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
	alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
#endif

#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
	/* self generated IPI for local APIC timer */
	alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);

	/* IPI for X86 platform specific use */
	alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);

	/* IPI vectors for APIC spurious and error interrupts */
	alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
	alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);

	/* IRQ work interrupts: */
# ifdef CONFIG_IRQ_WORK
	alloc_intr_gate(IRQ_WORK_VECTOR, irq_work_interrupt);
# endif

#endif
}

void __init native_init_IRQ(void)
{
	int i;

	/* Execute any quirks before the call gates are initialised: */
	x86_init.irqs.pre_vector_init();

	apic_intr_init();

	/*
	 * Cover the whole vector space, no vector can escape
	 * us. (some of these will be overridden and become
	 * 'special' SMP interrupts)
	 */
	for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
		/* IA32_SYSCALL_VECTOR could be used in trap_init already. */
		if (!test_bit(i, used_vectors))
			set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
	}

	if (!acpi_ioapic)
		setup_irq(2, &irq2);

#ifdef CONFIG_X86_32
	/*
	 * External FPU? Set up irq13 if so, for
	 * original braindamaged IBM FERR coupling.
	 */
	if (boot_cpu_data.hard_math && !cpu_has_fpu)
		setup_irq(FPU_IRQ, &fpu_irq);

	irq_ctx_init(smp_processor_id());
#endif
}
Commit	Line	Data
77883860	1	#include <linux/linkage.h>
1da177e4 LT	2	#include <linux/errno.h>
	3	#include <linux/signal.h>
	4	#include <linux/sched.h>
	5	#include <linux/ioport.h>
	6	#include <linux/interrupt.h>
77883860	7	#include <linux/timex.h>
1da177e4	8	#include <linux/random.h>
47f16ca7	9	#include <linux/kprobes.h>
1da177e4 LT	10	#include <linux/init.h>
	11	#include <linux/kernel_stat.h>
	12	#include <linux/sysdev.h>
	13	#include <linux/bitops.h>
77883860	14	#include <linux/acpi.h>
aa09e6cd JSR	15	#include <linux/io.h>
aa09e6cd JSR	16	#include <linux/delay.h>
1da177e4	17
1da177e4 LT	18	#include <asm/atomic.h>
1da177e4 LT	19	#include <asm/system.h>
1da177e4	20	#include <asm/timer.h>
77883860	21	#include <asm/hw_irq.h>
1da177e4	22	#include <asm/pgtable.h>
1da177e4 LT	23	#include <asm/desc.h>
1da177e4 LT	24	#include <asm/apic.h>
8e6dafd6	25	#include <asm/setup.h>
1da177e4	26	#include <asm/i8259.h>
aa09e6cd	27	#include <asm/traps.h>
1da177e4	28
77883860 PE	29	/*
	30	* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
	31	* (these are usually mapped to vectors 0x30-0x3f)
	32	*/
	33
	34	/*
	35	* The IO-APIC gives us many more interrupt sources. Most of these
	36	* are unused but an SMP system is supposed to have enough memory ...
	37	* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
	38	* across the spectrum, so we really want to be prepared to get all
	39	* of these. Plus, more powerful systems might have more than 64
	40	* IO-APIC registers.
	41	*
	42	* (these are usually mapped into the 0x30-0xff vector range)
	43	*/
1da177e4	44
320fd996	45	#ifdef CONFIG_X86_32
1da177e4 LT	46	/*
	47	* Note that on a 486, we don't want to do a SIGFPE on an irq13
	48	* as the irq is unreliable, and exception 16 works correctly
	49	* (ie as explained in the intel literature). On a 386, you
	50	* can't use exception 16 due to bad IBM design, so we have to
	51	* rely on the less exact irq13.
	52	*
	53	* Careful.. Not only is IRQ13 unreliable, but it is also
	54	* leads to races. IBM designers who came up with it should
	55	* be shot.
	56	*/
1da177e4	57
7d12e780	58	static irqreturn_t math_error_irq(int cpl, void *dev_id)
1da177e4	59	{
aa09e6cd	60	outb(0, 0xF0);
1da177e4 LT	61	if (ignore_fpu_irq \|\| !boot_cpu_data.hard_math)
1da177e4 LT	62	return IRQ_NONE;
9b6dba9e	63	math_error(get_irq_regs(), 0, 16);
1da177e4 LT	64	return IRQ_HANDLED;
	65	}
	66
	67	/*
	68	* New motherboards sometimes make IRQ 13 be a PCI interrupt,
	69	* so allow interrupt sharing.
	70	*/
6a61f6a5 TG	71	static struct irqaction fpu_irq = {
6a61f6a5 TG	72	.handler = math_error_irq,
6a61f6a5 TG	73	.name = "fpu",
6a61f6a5 TG	74	};
1da177e4	75	#endif
1da177e4	76
2ae111cd CG	77	/*
	78	* IRQ2 is cascade interrupt to second interrupt controller
	79	*/
	80	static struct irqaction irq2 = {
	81	.handler = no_action,
2ae111cd CG	82	.name = "cascade",
	83	};
	84
497c9a19	85	DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
97943390	86	[0 ... NR_VECTORS - 1] = -1,
497c9a19 YL	87	};
497c9a19 YL	88
b77b881f YL	89	int vector_used_by_percpu_irq(unsigned int vector)
	90	{
	91	int cpu;
	92
	93	for_each_online_cpu(cpu) {
	94	if (per_cpu(vector_irq, cpu)[vector] != -1)
	95	return 1;
	96	}
	97
	98	return 0;
	99	}
	100
d9112f43	101	void __init init_ISA_irqs(void)
1da177e4	102	{
011d578f TG	103	struct irq_chip *chip = legacy_pic->chip;
011d578f TG	104	const char *name = chip->name;
1da177e4 LT	105	int i;
1da177e4 LT	106
598c73d2	107	#if defined(CONFIG_X86_64) \|\| defined(CONFIG_X86_LOCAL_APIC)
7371d9fc PE	108	init_bsp_APIC();
7371d9fc PE	109	#endif
b81bb373	110	legacy_pic->init(0);
1da177e4	111
011d578f TG	112	for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
011d578f TG	113	set_irq_chip_and_handler_name(i, chip, handle_level_irq, name);
7371d9fc	114	}
1da177e4	115
54e2603f	116	void __init init_IRQ(void)
66bcaf0b	117	{
97943390 SS	118	int i;
	119
	120	/*
	121	* On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
	122	* If these IRQ's are handled by legacy interrupt-controllers like PIC,
	123	* then this configuration will likely be static after the boot. If
	124	* these IRQ's are handled by more mordern controllers like IO-APIC,
	125	* then this vector space can be freed and re-used dynamically as the
	126	* irq's migrate etc.
	127	*/
28c6a0ba	128	for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
97943390 SS	129	per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
97943390 SS	130
66bcaf0b TG	131	x86_init.irqs.intr_init();
66bcaf0b TG	132	}
2ae111cd	133
36e9e1ea SS	134	/*
	135	* Setup the vector to irq mappings.
	136	*/
	137	void setup_vector_irq(int cpu)
	138	{
	139	#ifndef CONFIG_X86_IO_APIC
	140	int irq;
	141
	142	/*
	143	* On most of the platforms, legacy PIC delivers the interrupts on the
	144	* boot cpu. But there are certain platforms where PIC interrupts are
	145	* delivered to multiple cpu's. If the legacy IRQ is handled by the
	146	* legacy PIC, for the new cpu that is coming online, setup the static
	147	* legacy vector to irq mapping:
	148	*/
	149	for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
	150	per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
	151	#endif
	152
	153	__setup_vector_irq(cpu);
	154	}
	155
36290d87 PE	156	static void __init smp_intr_init(void)
36290d87 PE	157	{
b0096bb0 PE	158	#ifdef CONFIG_SMP
b0096bb0 PE	159	#if defined(CONFIG_X86_64) \|\| defined(CONFIG_X86_LOCAL_APIC)
2ae111cd CG	160	/*
	161	* The reschedule interrupt is a CPU-to-CPU reschedule-helper
	162	* IPI, driven by wakeup.
	163	*/
	164	alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
	165
02cf94c3	166	/* IPIs for invalidation */
3a09fb45 SL	167	#define ALLOC_INVTLB_VEC(NR) \
	168	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+NR, \
	169	invalidate_interrupt##NR)
	170
	171	switch (NUM_INVALIDATE_TLB_VECTORS) {
	172	default:
	173	ALLOC_INVTLB_VEC(31);
	174	case 31:
	175	ALLOC_INVTLB_VEC(30);
	176	case 30:
	177	ALLOC_INVTLB_VEC(29);
	178	case 29:
	179	ALLOC_INVTLB_VEC(28);
	180	case 28:
	181	ALLOC_INVTLB_VEC(27);
	182	case 27:
	183	ALLOC_INVTLB_VEC(26);
	184	case 26:
	185	ALLOC_INVTLB_VEC(25);
	186	case 25:
	187	ALLOC_INVTLB_VEC(24);
	188	case 24:
	189	ALLOC_INVTLB_VEC(23);
	190	case 23:
	191	ALLOC_INVTLB_VEC(22);
	192	case 22:
	193	ALLOC_INVTLB_VEC(21);
	194	case 21:
	195	ALLOC_INVTLB_VEC(20);
	196	case 20:
	197	ALLOC_INVTLB_VEC(19);
	198	case 19:
	199	ALLOC_INVTLB_VEC(18);
	200	case 18:
	201	ALLOC_INVTLB_VEC(17);
	202	case 17:
	203	ALLOC_INVTLB_VEC(16);
	204	case 16:
	205	ALLOC_INVTLB_VEC(15);
	206	case 15:
	207	ALLOC_INVTLB_VEC(14);
	208	case 14:
	209	ALLOC_INVTLB_VEC(13);
	210	case 13:
	211	ALLOC_INVTLB_VEC(12);
	212	case 12:
	213	ALLOC_INVTLB_VEC(11);
	214	case 11:
	215	ALLOC_INVTLB_VEC(10);
	216	case 10:
	217	ALLOC_INVTLB_VEC(9);
	218	case 9:
	219	ALLOC_INVTLB_VEC(8);
	220	case 8:
	221	ALLOC_INVTLB_VEC(7);
	222	case 7:
	223	ALLOC_INVTLB_VEC(6);
	224	case 6:
	225	ALLOC_INVTLB_VEC(5);
	226	case 5:
	227	ALLOC_INVTLB_VEC(4);
	228	case 4:
	229	ALLOC_INVTLB_VEC(3);
	230	case 3:
231	ALLOC_INVTLB_VEC(2);
232	case 2:
233	ALLOC_INVTLB_VEC(1);
234	case 1:
235	ALLOC_INVTLB_VEC(0);
236	break;
237	}
2ae111cd CG	238
	239	/* IPI for generic function call */
	240	alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
	241
b0096bb0	242	/* IPI for generic single function call */
b77b881f	243	alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
b0096bb0	244	call_function_single_interrupt);
497c9a19 YL	245
	246	/* Low priority IPI to cleanup after moving an irq */
	247	set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
b77b881f	248	set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
4ef702c1 AK	249
	250	/* IPI used for rebooting/stopping */
	251	alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
2ae111cd	252	#endif
b0096bb0	253	#endif /* CONFIG_SMP */
36290d87 PE	254	}
36290d87 PE	255
22813c45	256	static void __init apic_intr_init(void)
1da177e4	257	{
36290d87	258	smp_intr_init();
2ae111cd	259
48b1fddb	260	#ifdef CONFIG_X86_THERMAL_VECTOR
ab19c25a	261	alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
48b1fddb	262	#endif
6effa8f6	263	#ifdef CONFIG_X86_MCE_THRESHOLD
ab19c25a PE	264	alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
ab19c25a PE	265	#endif
c1ebf835	266	#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
ccc3c319 AK	267	alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
ccc3c319 AK	268	#endif
ab19c25a PE	269
ab19c25a PE	270	#if defined(CONFIG_X86_64) \|\| defined(CONFIG_X86_LOCAL_APIC)
2ae111cd CG	271	/* self generated IPI for local APIC timer */
	272	alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
	273
4a4de9c7 DS	274	/* IPI for X86 platform specific use */
4a4de9c7 DS	275	alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
acaabe79	276
2ae111cd CG	277	/* IPI vectors for APIC spurious and error interrupts */
	278	alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
	279	alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
2ae111cd	280
e360adbe PZ	281	/* IRQ work interrupts: */
	282	# ifdef CONFIG_IRQ_WORK
	283	alloc_intr_gate(IRQ_WORK_VECTOR, irq_work_interrupt);
47f16ca7 IM	284	# endif
47f16ca7 IM	285
2ae111cd	286	#endif
22813c45	287	}
2ae111cd	288
22813c45 PE	289	void __init native_init_IRQ(void)
	290	{
	291	int i;
	292
	293	/* Execute any quirks before the call gates are initialised: */
d9112f43	294	x86_init.irqs.pre_vector_init();
22813c45	295
77857dc0 YL	296	apic_intr_init();
77857dc0 YL	297
22813c45 PE	298	/*
	299	* Cover the whole vector space, no vector can escape
	300	* us. (some of these will be overridden and become
	301	* 'special' SMP interrupts)
	302	*/
d3496c85	303	for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
77857dc0 YL	304	/* IA32_SYSCALL_VECTOR could be used in trap_init already. */
77857dc0 YL	305	if (!test_bit(i, used_vectors))
320fd996	306	set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
22813c45	307	}
7856f6cc	308
2ae111cd CG	309	if (!acpi_ioapic)
	310	setup_irq(2, &irq2);
	311
320fd996	312	#ifdef CONFIG_X86_32
1da177e4 LT	313	/*
	314	* External FPU? Set up irq13 if so, for
	315	* original braindamaged IBM FERR coupling.
	316	*/
	317	if (boot_cpu_data.hard_math && !cpu_has_fpu)
	318	setup_irq(FPU_IRQ, &fpu_irq);
	319
	320	irq_ctx_init(smp_processor_id());
320fd996	321	#endif
1da177e4	322	}