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x86: make 32 bit to use sparse_irq
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / irqinit_32.c
CommitLineData
1da177e4
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1#include <linux/errno.h>
2#include <linux/signal.h>
3#include <linux/sched.h>
4#include <linux/ioport.h>
5#include <linux/interrupt.h>
6#include <linux/slab.h>
7#include <linux/random.h>
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8#include <linux/init.h>
9#include <linux/kernel_stat.h>
10#include <linux/sysdev.h>
11#include <linux/bitops.h>
12
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13#include <asm/atomic.h>
14#include <asm/system.h>
15#include <asm/io.h>
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16#include <asm/timer.h>
17#include <asm/pgtable.h>
18#include <asm/delay.h>
19#include <asm/desc.h>
20#include <asm/apic.h>
21#include <asm/arch_hooks.h>
22#include <asm/i8259.h>
23
1da177e4 24
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25
26/*
27 * Note that on a 486, we don't want to do a SIGFPE on an irq13
28 * as the irq is unreliable, and exception 16 works correctly
29 * (ie as explained in the intel literature). On a 386, you
30 * can't use exception 16 due to bad IBM design, so we have to
31 * rely on the less exact irq13.
32 *
33 * Careful.. Not only is IRQ13 unreliable, but it is also
34 * leads to races. IBM designers who came up with it should
35 * be shot.
36 */
37
38
7d12e780 39static irqreturn_t math_error_irq(int cpl, void *dev_id)
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40{
41 extern void math_error(void __user *);
42 outb(0,0xF0);
43 if (ignore_fpu_irq || !boot_cpu_data.hard_math)
44 return IRQ_NONE;
65ea5b03 45 math_error((void __user *)get_irq_regs()->ip);
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46 return IRQ_HANDLED;
47}
48
49/*
50 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
51 * so allow interrupt sharing.
52 */
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TG
53static struct irqaction fpu_irq = {
54 .handler = math_error_irq,
55 .mask = CPU_MASK_NONE,
56 .name = "fpu",
57};
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58
59void __init init_ISA_irqs (void)
60{
61 int i;
62
63#ifdef CONFIG_X86_LOCAL_APIC
64 init_bsp_APIC();
65#endif
66 init_8259A(0);
67
7c6357da
AD
68 /*
69 * 16 old-style INTA-cycle interrupts:
70 */
71 for (i = 0; i < 16; i++) {
199751d7
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72 /* first time call this irq_desc */
73 struct irq_desc *desc = irq_to_desc_alloc(i);
74
75 desc->status = IRQ_DISABLED;
76 desc->action = NULL;
77 desc->depth = 1;
78
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AD
79 set_irq_chip_and_handler_name(i, &i8259A_chip,
80 handle_level_irq, "XT");
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81 }
82}
83
2ae111cd
CG
84/*
85 * IRQ2 is cascade interrupt to second interrupt controller
86 */
87static struct irqaction irq2 = {
88 .handler = no_action,
89 .mask = CPU_MASK_NONE,
90 .name = "cascade",
91};
92
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93/* Overridden in paravirt.c */
94void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
95
96void __init native_init_IRQ(void)
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97{
98 int i;
99
100 /* all the set up before the call gates are initialised */
101 pre_intr_init_hook();
102
103 /*
104 * Cover the whole vector space, no vector can escape
105 * us. (some of these will be overridden and become
106 * 'special' SMP interrupts)
107 */
108 for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
109 int vector = FIRST_EXTERNAL_VECTOR + i;
0799e432 110 if (i >= nr_irqs)
1da177e4 111 break;
dbeb2be2
RR
112 /* SYSCALL_VECTOR was reserved in trap_init. */
113 if (!test_bit(vector, used_vectors))
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114 set_intr_gate(vector, interrupt[i]);
115 }
116
2ae111cd
CG
117#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
118 /*
119 * IRQ0 must be given a fixed assignment and initialized,
120 * because it's used before the IO-APIC is set up.
121 */
122 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
123
124 /*
125 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
126 * IPI, driven by wakeup.
127 */
128 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
129
130 /* IPI for invalidation */
131 alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
132
133 /* IPI for generic function call */
134 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
135
136 /* IPI for single call function */
137 set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt);
138#endif
139
140#ifdef CONFIG_X86_LOCAL_APIC
141 /* self generated IPI for local APIC timer */
142 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
143
144 /* IPI vectors for APIC spurious and error interrupts */
145 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
146 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
147#endif
148
149#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_MCE_P4THERMAL)
150 /* thermal monitor LVT interrupt */
151 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
152#endif
153
154 if (!acpi_ioapic)
155 setup_irq(2, &irq2);
156
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157 /* setup after call gates are initialised (usually add in
158 * the architecture specific gates)
159 */
160 intr_init_hook();
161
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162 /*
163 * External FPU? Set up irq13 if so, for
164 * original braindamaged IBM FERR coupling.
165 */
166 if (boot_cpu_data.hard_math && !cpu_has_fpu)
167 setup_irq(FPU_IRQ, &fpu_irq);
168
169 irq_ctx_init(smp_processor_id());
170}