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Commit | Line | Data |
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1da177e4 LT |
1 | #include <linux/errno.h> |
2 | #include <linux/signal.h> | |
3 | #include <linux/sched.h> | |
4 | #include <linux/ioport.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/slab.h> | |
7 | #include <linux/random.h> | |
1da177e4 LT |
8 | #include <linux/init.h> |
9 | #include <linux/kernel_stat.h> | |
10 | #include <linux/sysdev.h> | |
11 | #include <linux/bitops.h> | |
aa09e6cd JSR |
12 | #include <linux/io.h> |
13 | #include <linux/delay.h> | |
1da177e4 | 14 | |
1da177e4 LT |
15 | #include <asm/atomic.h> |
16 | #include <asm/system.h> | |
1da177e4 LT |
17 | #include <asm/timer.h> |
18 | #include <asm/pgtable.h> | |
1da177e4 LT |
19 | #include <asm/desc.h> |
20 | #include <asm/apic.h> | |
8e6dafd6 | 21 | #include <asm/setup.h> |
1da177e4 | 22 | #include <asm/i8259.h> |
aa09e6cd | 23 | #include <asm/traps.h> |
1da177e4 | 24 | |
1da177e4 LT |
25 | |
26 | /* | |
27 | * Note that on a 486, we don't want to do a SIGFPE on an irq13 | |
28 | * as the irq is unreliable, and exception 16 works correctly | |
29 | * (ie as explained in the intel literature). On a 386, you | |
30 | * can't use exception 16 due to bad IBM design, so we have to | |
31 | * rely on the less exact irq13. | |
32 | * | |
33 | * Careful.. Not only is IRQ13 unreliable, but it is also | |
34 | * leads to races. IBM designers who came up with it should | |
35 | * be shot. | |
36 | */ | |
1da177e4 | 37 | |
7d12e780 | 38 | static irqreturn_t math_error_irq(int cpl, void *dev_id) |
1da177e4 | 39 | { |
aa09e6cd | 40 | outb(0, 0xF0); |
1da177e4 LT |
41 | if (ignore_fpu_irq || !boot_cpu_data.hard_math) |
42 | return IRQ_NONE; | |
65ea5b03 | 43 | math_error((void __user *)get_irq_regs()->ip); |
1da177e4 LT |
44 | return IRQ_HANDLED; |
45 | } | |
46 | ||
47 | /* | |
48 | * New motherboards sometimes make IRQ 13 be a PCI interrupt, | |
49 | * so allow interrupt sharing. | |
50 | */ | |
6a61f6a5 TG |
51 | static struct irqaction fpu_irq = { |
52 | .handler = math_error_irq, | |
6a61f6a5 TG |
53 | .name = "fpu", |
54 | }; | |
1da177e4 | 55 | |
aa09e6cd | 56 | void __init init_ISA_irqs(void) |
1da177e4 LT |
57 | { |
58 | int i; | |
59 | ||
60 | #ifdef CONFIG_X86_LOCAL_APIC | |
61 | init_bsp_APIC(); | |
62 | #endif | |
63 | init_8259A(0); | |
64 | ||
7c6357da AD |
65 | /* |
66 | * 16 old-style INTA-cycle interrupts: | |
67 | */ | |
99d093d1 | 68 | for (i = 0; i < NR_IRQS_LEGACY; i++) { |
ee32c973 | 69 | struct irq_desc *desc = irq_to_desc(i); |
199751d7 YL |
70 | |
71 | desc->status = IRQ_DISABLED; | |
72 | desc->action = NULL; | |
73 | desc->depth = 1; | |
74 | ||
7c6357da AD |
75 | set_irq_chip_and_handler_name(i, &i8259A_chip, |
76 | handle_level_irq, "XT"); | |
1da177e4 LT |
77 | } |
78 | } | |
79 | ||
2ae111cd CG |
80 | /* |
81 | * IRQ2 is cascade interrupt to second interrupt controller | |
82 | */ | |
83 | static struct irqaction irq2 = { | |
84 | .handler = no_action, | |
2ae111cd CG |
85 | .name = "cascade", |
86 | }; | |
87 | ||
497c9a19 YL |
88 | DEFINE_PER_CPU(vector_irq_t, vector_irq) = { |
89 | [0 ... IRQ0_VECTOR - 1] = -1, | |
90 | [IRQ0_VECTOR] = 0, | |
91 | [IRQ1_VECTOR] = 1, | |
92 | [IRQ2_VECTOR] = 2, | |
93 | [IRQ3_VECTOR] = 3, | |
94 | [IRQ4_VECTOR] = 4, | |
95 | [IRQ5_VECTOR] = 5, | |
96 | [IRQ6_VECTOR] = 6, | |
97 | [IRQ7_VECTOR] = 7, | |
98 | [IRQ8_VECTOR] = 8, | |
99 | [IRQ9_VECTOR] = 9, | |
100 | [IRQ10_VECTOR] = 10, | |
101 | [IRQ11_VECTOR] = 11, | |
102 | [IRQ12_VECTOR] = 12, | |
103 | [IRQ13_VECTOR] = 13, | |
104 | [IRQ14_VECTOR] = 14, | |
105 | [IRQ15_VECTOR] = 15, | |
106 | [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1 | |
107 | }; | |
108 | ||
b77b881f YL |
109 | int vector_used_by_percpu_irq(unsigned int vector) |
110 | { | |
111 | int cpu; | |
112 | ||
113 | for_each_online_cpu(cpu) { | |
114 | if (per_cpu(vector_irq, cpu)[vector] != -1) | |
115 | return 1; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
d3561b7f RR |
121 | /* Overridden in paravirt.c */ |
122 | void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ"))); | |
123 | ||
124 | void __init native_init_IRQ(void) | |
1da177e4 LT |
125 | { |
126 | int i; | |
127 | ||
8e6dafd6 IM |
128 | /* Execute any quirks before the call gates are initialised: */ |
129 | x86_quirk_pre_intr_init(); | |
1da177e4 LT |
130 | |
131 | /* | |
132 | * Cover the whole vector space, no vector can escape | |
133 | * us. (some of these will be overridden and become | |
134 | * 'special' SMP interrupts) | |
135 | */ | |
497c9a19 | 136 | for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) { |
dbeb2be2 | 137 | /* SYSCALL_VECTOR was reserved in trap_init. */ |
497c9a19 | 138 | if (i != SYSCALL_VECTOR) |
4687518c | 139 | set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]); |
1da177e4 LT |
140 | } |
141 | ||
2ae111cd | 142 | |
497c9a19 | 143 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP) |
2ae111cd CG |
144 | /* |
145 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
146 | * IPI, driven by wakeup. | |
147 | */ | |
148 | alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
149 | ||
02cf94c3 TH |
150 | /* IPIs for invalidation */ |
151 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0); | |
152 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1); | |
153 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2); | |
154 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3); | |
155 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4); | |
156 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5); | |
157 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6); | |
158 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7); | |
2ae111cd CG |
159 | |
160 | /* IPI for generic function call */ | |
161 | alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
162 | ||
163 | /* IPI for single call function */ | |
b77b881f YL |
164 | alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, |
165 | call_function_single_interrupt); | |
497c9a19 YL |
166 | |
167 | /* Low priority IPI to cleanup after moving an irq */ | |
168 | set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt); | |
b77b881f | 169 | set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors); |
2ae111cd CG |
170 | #endif |
171 | ||
172 | #ifdef CONFIG_X86_LOCAL_APIC | |
173 | /* self generated IPI for local APIC timer */ | |
174 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
175 | ||
acaabe79 DS |
176 | /* generic IPI for platform specific use */ |
177 | alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt); | |
178 | ||
2ae111cd CG |
179 | /* IPI vectors for APIC spurious and error interrupts */ |
180 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
181 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
182 | #endif | |
183 | ||
4efc0670 | 184 | #ifdef CONFIG_X86_THERMAL_VECTOR |
2ae111cd CG |
185 | /* thermal monitor LVT interrupt */ |
186 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
187 | #endif | |
188 | ||
7856f6cc AK |
189 | #ifdef CONFIG_X86_MCE_THRESHOLD |
190 | alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); | |
191 | #endif | |
192 | ||
2ae111cd CG |
193 | if (!acpi_ioapic) |
194 | setup_irq(2, &irq2); | |
195 | ||
8e6dafd6 IM |
196 | /* |
197 | * Call quirks after call gates are initialised (usually add in | |
198 | * the architecture specific gates): | |
1da177e4 | 199 | */ |
8e6dafd6 | 200 | x86_quirk_intr_init(); |
1da177e4 | 201 | |
1da177e4 LT |
202 | /* |
203 | * External FPU? Set up irq13 if so, for | |
204 | * original braindamaged IBM FERR coupling. | |
205 | */ | |
206 | if (boot_cpu_data.hard_math && !cpu_has_fpu) | |
207 | setup_irq(FPU_IRQ, &fpu_irq); | |
208 | ||
209 | irq_ctx_init(smp_processor_id()); | |
210 | } |