]>
Commit | Line | Data |
---|---|---|
d39398a3 YL |
1 | /* |
2 | * AMD Family 10h mmconfig enablement | |
3 | */ | |
4 | ||
5 | #include <linux/types.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/string.h> | |
8 | #include <linux/pci.h> | |
5f0b2976 | 9 | #include <linux/dmi.h> |
d39398a3 YL |
10 | #include <asm/pci-direct.h> |
11 | #include <linux/sort.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/msr.h> | |
14 | #include <asm/acpi.h> | |
d1097635 | 15 | #include <asm/mmconfig.h> |
d39398a3 | 16 | |
5f0b2976 YL |
17 | #include "../pci/pci.h" |
18 | ||
d39398a3 YL |
19 | struct pci_hostbridge_probe { |
20 | u32 bus; | |
21 | u32 slot; | |
22 | u32 vendor; | |
23 | u32 device; | |
24 | }; | |
25 | ||
26 | static u64 __cpuinitdata fam10h_pci_mmconf_base; | |
27 | static int __cpuinitdata fam10h_pci_mmconf_base_status; | |
28 | ||
29 | static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = { | |
30 | { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 }, | |
31 | { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 }, | |
32 | }; | |
33 | ||
34 | struct range { | |
35 | u64 start; | |
36 | u64 end; | |
37 | }; | |
38 | ||
39 | static int __cpuinit cmp_range(const void *x1, const void *x2) | |
40 | { | |
41 | const struct range *r1 = x1; | |
42 | const struct range *r2 = x2; | |
43 | int start1, start2; | |
44 | ||
45 | start1 = r1->start >> 32; | |
46 | start2 = r2->start >> 32; | |
47 | ||
48 | return start1 - start2; | |
49 | } | |
50 | ||
51 | /*[47:0] */ | |
52 | /* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */ | |
53 | #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32) | |
54 | #define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32))) | |
55 | static void __cpuinit get_fam10h_pci_mmconf_base(void) | |
56 | { | |
57 | int i; | |
58 | unsigned bus; | |
59 | unsigned slot; | |
60 | int found; | |
61 | ||
62 | u64 val; | |
63 | u32 address; | |
64 | u64 tom2; | |
65 | u64 base = FAM10H_PCI_MMCONF_BASE; | |
66 | ||
67 | int hi_mmio_num; | |
68 | struct range range[8]; | |
69 | ||
70 | /* only try to get setting from BSP */ | |
71 | /* -1 or 1 */ | |
72 | if (fam10h_pci_mmconf_base_status) | |
73 | return; | |
74 | ||
75 | if (!early_pci_allowed()) | |
76 | goto fail; | |
77 | ||
78 | found = 0; | |
79 | for (i = 0; i < ARRAY_SIZE(pci_probes); i++) { | |
80 | u32 id; | |
81 | u16 device; | |
82 | u16 vendor; | |
83 | ||
84 | bus = pci_probes[i].bus; | |
85 | slot = pci_probes[i].slot; | |
86 | id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); | |
87 | ||
88 | vendor = id & 0xffff; | |
89 | device = (id>>16) & 0xffff; | |
90 | if (pci_probes[i].vendor == vendor && | |
91 | pci_probes[i].device == device) { | |
92 | found = 1; | |
93 | break; | |
94 | } | |
95 | } | |
96 | ||
97 | if (!found) | |
98 | goto fail; | |
99 | ||
100 | /* SYS_CFG */ | |
101 | address = MSR_K8_SYSCFG; | |
102 | rdmsrl(address, val); | |
103 | ||
104 | /* TOP_MEM2 is not enabled? */ | |
105 | if (!(val & (1<<21))) { | |
106 | tom2 = 0; | |
107 | } else { | |
108 | /* TOP_MEM2 */ | |
109 | address = MSR_K8_TOP_MEM2; | |
110 | rdmsrl(address, val); | |
111 | tom2 = val & (0xffffULL<<32); | |
112 | } | |
113 | ||
114 | if (base <= tom2) | |
115 | base = tom2 + (1ULL<<32); | |
116 | ||
117 | /* | |
118 | * need to check if the range is in the high mmio range that is | |
119 | * above 4G | |
120 | */ | |
121 | hi_mmio_num = 0; | |
122 | for (i = 0; i < 8; i++) { | |
123 | u32 reg; | |
124 | u64 start; | |
125 | u64 end; | |
126 | reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); | |
127 | if (!(reg & 3)) | |
128 | continue; | |
129 | ||
130 | start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/ | |
131 | reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); | |
132 | end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/ | |
133 | ||
134 | if (!end) | |
135 | continue; | |
136 | ||
137 | range[hi_mmio_num].start = start; | |
138 | range[hi_mmio_num].end = end; | |
139 | hi_mmio_num++; | |
140 | } | |
141 | ||
142 | if (!hi_mmio_num) | |
143 | goto out; | |
144 | ||
145 | /* sort the range */ | |
146 | sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL); | |
147 | ||
148 | if (range[hi_mmio_num - 1].end < base) | |
149 | goto out; | |
150 | if (range[0].start > base) | |
151 | goto out; | |
152 | ||
153 | /* need to find one window */ | |
154 | base = range[0].start - (1ULL << 32); | |
155 | if ((base > tom2) && BASE_VALID(base)) | |
156 | goto out; | |
157 | base = range[hi_mmio_num - 1].end + (1ULL << 32); | |
158 | if ((base > tom2) && BASE_VALID(base)) | |
159 | goto out; | |
160 | /* need to find window between ranges */ | |
161 | if (hi_mmio_num > 1) | |
162 | for (i = 0; i < hi_mmio_num - 1; i++) { | |
163 | if (range[i + 1].start > (range[i].end + (1ULL << 32))) { | |
164 | base = range[i].end + (1ULL << 32); | |
165 | if ((base > tom2) && BASE_VALID(base)) | |
166 | goto out; | |
167 | } | |
168 | } | |
169 | ||
170 | fail: | |
171 | fam10h_pci_mmconf_base_status = -1; | |
172 | return; | |
173 | out: | |
174 | fam10h_pci_mmconf_base = base; | |
175 | fam10h_pci_mmconf_base_status = 1; | |
176 | } | |
177 | ||
178 | void __cpuinit fam10h_check_enable_mmcfg(void) | |
179 | { | |
180 | u64 val; | |
181 | u32 address; | |
182 | ||
5f0b2976 YL |
183 | if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) |
184 | return; | |
185 | ||
d39398a3 YL |
186 | address = MSR_FAM10H_MMIO_CONF_BASE; |
187 | rdmsrl(address, val); | |
188 | ||
189 | /* try to make sure that AP's setting is identical to BSP setting */ | |
190 | if (val & FAM10H_MMIO_CONF_ENABLE) { | |
191 | unsigned busnbits; | |
192 | busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & | |
193 | FAM10H_MMIO_CONF_BUSRANGE_MASK; | |
194 | ||
195 | /* only trust the one handle 256 buses, if acpi=off */ | |
196 | if (!acpi_pci_disabled || busnbits >= 8) { | |
197 | u64 base; | |
198 | base = val & (0xffffULL << 32); | |
199 | if (fam10h_pci_mmconf_base_status <= 0) { | |
200 | fam10h_pci_mmconf_base = base; | |
201 | fam10h_pci_mmconf_base_status = 1; | |
202 | return; | |
203 | } else if (fam10h_pci_mmconf_base == base) | |
204 | return; | |
205 | } | |
206 | } | |
207 | ||
208 | /* | |
209 | * if it is not enabled, try to enable it and assume only one segment | |
210 | * with 256 buses | |
211 | */ | |
212 | get_fam10h_pci_mmconf_base(); | |
213 | if (fam10h_pci_mmconf_base_status <= 0) | |
214 | return; | |
215 | ||
216 | printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n"); | |
217 | val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) | | |
218 | (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT)); | |
219 | val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) | | |
220 | FAM10H_MMIO_CONF_ENABLE; | |
221 | wrmsrl(address, val); | |
222 | } | |
5f0b2976 YL |
223 | |
224 | static int __devinit set_check_enable_amd_mmconf(const struct dmi_system_id *d) | |
225 | { | |
226 | pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF; | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static struct dmi_system_id __devinitdata mmconf_dmi_table[] = { | |
231 | { | |
232 | .callback = set_check_enable_amd_mmconf, | |
233 | .ident = "Sun Microsystems Machine", | |
234 | .matches = { | |
235 | DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"), | |
236 | }, | |
237 | }, | |
238 | {} | |
239 | }; | |
240 | ||
c72a5efe | 241 | void __cpuinit check_enable_amd_mmconf_dmi(void) |
5f0b2976 YL |
242 | { |
243 | dmi_check_system(mmconf_dmi_table); | |
244 | } |