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Commit | Line | Data |
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1da177e4 | 1 | /* |
11113f84 | 2 | * Intel Multiprocessor Specification 1.1 and 1.4 |
1da177e4 LT |
3 | * compliant MP-table parsing routines. |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
85bdddec | 7 | * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/mm.h> | |
1da177e4 | 11 | #include <linux/init.h> |
1da177e4 | 12 | #include <linux/delay.h> |
1da177e4 | 13 | #include <linux/bootmem.h> |
72d7c3b3 | 14 | #include <linux/memblock.h> |
1da177e4 LT |
15 | #include <linux/kernel_stat.h> |
16 | #include <linux/mc146818rtc.h> | |
17 | #include <linux/bitops.h> | |
85bdddec | 18 | #include <linux/acpi.h> |
103ceffb | 19 | #include <linux/smp.h> |
629e15d2 | 20 | #include <linux/pci.h> |
1da177e4 | 21 | |
f7a0c786 | 22 | #include <asm/irqdomain.h> |
1da177e4 LT |
23 | #include <asm/mtrr.h> |
24 | #include <asm/mpspec.h> | |
85bdddec | 25 | #include <asm/pgalloc.h> |
1da177e4 | 26 | #include <asm/io_apic.h> |
85bdddec | 27 | #include <asm/proto.h> |
ce3fe6b2 | 28 | #include <asm/bios_ebda.h> |
2944e16b | 29 | #include <asm/e820.h> |
3c9cb6de | 30 | #include <asm/setup.h> |
4884d8e6 | 31 | #include <asm/smp.h> |
1da177e4 | 32 | |
7b6aa335 | 33 | #include <asm/apic.h> |
1da177e4 LT |
34 | /* |
35 | * Checksum an MP configuration block. | |
36 | */ | |
37 | ||
38 | static int __init mpf_checksum(unsigned char *mp, int len) | |
39 | { | |
40 | int sum = 0; | |
41 | ||
42 | while (len--) | |
43 | sum += *mp++; | |
44 | ||
45 | return sum & 0xFF; | |
46 | } | |
47 | ||
fd6c6661 TG |
48 | int __init default_mpc_apic_id(struct mpc_cpu *m) |
49 | { | |
50 | return m->apicid; | |
51 | } | |
52 | ||
f4f21b71 | 53 | static void __init MP_processor_info(struct mpc_cpu *m) |
c853c676 AS |
54 | { |
55 | int apicid; | |
746f2244 | 56 | char *bootup_cpu = ""; |
c853c676 | 57 | |
c4563826 | 58 | if (!(m->cpuflag & CPU_ENABLED)) { |
7b1292e2 | 59 | disabled_cpus++; |
1da177e4 | 60 | return; |
7b1292e2 | 61 | } |
64898a8b | 62 | |
fd6c6661 | 63 | apicid = x86_init.mpparse.mpc_apic_id(m); |
64898a8b | 64 | |
c4563826 | 65 | if (m->cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 66 | bootup_cpu = " (Bootup-CPU)"; |
c4563826 | 67 | boot_cpu_physical_apicid = m->apicid; |
1da177e4 LT |
68 | } |
69 | ||
b1bfd5ea | 70 | pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); |
c4563826 | 71 | generic_processor_info(apicid, m->apicver); |
1da177e4 LT |
72 | } |
73 | ||
85cc35fa | 74 | #ifdef CONFIG_X86_IO_APIC |
90e1c696 | 75 | void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str) |
1da177e4 | 76 | { |
d4c715fa | 77 | memcpy(str, m->bustype, 6); |
1da177e4 | 78 | str[6] = 0; |
90e1c696 TG |
79 | apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); |
80 | } | |
1da177e4 | 81 | |
90e1c696 TG |
82 | static void __init MP_bus_info(struct mpc_bus *m) |
83 | { | |
84 | char str[7]; | |
1da177e4 | 85 | |
90e1c696 | 86 | x86_init.mpparse.mpc_oem_bus_info(m, str); |
1da177e4 | 87 | |
5e4edbb7 | 88 | #if MAX_MP_BUSSES < 256 |
d4c715fa | 89 | if (m->busid >= MAX_MP_BUSSES) { |
b1bfd5ea JL |
90 | pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n", |
91 | m->busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
92 | return; |
93 | } | |
5e4edbb7 | 94 | #endif |
c0ec31ad | 95 | |
9e686668 | 96 | set_bit(m->busid, mp_bus_not_pci); |
f8924e77 | 97 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
bb8187d3 | 98 | #ifdef CONFIG_EISA |
d4c715fa | 99 | mp_bus_id_to_type[m->busid] = MP_BUS_ISA; |
f8924e77 AS |
100 | #endif |
101 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
52fdb568 TG |
102 | if (x86_init.mpparse.mpc_oem_pci_bus) |
103 | x86_init.mpparse.mpc_oem_pci_bus(m); | |
64898a8b | 104 | |
d4c715fa | 105 | clear_bit(m->busid, mp_bus_not_pci); |
bb8187d3 | 106 | #ifdef CONFIG_EISA |
d4c715fa | 107 | mp_bus_id_to_type[m->busid] = MP_BUS_PCI; |
4ef81297 | 108 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
d4c715fa | 109 | mp_bus_id_to_type[m->busid] = MP_BUS_EISA; |
c0a282c2 | 110 | #endif |
f8924e77 | 111 | } else |
b1bfd5ea | 112 | pr_warn("Unknown bustype %s - ignoring\n", str); |
1da177e4 | 113 | } |
61048c63 | 114 | |
2b85b5fb | 115 | static void __init MP_ioapic_info(struct mpc_ioapic *m) |
1da177e4 | 116 | { |
74501edc JL |
117 | struct ioapic_domain_cfg cfg = { |
118 | .type = IOAPIC_DOMAIN_LEGACY, | |
119 | .ops = &mp_ioapic_irqdomain_ops, | |
120 | }; | |
121 | ||
0e3fa13f | 122 | if (m->flags & MPC_APIC_USABLE) |
74501edc | 123 | mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg); |
2944e16b YL |
124 | } |
125 | ||
c2c21745 | 126 | static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) |
2944e16b | 127 | { |
b1bfd5ea JL |
128 | apic_printk(APIC_VERBOSE, |
129 | "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
c2c21745 JSR |
130 | mp_irq->irqtype, mp_irq->irqflag & 3, |
131 | (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus, | |
132 | mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); | |
2944e16b YL |
133 | } |
134 | ||
a6830278 JSR |
135 | #else /* CONFIG_X86_IO_APIC */ |
136 | static inline void __init MP_bus_info(struct mpc_bus *m) {} | |
137 | static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {} | |
a6830278 | 138 | #endif /* CONFIG_X86_IO_APIC */ |
1da177e4 | 139 | |
8fb2952b | 140 | static void __init MP_lintsrc_info(struct mpc_lintsrc *m) |
1da177e4 | 141 | { |
b1bfd5ea JL |
142 | apic_printk(APIC_VERBOSE, |
143 | "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
b5ced7cd JSR |
144 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid, |
145 | m->srcbusirq, m->destapic, m->destapiclint); | |
1da177e4 LT |
146 | } |
147 | ||
1da177e4 LT |
148 | /* |
149 | * Read/parse the MPC | |
150 | */ | |
f29521e4 | 151 | static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str) |
1da177e4 | 152 | { |
1da177e4 | 153 | |
6c65da50 | 154 | if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) { |
b1bfd5ea | 155 | pr_err("MPTABLE: bad signature [%c%c%c%c]!\n", |
6c65da50 JSR |
156 | mpc->signature[0], mpc->signature[1], |
157 | mpc->signature[2], mpc->signature[3]); | |
1da177e4 LT |
158 | return 0; |
159 | } | |
6c65da50 | 160 | if (mpf_checksum((unsigned char *)mpc, mpc->length)) { |
b1bfd5ea | 161 | pr_err("MPTABLE: checksum error!\n"); |
1da177e4 LT |
162 | return 0; |
163 | } | |
6c65da50 | 164 | if (mpc->spec != 0x01 && mpc->spec != 0x04) { |
b1bfd5ea | 165 | pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec); |
1da177e4 LT |
166 | return 0; |
167 | } | |
6c65da50 | 168 | if (!mpc->lapic) { |
b1bfd5ea | 169 | pr_err("MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
170 | return 0; |
171 | } | |
6c65da50 | 172 | memcpy(oem, mpc->oem, 8); |
4ef81297 | 173 | oem[8] = 0; |
b1bfd5ea | 174 | pr_info("MPTABLE: OEM ID: %s\n", oem); |
1da177e4 | 175 | |
6c65da50 | 176 | memcpy(str, mpc->productid, 12); |
4ef81297 | 177 | str[12] = 0; |
1da177e4 | 178 | |
b1bfd5ea | 179 | pr_info("MPTABLE: Product ID: %s\n", str); |
1da177e4 | 180 | |
b1bfd5ea | 181 | pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic); |
1da177e4 | 182 | |
2944e16b YL |
183 | return 1; |
184 | } | |
185 | ||
a6830278 JSR |
186 | static void skip_entry(unsigned char **ptr, int *count, int size) |
187 | { | |
188 | *ptr += size; | |
189 | *count += size; | |
190 | } | |
191 | ||
5a5737ea JSR |
192 | static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) |
193 | { | |
b1bfd5ea JL |
194 | pr_err("Your mptable is wrong, contact your HW vendor!\n"); |
195 | pr_cont("type %x\n", *mpt); | |
5a5737ea JSR |
196 | print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, |
197 | 1, mpc, mpc->length, 1); | |
198 | } | |
199 | ||
72302142 TG |
200 | void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } |
201 | ||
f29521e4 | 202 | static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) |
2944e16b YL |
203 | { |
204 | char str[16]; | |
205 | char oem[10]; | |
206 | ||
207 | int count = sizeof(*mpc); | |
208 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
209 | ||
210 | if (!smp_check_mpc(mpc, oem, str)) | |
211 | return 0; | |
212 | ||
f1157141 | 213 | /* Initialize the lapic mapping */ |
1da177e4 | 214 | if (!acpi_lapic) |
f1157141 | 215 | register_lapic_address(mpc->lapic); |
1da177e4 | 216 | |
888032cd AS |
217 | if (early) |
218 | return 1; | |
219 | ||
72302142 TG |
220 | if (mpc->oemptr) |
221 | x86_init.mpparse.smp_read_mpc_oem(mpc); | |
64898a8b | 222 | |
1da177e4 | 223 | /* |
4ef81297 | 224 | * Now process the configuration blocks. |
1da177e4 | 225 | */ |
f4848472 | 226 | x86_init.mpparse.mpc_record(0); |
64898a8b | 227 | |
6c65da50 | 228 | while (count < mpc->length) { |
4ef81297 AS |
229 | switch (*mpt) { |
230 | case MP_PROCESSOR: | |
a6830278 JSR |
231 | /* ACPI may have already provided this data */ |
232 | if (!acpi_lapic) | |
c58603e8 | 233 | MP_processor_info((struct mpc_cpu *)mpt); |
a6830278 JSR |
234 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
235 | break; | |
4ef81297 | 236 | case MP_BUS: |
c58603e8 | 237 | MP_bus_info((struct mpc_bus *)mpt); |
a6830278 JSR |
238 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
239 | break; | |
4ef81297 | 240 | case MP_IOAPIC: |
c58603e8 | 241 | MP_ioapic_info((struct mpc_ioapic *)mpt); |
a6830278 JSR |
242 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
243 | break; | |
4ef81297 | 244 | case MP_INTSRC: |
2d8009ba | 245 | mp_save_irq((struct mpc_intsrc *)mpt); |
a6830278 JSR |
246 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
247 | break; | |
4ef81297 | 248 | case MP_LINTSRC: |
c58603e8 | 249 | MP_lintsrc_info((struct mpc_lintsrc *)mpt); |
a6830278 JSR |
250 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
251 | break; | |
4ef81297 | 252 | default: |
711554db | 253 | /* wrong mptable */ |
5a5737ea | 254 | smp_dump_mptable(mpc, mpt); |
6c65da50 | 255 | count = mpc->length; |
711554db | 256 | break; |
1da177e4 | 257 | } |
f4848472 | 258 | x86_init.mpparse.mpc_record(1); |
1da177e4 | 259 | } |
e0da3364 | 260 | |
1da177e4 | 261 | if (!num_processors) |
b1bfd5ea | 262 | pr_err("MPTABLE: no processors registered!\n"); |
1da177e4 LT |
263 | return num_processors; |
264 | } | |
265 | ||
61048c63 AS |
266 | #ifdef CONFIG_X86_IO_APIC |
267 | ||
1da177e4 LT |
268 | static int __init ELCR_trigger(unsigned int irq) |
269 | { | |
270 | unsigned int port; | |
271 | ||
272 | port = 0x4d0 + (irq >> 3); | |
273 | return (inb(port) >> (irq & 7)) & 1; | |
274 | } | |
275 | ||
276 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
277 | { | |
540d4e72 | 278 | struct mpc_intsrc intsrc; |
1da177e4 LT |
279 | int i; |
280 | int ELCR_fallback = 0; | |
281 | ||
e253b396 JSR |
282 | intsrc.type = MP_INTSRC; |
283 | intsrc.irqflag = 0; /* conforming */ | |
284 | intsrc.srcbus = 0; | |
d5371430 | 285 | intsrc.dstapic = mpc_ioapic_id(0); |
1da177e4 | 286 | |
e253b396 | 287 | intsrc.irqtype = mp_INT; |
1da177e4 LT |
288 | |
289 | /* | |
290 | * If true, we have an ISA/PCI system with no IRQ entries | |
291 | * in the MP table. To prevent the PCI interrupts from being set up | |
292 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
293 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
294 | * never be level sensitive, so we simply see if the ELCR agrees. | |
295 | * If it does, we assume it's valid. | |
296 | */ | |
297 | if (mpc_default_type == 5) { | |
b1bfd5ea | 298 | pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); |
1da177e4 | 299 | |
62441bf1 AS |
300 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
301 | ELCR_trigger(13)) | |
b1bfd5ea | 302 | pr_err("ELCR contains invalid data... not using ELCR\n"); |
1da177e4 | 303 | else { |
b1bfd5ea | 304 | pr_info("Using ELCR to identify PCI interrupts\n"); |
1da177e4 LT |
305 | ELCR_fallback = 1; |
306 | } | |
307 | } | |
308 | ||
309 | for (i = 0; i < 16; i++) { | |
310 | switch (mpc_default_type) { | |
311 | case 2: | |
312 | if (i == 0 || i == 13) | |
313 | continue; /* IRQ0 & IRQ13 not connected */ | |
314 | /* fall through */ | |
315 | default: | |
316 | if (i == 2) | |
317 | continue; /* IRQ2 is never connected */ | |
318 | } | |
319 | ||
320 | if (ELCR_fallback) { | |
321 | /* | |
322 | * If the ELCR indicates a level-sensitive interrupt, we | |
323 | * copy that information over to the MP table in the | |
324 | * irqflag field (level sensitive, active high polarity). | |
325 | */ | |
326 | if (ELCR_trigger(i)) | |
e253b396 | 327 | intsrc.irqflag = 13; |
1da177e4 | 328 | else |
e253b396 | 329 | intsrc.irqflag = 0; |
1da177e4 LT |
330 | } |
331 | ||
e253b396 JSR |
332 | intsrc.srcbusirq = i; |
333 | intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
2d8009ba | 334 | mp_save_irq(&intsrc); |
1da177e4 LT |
335 | } |
336 | ||
e253b396 JSR |
337 | intsrc.irqtype = mp_ExtINT; |
338 | intsrc.srcbusirq = 0; | |
339 | intsrc.dstirq = 0; /* 8259A to INTIN0 */ | |
2d8009ba | 340 | mp_save_irq(&intsrc); |
1da177e4 LT |
341 | } |
342 | ||
61048c63 | 343 | |
39e00fe2 | 344 | static void __init construct_ioapic_table(int mpc_default_type) |
1da177e4 | 345 | { |
2b85b5fb | 346 | struct mpc_ioapic ioapic; |
00fb8606 | 347 | struct mpc_bus bus; |
1da177e4 | 348 | |
d4c715fa JSR |
349 | bus.type = MP_BUS; |
350 | bus.busid = 0; | |
1da177e4 | 351 | switch (mpc_default_type) { |
4ef81297 | 352 | default: |
b1bfd5ea | 353 | pr_err("???\nUnknown standard configuration %d\n", |
4ef81297 AS |
354 | mpc_default_type); |
355 | /* fall through */ | |
356 | case 1: | |
357 | case 5: | |
d4c715fa | 358 | memcpy(bus.bustype, "ISA ", 6); |
4ef81297 AS |
359 | break; |
360 | case 2: | |
361 | case 6: | |
362 | case 3: | |
d4c715fa | 363 | memcpy(bus.bustype, "EISA ", 6); |
4ef81297 | 364 | break; |
1da177e4 LT |
365 | } |
366 | MP_bus_info(&bus); | |
367 | if (mpc_default_type > 4) { | |
d4c715fa JSR |
368 | bus.busid = 1; |
369 | memcpy(bus.bustype, "PCI ", 6); | |
1da177e4 LT |
370 | MP_bus_info(&bus); |
371 | } | |
372 | ||
8f3e1df4 CG |
373 | ioapic.type = MP_IOAPIC; |
374 | ioapic.apicid = 2; | |
375 | ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
376 | ioapic.flags = MPC_APIC_USABLE; | |
377 | ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
378 | MP_ioapic_info(&ioapic); |
379 | ||
380 | /* | |
381 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
382 | */ | |
383 | construct_default_ioirq_mptable(mpc_default_type); | |
85cc35fa TG |
384 | } |
385 | #else | |
39e00fe2 | 386 | static inline void __init construct_ioapic_table(int mpc_default_type) { } |
61048c63 | 387 | #endif |
85cc35fa TG |
388 | |
389 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
390 | { | |
f4f21b71 | 391 | struct mpc_cpu processor; |
8fb2952b | 392 | struct mpc_lintsrc lintsrc; |
85cc35fa TG |
393 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
394 | int i; | |
395 | ||
396 | /* | |
397 | * local APIC has default address | |
398 | */ | |
399 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
400 | ||
401 | /* | |
402 | * 2 CPUs, numbered 0 & 1. | |
403 | */ | |
c4563826 | 404 | processor.type = MP_PROCESSOR; |
85cc35fa | 405 | /* Either an integrated APIC or a discrete 82489DX. */ |
c4563826 JSR |
406 | processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
407 | processor.cpuflag = CPU_ENABLED; | |
408 | processor.cpufeature = (boot_cpu_data.x86 << 8) | | |
85cc35fa | 409 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
16aaa537 | 410 | processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX]; |
c4563826 JSR |
411 | processor.reserved[0] = 0; |
412 | processor.reserved[1] = 0; | |
85cc35fa | 413 | for (i = 0; i < 2; i++) { |
c4563826 | 414 | processor.apicid = i; |
85cc35fa TG |
415 | MP_processor_info(&processor); |
416 | } | |
417 | ||
418 | construct_ioapic_table(mpc_default_type); | |
419 | ||
b5ced7cd JSR |
420 | lintsrc.type = MP_LINTSRC; |
421 | lintsrc.irqflag = 0; /* conforming */ | |
422 | lintsrc.srcbusid = 0; | |
423 | lintsrc.srcbusirq = 0; | |
424 | lintsrc.destapic = MP_APIC_ALL; | |
1da177e4 | 425 | for (i = 0; i < 2; i++) { |
b5ced7cd JSR |
426 | lintsrc.irqtype = linttypes[i]; |
427 | lintsrc.destapiclint = i; | |
1da177e4 LT |
428 | MP_lintsrc_info(&lintsrc); |
429 | } | |
430 | } | |
431 | ||
41401db6 | 432 | static struct mpf_intel *mpf_found; |
1da177e4 | 433 | |
8d4dd919 YL |
434 | static unsigned long __init get_mpc_size(unsigned long physptr) |
435 | { | |
436 | struct mpc_table *mpc; | |
437 | unsigned long size; | |
438 | ||
439 | mpc = early_ioremap(physptr, PAGE_SIZE); | |
440 | size = mpc->length; | |
441 | early_iounmap(mpc, PAGE_SIZE); | |
442 | apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); | |
443 | ||
444 | return size; | |
445 | } | |
446 | ||
0b3ba0c3 JSR |
447 | static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) |
448 | { | |
449 | struct mpc_table *mpc; | |
450 | unsigned long size; | |
451 | ||
452 | size = get_mpc_size(mpf->physptr); | |
453 | mpc = early_ioremap(mpf->physptr, size); | |
454 | /* | |
455 | * Read the physical hardware table. Anything here will | |
456 | * override the defaults. | |
457 | */ | |
458 | if (!smp_read_mpc(mpc, early)) { | |
459 | #ifdef CONFIG_X86_LOCAL_APIC | |
460 | smp_found_config = 0; | |
461 | #endif | |
b1bfd5ea JL |
462 | pr_err("BIOS bug, MP table errors detected!...\n"); |
463 | pr_cont("... disabling SMP support. (tell your hw vendor)\n"); | |
0b3ba0c3 JSR |
464 | early_iounmap(mpc, size); |
465 | return -1; | |
466 | } | |
467 | early_iounmap(mpc, size); | |
468 | ||
469 | if (early) | |
470 | return -1; | |
471 | ||
472 | #ifdef CONFIG_X86_IO_APIC | |
473 | /* | |
474 | * If there are no explicit MP IRQ entries, then we are | |
475 | * broken. We set up most of the low 16 IO-APIC pins to | |
476 | * ISA defaults and hope it will work. | |
477 | */ | |
478 | if (!mp_irq_entries) { | |
479 | struct mpc_bus bus; | |
480 | ||
b1bfd5ea | 481 | pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); |
0b3ba0c3 JSR |
482 | |
483 | bus.type = MP_BUS; | |
484 | bus.busid = 0; | |
485 | memcpy(bus.bustype, "ISA ", 6); | |
486 | MP_bus_info(&bus); | |
487 | ||
488 | construct_default_ioirq_mptable(0); | |
489 | } | |
490 | #endif | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
1da177e4 LT |
495 | /* |
496 | * Scan the memory blocks for an SMP configuration block. | |
497 | */ | |
b3f1b617 | 498 | void __init default_get_smp_config(unsigned int early) |
1da177e4 | 499 | { |
41401db6 | 500 | struct mpf_intel *mpf = mpf_found; |
1da177e4 | 501 | |
a91bf718 BH |
502 | if (!smp_found_config) |
503 | return; | |
504 | ||
69b88afa YL |
505 | if (!mpf) |
506 | return; | |
507 | ||
888032cd AS |
508 | if (acpi_lapic && early) |
509 | return; | |
69b88afa | 510 | |
1da177e4 | 511 | /* |
69b88afa YL |
512 | * MPS doesn't support hyperthreading, aka only have |
513 | * thread 0 apic id in MPS table | |
1da177e4 | 514 | */ |
69b88afa | 515 | if (acpi_lapic && acpi_ioapic) |
1da177e4 | 516 | return; |
1da177e4 | 517 | |
b1bfd5ea JL |
518 | pr_info("Intel MultiProcessor Specification v1.%d\n", |
519 | mpf->specification); | |
b3e24164 | 520 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
1eb1b3b6 | 521 | if (mpf->feature2 & (1 << 7)) { |
b1bfd5ea | 522 | pr_info(" IMCR and PIC compatibility mode.\n"); |
1da177e4 LT |
523 | pic_mode = 1; |
524 | } else { | |
b1bfd5ea | 525 | pr_info(" Virtual Wire compatibility mode.\n"); |
1da177e4 LT |
526 | pic_mode = 0; |
527 | } | |
4421b1c8 | 528 | #endif |
1da177e4 LT |
529 | /* |
530 | * Now see if we need to read further. | |
531 | */ | |
1eb1b3b6 | 532 | if (mpf->feature1 != 0) { |
888032cd AS |
533 | if (early) { |
534 | /* | |
535 | * local APIC has default address | |
536 | */ | |
537 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
538 | return; | |
539 | } | |
1da177e4 | 540 | |
b1bfd5ea | 541 | pr_info("Default MP configuration #%d\n", mpf->feature1); |
1eb1b3b6 | 542 | construct_default_ISA_mptable(mpf->feature1); |
1da177e4 | 543 | |
1eb1b3b6 | 544 | } else if (mpf->physptr) { |
0b3ba0c3 | 545 | if (check_physptr(mpf, early)) |
1da177e4 | 546 | return; |
1da177e4 LT |
547 | } else |
548 | BUG(); | |
549 | ||
888032cd | 550 | if (!early) |
b1bfd5ea | 551 | pr_info("Processors: %d\n", num_processors); |
1da177e4 LT |
552 | /* |
553 | * Only use the first configuration found. | |
554 | */ | |
555 | } | |
556 | ||
b24c2a92 | 557 | static void __init smp_reserve_memory(struct mpf_intel *mpf) |
a6830278 | 558 | { |
24aa0788 | 559 | memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); |
a6830278 JSR |
560 | } |
561 | ||
b24c2a92 | 562 | static int __init smp_scan_config(unsigned long base, unsigned long length) |
1da177e4 | 563 | { |
92fd4b7a | 564 | unsigned int *bp = phys_to_virt(base); |
41401db6 | 565 | struct mpf_intel *mpf; |
b24c2a92 | 566 | unsigned long mem; |
1da177e4 | 567 | |
365811d6 BH |
568 | apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", |
569 | base, base + length - 1); | |
5d47a271 | 570 | BUILD_BUG_ON(sizeof(*mpf) != 16); |
1da177e4 LT |
571 | |
572 | while (length > 0) { | |
41401db6 | 573 | mpf = (struct mpf_intel *)bp; |
1da177e4 | 574 | if ((*bp == SMP_MAGIC_IDENT) && |
1eb1b3b6 | 575 | (mpf->length == 1) && |
4ef81297 | 576 | !mpf_checksum((unsigned char *)bp, 16) && |
1eb1b3b6 JSR |
577 | ((mpf->specification == 1) |
578 | || (mpf->specification == 4))) { | |
bab4b27c | 579 | #ifdef CONFIG_X86_LOCAL_APIC |
1da177e4 | 580 | smp_found_config = 1; |
bab4b27c | 581 | #endif |
92fd4b7a | 582 | mpf_found = mpf; |
b1f006b6 | 583 | |
b1bfd5ea JL |
584 | pr_info("found SMP MP-table at [mem %#010llx-%#010llx] mapped at [%p]\n", |
585 | (unsigned long long) virt_to_phys(mpf), | |
586 | (unsigned long long) virt_to_phys(mpf) + | |
587 | sizeof(*mpf) - 1, mpf); | |
b1f006b6 | 588 | |
b24c2a92 | 589 | mem = virt_to_phys(mpf); |
24aa0788 | 590 | memblock_reserve(mem, sizeof(*mpf)); |
a6830278 | 591 | if (mpf->physptr) |
b24c2a92 | 592 | smp_reserve_memory(mpf); |
1da177e4 | 593 | |
d2dbf343 | 594 | return 1; |
1da177e4 LT |
595 | } |
596 | bp += 4; | |
597 | length -= 16; | |
598 | } | |
599 | return 0; | |
600 | } | |
601 | ||
b24c2a92 | 602 | void __init default_find_smp_config(void) |
1da177e4 LT |
603 | { |
604 | unsigned int address; | |
605 | ||
606 | /* | |
607 | * FIXME: Linux assumes you have 640K of base ram.. | |
608 | * this continues the error... | |
609 | * | |
610 | * 1) Scan the bottom 1K for a signature | |
611 | * 2) Scan the top 1K of base RAM | |
612 | * 3) Scan the 64K of bios | |
613 | */ | |
b24c2a92 YL |
614 | if (smp_scan_config(0x0, 0x400) || |
615 | smp_scan_config(639 * 0x400, 0x400) || | |
616 | smp_scan_config(0xF0000, 0x10000)) | |
1da177e4 LT |
617 | return; |
618 | /* | |
619 | * If it is an SMP machine we should know now, unless the | |
bb8187d3 | 620 | * configuration is in an EISA bus machine with an |
1da177e4 LT |
621 | * extended bios data area. |
622 | * | |
623 | * there is a real-mode segmented pointer pointing to the | |
624 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
625 | * | |
626 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
627 | * area, and as such this kind of SMP config may be less | |
628 | * trustworthy, simply because the SMP table may have been | |
629 | * stomped on during early boot. These loaders are buggy and | |
630 | * should be fixed. | |
631 | * | |
632 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
633 | */ | |
634 | ||
635 | address = get_bios_ebda(); | |
636 | if (address) | |
b24c2a92 | 637 | smp_scan_config(address, 0x400); |
888032cd AS |
638 | } |
639 | ||
2944e16b YL |
640 | #ifdef CONFIG_X86_IO_APIC |
641 | static u8 __initdata irq_used[MAX_IRQ_SOURCES]; | |
642 | ||
540d4e72 | 643 | static int __init get_MP_intsrc_index(struct mpc_intsrc *m) |
2944e16b YL |
644 | { |
645 | int i; | |
646 | ||
e253b396 | 647 | if (m->irqtype != mp_INT) |
2944e16b YL |
648 | return 0; |
649 | ||
e253b396 | 650 | if (m->irqflag != 0x0f) |
2944e16b YL |
651 | return 0; |
652 | ||
653 | /* not legacy */ | |
654 | ||
655 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 656 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
657 | continue; |
658 | ||
c2c21745 | 659 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
660 | continue; |
661 | ||
c2c21745 | 662 | if (mp_irqs[i].srcbus != m->srcbus) |
2944e16b | 663 | continue; |
c2c21745 | 664 | if (mp_irqs[i].srcbusirq != m->srcbusirq) |
2944e16b YL |
665 | continue; |
666 | if (irq_used[i]) { | |
667 | /* already claimed */ | |
668 | return -2; | |
669 | } | |
670 | irq_used[i] = 1; | |
671 | return i; | |
672 | } | |
673 | ||
674 | /* not found */ | |
675 | return -1; | |
676 | } | |
677 | ||
678 | #define SPARE_SLOT_NUM 20 | |
679 | ||
540d4e72 | 680 | static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM]; |
a6830278 | 681 | |
57592224 | 682 | static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) |
a6830278 JSR |
683 | { |
684 | int i; | |
685 | ||
686 | apic_printk(APIC_VERBOSE, "OLD "); | |
0e3fa13f | 687 | print_mp_irq_info(m); |
a6830278 JSR |
688 | |
689 | i = get_MP_intsrc_index(m); | |
690 | if (i > 0) { | |
0e3fa13f | 691 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
a6830278 JSR |
692 | apic_printk(APIC_VERBOSE, "NEW "); |
693 | print_mp_irq_info(&mp_irqs[i]); | |
694 | return; | |
695 | } | |
696 | if (!i) { | |
697 | /* legacy, do nothing */ | |
698 | return; | |
699 | } | |
700 | if (*nr_m_spare < SPARE_SLOT_NUM) { | |
701 | /* | |
702 | * not found (-1), or duplicated (-2) are invalid entries, | |
703 | * we need to use the slot later | |
704 | */ | |
705 | m_spare[*nr_m_spare] = m; | |
706 | *nr_m_spare += 1; | |
707 | } | |
708 | } | |
a6830278 | 709 | |
64d21fc1 | 710 | static int __init |
ee214558 | 711 | check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) |
a6830278 | 712 | { |
ee214558 YL |
713 | if (!mpc_new_phys || count <= mpc_new_length) { |
714 | WARN(1, "update_mptable: No spare slots (length: %x)\n", count); | |
715 | return -1; | |
a6830278 JSR |
716 | } |
717 | ||
9f1f1bfd | 718 | return 0; |
a6830278 | 719 | } |
cbb84c4c RM |
720 | #else /* CONFIG_X86_IO_APIC */ |
721 | static | |
722 | inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} | |
723 | #endif /* CONFIG_X86_IO_APIC */ | |
2944e16b | 724 | |
f29521e4 | 725 | static int __init replace_intsrc_all(struct mpc_table *mpc, |
2944e16b YL |
726 | unsigned long mpc_new_phys, |
727 | unsigned long mpc_new_length) | |
728 | { | |
729 | #ifdef CONFIG_X86_IO_APIC | |
730 | int i; | |
2944e16b | 731 | #endif |
2944e16b | 732 | int count = sizeof(*mpc); |
a6830278 | 733 | int nr_m_spare = 0; |
2944e16b YL |
734 | unsigned char *mpt = ((unsigned char *)mpc) + count; |
735 | ||
b1bfd5ea | 736 | pr_info("mpc_length %x\n", mpc->length); |
6c65da50 | 737 | while (count < mpc->length) { |
2944e16b YL |
738 | switch (*mpt) { |
739 | case MP_PROCESSOR: | |
a6830278 JSR |
740 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
741 | break; | |
2944e16b | 742 | case MP_BUS: |
a6830278 JSR |
743 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
744 | break; | |
2944e16b | 745 | case MP_IOAPIC: |
a6830278 JSR |
746 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
747 | break; | |
2944e16b | 748 | case MP_INTSRC: |
c58603e8 | 749 | check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare); |
a6830278 JSR |
750 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
751 | break; | |
2944e16b | 752 | case MP_LINTSRC: |
a6830278 JSR |
753 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
754 | break; | |
2944e16b YL |
755 | default: |
756 | /* wrong mptable */ | |
5a5737ea | 757 | smp_dump_mptable(mpc, mpt); |
2944e16b YL |
758 | goto out; |
759 | } | |
760 | } | |
761 | ||
762 | #ifdef CONFIG_X86_IO_APIC | |
763 | for (i = 0; i < mp_irq_entries; i++) { | |
764 | if (irq_used[i]) | |
765 | continue; | |
766 | ||
c2c21745 | 767 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
768 | continue; |
769 | ||
c2c21745 | 770 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
771 | continue; |
772 | ||
773 | if (nr_m_spare > 0) { | |
82034d6f | 774 | apic_printk(APIC_VERBOSE, "*NEW* found\n"); |
2944e16b | 775 | nr_m_spare--; |
0e3fa13f | 776 | memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); |
2944e16b YL |
777 | m_spare[nr_m_spare] = NULL; |
778 | } else { | |
540d4e72 JSR |
779 | struct mpc_intsrc *m = (struct mpc_intsrc *)mpt; |
780 | count += sizeof(struct mpc_intsrc); | |
ee214558 | 781 | if (check_slot(mpc_new_phys, mpc_new_length, count) < 0) |
a6830278 | 782 | goto out; |
0e3fa13f | 783 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
6c65da50 | 784 | mpc->length = count; |
540d4e72 | 785 | mpt += sizeof(struct mpc_intsrc); |
2944e16b YL |
786 | } |
787 | print_mp_irq_info(&mp_irqs[i]); | |
788 | } | |
789 | #endif | |
790 | out: | |
791 | /* update checksum */ | |
6c65da50 JSR |
792 | mpc->checksum = 0; |
793 | mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b YL |
794 | |
795 | return 0; | |
796 | } | |
797 | ||
f1bdb523 | 798 | int enable_update_mptable; |
fcfa146e | 799 | |
2944e16b YL |
800 | static int __init update_mptable_setup(char *str) |
801 | { | |
802 | enable_update_mptable = 1; | |
629e15d2 YL |
803 | #ifdef CONFIG_PCI |
804 | pci_routeirq = 1; | |
805 | #endif | |
2944e16b YL |
806 | return 0; |
807 | } | |
808 | early_param("update_mptable", update_mptable_setup); | |
809 | ||
810 | static unsigned long __initdata mpc_new_phys; | |
811 | static unsigned long mpc_new_length __initdata = 4096; | |
812 | ||
813 | /* alloc_mptable or alloc_mptable=4k */ | |
814 | static int __initdata alloc_mptable; | |
815 | static int __init parse_alloc_mptable_opt(char *p) | |
816 | { | |
817 | enable_update_mptable = 1; | |
629e15d2 YL |
818 | #ifdef CONFIG_PCI |
819 | pci_routeirq = 1; | |
820 | #endif | |
2944e16b YL |
821 | alloc_mptable = 1; |
822 | if (!p) | |
823 | return 0; | |
824 | mpc_new_length = memparse(p, &p); | |
825 | return 0; | |
826 | } | |
827 | early_param("alloc_mptable", parse_alloc_mptable_opt); | |
828 | ||
829 | void __init early_reserve_e820_mpc_new(void) | |
830 | { | |
ab5d140b TH |
831 | if (enable_update_mptable && alloc_mptable) |
832 | mpc_new_phys = early_reserve_e820(mpc_new_length, 4); | |
2944e16b YL |
833 | } |
834 | ||
835 | static int __init update_mp_table(void) | |
836 | { | |
837 | char str[16]; | |
838 | char oem[10]; | |
41401db6 | 839 | struct mpf_intel *mpf; |
f29521e4 | 840 | struct mpc_table *mpc, *mpc_new; |
2944e16b YL |
841 | |
842 | if (!enable_update_mptable) | |
843 | return 0; | |
844 | ||
845 | mpf = mpf_found; | |
846 | if (!mpf) | |
847 | return 0; | |
848 | ||
849 | /* | |
850 | * Now see if we need to go further. | |
851 | */ | |
1eb1b3b6 | 852 | if (mpf->feature1 != 0) |
2944e16b YL |
853 | return 0; |
854 | ||
1eb1b3b6 | 855 | if (!mpf->physptr) |
2944e16b YL |
856 | return 0; |
857 | ||
1eb1b3b6 | 858 | mpc = phys_to_virt(mpf->physptr); |
2944e16b YL |
859 | |
860 | if (!smp_check_mpc(mpc, oem, str)) | |
861 | return 0; | |
862 | ||
b1bfd5ea JL |
863 | pr_info("mpf: %llx\n", (u64)virt_to_phys(mpf)); |
864 | pr_info("physptr: %x\n", mpf->physptr); | |
2944e16b | 865 | |
6c65da50 | 866 | if (mpc_new_phys && mpc->length > mpc_new_length) { |
2944e16b | 867 | mpc_new_phys = 0; |
b1bfd5ea JL |
868 | pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n", |
869 | mpc_new_length); | |
2944e16b YL |
870 | } |
871 | ||
872 | if (!mpc_new_phys) { | |
873 | unsigned char old, new; | |
0d2eb44f | 874 | /* check if we can change the position */ |
6c65da50 JSR |
875 | mpc->checksum = 0; |
876 | old = mpf_checksum((unsigned char *)mpc, mpc->length); | |
877 | mpc->checksum = 0xff; | |
878 | new = mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b | 879 | if (old == new) { |
b1bfd5ea | 880 | pr_info("mpc is readonly, please try alloc_mptable instead\n"); |
2944e16b YL |
881 | return 0; |
882 | } | |
b1bfd5ea | 883 | pr_info("use in-position replacing\n"); |
2944e16b | 884 | } else { |
1eb1b3b6 | 885 | mpf->physptr = mpc_new_phys; |
2944e16b | 886 | mpc_new = phys_to_virt(mpc_new_phys); |
6c65da50 | 887 | memcpy(mpc_new, mpc, mpc->length); |
2944e16b YL |
888 | mpc = mpc_new; |
889 | /* check if we can modify that */ | |
1eb1b3b6 | 890 | if (mpc_new_phys - mpf->physptr) { |
41401db6 | 891 | struct mpf_intel *mpf_new; |
2944e16b | 892 | /* steal 16 bytes from [0, 1k) */ |
b1bfd5ea | 893 | pr_info("mpf new: %x\n", 0x400 - 16); |
2944e16b YL |
894 | mpf_new = phys_to_virt(0x400 - 16); |
895 | memcpy(mpf_new, mpf, 16); | |
896 | mpf = mpf_new; | |
1eb1b3b6 | 897 | mpf->physptr = mpc_new_phys; |
2944e16b | 898 | } |
1eb1b3b6 JSR |
899 | mpf->checksum = 0; |
900 | mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16); | |
b1bfd5ea | 901 | pr_info("physptr new: %x\n", mpf->physptr); |
2944e16b YL |
902 | } |
903 | ||
904 | /* | |
905 | * only replace the one with mp_INT and | |
906 | * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, | |
907 | * already in mp_irqs , stored by ... and mp_config_acpi_gsi, | |
908 | * may need pci=routeirq for all coverage | |
909 | */ | |
910 | replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length); | |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
915 | late_initcall(update_mp_table); |