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Commit | Line | Data |
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1da177e4 | 1 | /* |
11113f84 | 2 | * Intel Multiprocessor Specification 1.1 and 1.4 |
1da177e4 LT |
3 | * compliant MP-table parsing routines. |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
85bdddec | 7 | * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/mm.h> | |
1da177e4 | 11 | #include <linux/init.h> |
1da177e4 | 12 | #include <linux/delay.h> |
1da177e4 | 13 | #include <linux/bootmem.h> |
72d7c3b3 | 14 | #include <linux/memblock.h> |
1da177e4 LT |
15 | #include <linux/kernel_stat.h> |
16 | #include <linux/mc146818rtc.h> | |
17 | #include <linux/bitops.h> | |
85bdddec AS |
18 | #include <linux/acpi.h> |
19 | #include <linux/module.h> | |
103ceffb | 20 | #include <linux/smp.h> |
629e15d2 | 21 | #include <linux/pci.h> |
74501edc | 22 | #include <linux/irqdomain.h> |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <asm/mtrr.h> |
25 | #include <asm/mpspec.h> | |
85bdddec | 26 | #include <asm/pgalloc.h> |
1da177e4 | 27 | #include <asm/io_apic.h> |
85bdddec | 28 | #include <asm/proto.h> |
ce3fe6b2 | 29 | #include <asm/bios_ebda.h> |
2944e16b | 30 | #include <asm/e820.h> |
3c9cb6de | 31 | #include <asm/setup.h> |
4884d8e6 | 32 | #include <asm/smp.h> |
1da177e4 | 33 | |
7b6aa335 | 34 | #include <asm/apic.h> |
1da177e4 LT |
35 | /* |
36 | * Checksum an MP configuration block. | |
37 | */ | |
38 | ||
39 | static int __init mpf_checksum(unsigned char *mp, int len) | |
40 | { | |
41 | int sum = 0; | |
42 | ||
43 | while (len--) | |
44 | sum += *mp++; | |
45 | ||
46 | return sum & 0xFF; | |
47 | } | |
48 | ||
fd6c6661 TG |
49 | int __init default_mpc_apic_id(struct mpc_cpu *m) |
50 | { | |
51 | return m->apicid; | |
52 | } | |
53 | ||
f4f21b71 | 54 | static void __init MP_processor_info(struct mpc_cpu *m) |
c853c676 AS |
55 | { |
56 | int apicid; | |
746f2244 | 57 | char *bootup_cpu = ""; |
c853c676 | 58 | |
c4563826 | 59 | if (!(m->cpuflag & CPU_ENABLED)) { |
7b1292e2 | 60 | disabled_cpus++; |
1da177e4 | 61 | return; |
7b1292e2 | 62 | } |
64898a8b | 63 | |
fd6c6661 | 64 | apicid = x86_init.mpparse.mpc_apic_id(m); |
64898a8b | 65 | |
c4563826 | 66 | if (m->cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 67 | bootup_cpu = " (Bootup-CPU)"; |
c4563826 | 68 | boot_cpu_physical_apicid = m->apicid; |
1da177e4 LT |
69 | } |
70 | ||
b1bfd5ea | 71 | pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); |
c4563826 | 72 | generic_processor_info(apicid, m->apicver); |
1da177e4 LT |
73 | } |
74 | ||
85cc35fa | 75 | #ifdef CONFIG_X86_IO_APIC |
90e1c696 | 76 | void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str) |
1da177e4 | 77 | { |
d4c715fa | 78 | memcpy(str, m->bustype, 6); |
1da177e4 | 79 | str[6] = 0; |
90e1c696 TG |
80 | apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); |
81 | } | |
1da177e4 | 82 | |
90e1c696 TG |
83 | static void __init MP_bus_info(struct mpc_bus *m) |
84 | { | |
85 | char str[7]; | |
1da177e4 | 86 | |
90e1c696 | 87 | x86_init.mpparse.mpc_oem_bus_info(m, str); |
1da177e4 | 88 | |
5e4edbb7 | 89 | #if MAX_MP_BUSSES < 256 |
d4c715fa | 90 | if (m->busid >= MAX_MP_BUSSES) { |
b1bfd5ea JL |
91 | pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n", |
92 | m->busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
93 | return; |
94 | } | |
5e4edbb7 | 95 | #endif |
c0ec31ad | 96 | |
9e686668 | 97 | set_bit(m->busid, mp_bus_not_pci); |
f8924e77 | 98 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
bb8187d3 | 99 | #ifdef CONFIG_EISA |
d4c715fa | 100 | mp_bus_id_to_type[m->busid] = MP_BUS_ISA; |
f8924e77 AS |
101 | #endif |
102 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
52fdb568 TG |
103 | if (x86_init.mpparse.mpc_oem_pci_bus) |
104 | x86_init.mpparse.mpc_oem_pci_bus(m); | |
64898a8b | 105 | |
d4c715fa | 106 | clear_bit(m->busid, mp_bus_not_pci); |
bb8187d3 | 107 | #ifdef CONFIG_EISA |
d4c715fa | 108 | mp_bus_id_to_type[m->busid] = MP_BUS_PCI; |
4ef81297 | 109 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
d4c715fa | 110 | mp_bus_id_to_type[m->busid] = MP_BUS_EISA; |
c0a282c2 | 111 | #endif |
f8924e77 | 112 | } else |
b1bfd5ea | 113 | pr_warn("Unknown bustype %s - ignoring\n", str); |
1da177e4 | 114 | } |
61048c63 | 115 | |
95060639 JL |
116 | static struct irq_domain_ops mp_ioapic_irqdomain_ops = { |
117 | .map = mp_irqdomain_map, | |
c03b3b07 | 118 | .unmap = mp_irqdomain_unmap, |
95060639 | 119 | }; |
74501edc | 120 | |
2b85b5fb | 121 | static void __init MP_ioapic_info(struct mpc_ioapic *m) |
1da177e4 | 122 | { |
74501edc JL |
123 | struct ioapic_domain_cfg cfg = { |
124 | .type = IOAPIC_DOMAIN_LEGACY, | |
125 | .ops = &mp_ioapic_irqdomain_ops, | |
126 | }; | |
127 | ||
0e3fa13f | 128 | if (m->flags & MPC_APIC_USABLE) |
74501edc | 129 | mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg); |
2944e16b YL |
130 | } |
131 | ||
c2c21745 | 132 | static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) |
2944e16b | 133 | { |
b1bfd5ea JL |
134 | apic_printk(APIC_VERBOSE, |
135 | "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
c2c21745 JSR |
136 | mp_irq->irqtype, mp_irq->irqflag & 3, |
137 | (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus, | |
138 | mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); | |
2944e16b YL |
139 | } |
140 | ||
a6830278 JSR |
141 | #else /* CONFIG_X86_IO_APIC */ |
142 | static inline void __init MP_bus_info(struct mpc_bus *m) {} | |
143 | static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {} | |
a6830278 | 144 | #endif /* CONFIG_X86_IO_APIC */ |
1da177e4 | 145 | |
8fb2952b | 146 | static void __init MP_lintsrc_info(struct mpc_lintsrc *m) |
1da177e4 | 147 | { |
b1bfd5ea JL |
148 | apic_printk(APIC_VERBOSE, |
149 | "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
b5ced7cd JSR |
150 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid, |
151 | m->srcbusirq, m->destapic, m->destapiclint); | |
1da177e4 LT |
152 | } |
153 | ||
1da177e4 LT |
154 | /* |
155 | * Read/parse the MPC | |
156 | */ | |
f29521e4 | 157 | static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str) |
1da177e4 | 158 | { |
1da177e4 | 159 | |
6c65da50 | 160 | if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) { |
b1bfd5ea | 161 | pr_err("MPTABLE: bad signature [%c%c%c%c]!\n", |
6c65da50 JSR |
162 | mpc->signature[0], mpc->signature[1], |
163 | mpc->signature[2], mpc->signature[3]); | |
1da177e4 LT |
164 | return 0; |
165 | } | |
6c65da50 | 166 | if (mpf_checksum((unsigned char *)mpc, mpc->length)) { |
b1bfd5ea | 167 | pr_err("MPTABLE: checksum error!\n"); |
1da177e4 LT |
168 | return 0; |
169 | } | |
6c65da50 | 170 | if (mpc->spec != 0x01 && mpc->spec != 0x04) { |
b1bfd5ea | 171 | pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec); |
1da177e4 LT |
172 | return 0; |
173 | } | |
6c65da50 | 174 | if (!mpc->lapic) { |
b1bfd5ea | 175 | pr_err("MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
176 | return 0; |
177 | } | |
6c65da50 | 178 | memcpy(oem, mpc->oem, 8); |
4ef81297 | 179 | oem[8] = 0; |
b1bfd5ea | 180 | pr_info("MPTABLE: OEM ID: %s\n", oem); |
1da177e4 | 181 | |
6c65da50 | 182 | memcpy(str, mpc->productid, 12); |
4ef81297 | 183 | str[12] = 0; |
1da177e4 | 184 | |
b1bfd5ea | 185 | pr_info("MPTABLE: Product ID: %s\n", str); |
1da177e4 | 186 | |
b1bfd5ea | 187 | pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic); |
1da177e4 | 188 | |
2944e16b YL |
189 | return 1; |
190 | } | |
191 | ||
a6830278 JSR |
192 | static void skip_entry(unsigned char **ptr, int *count, int size) |
193 | { | |
194 | *ptr += size; | |
195 | *count += size; | |
196 | } | |
197 | ||
5a5737ea JSR |
198 | static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) |
199 | { | |
b1bfd5ea JL |
200 | pr_err("Your mptable is wrong, contact your HW vendor!\n"); |
201 | pr_cont("type %x\n", *mpt); | |
5a5737ea JSR |
202 | print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, |
203 | 1, mpc, mpc->length, 1); | |
204 | } | |
205 | ||
72302142 TG |
206 | void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } |
207 | ||
f29521e4 | 208 | static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) |
2944e16b YL |
209 | { |
210 | char str[16]; | |
211 | char oem[10]; | |
212 | ||
213 | int count = sizeof(*mpc); | |
214 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
215 | ||
216 | if (!smp_check_mpc(mpc, oem, str)) | |
217 | return 0; | |
218 | ||
f1157141 | 219 | /* Initialize the lapic mapping */ |
1da177e4 | 220 | if (!acpi_lapic) |
f1157141 | 221 | register_lapic_address(mpc->lapic); |
1da177e4 | 222 | |
888032cd AS |
223 | if (early) |
224 | return 1; | |
225 | ||
72302142 TG |
226 | if (mpc->oemptr) |
227 | x86_init.mpparse.smp_read_mpc_oem(mpc); | |
64898a8b | 228 | |
1da177e4 | 229 | /* |
4ef81297 | 230 | * Now process the configuration blocks. |
1da177e4 | 231 | */ |
f4848472 | 232 | x86_init.mpparse.mpc_record(0); |
64898a8b | 233 | |
6c65da50 | 234 | while (count < mpc->length) { |
4ef81297 AS |
235 | switch (*mpt) { |
236 | case MP_PROCESSOR: | |
a6830278 JSR |
237 | /* ACPI may have already provided this data */ |
238 | if (!acpi_lapic) | |
c58603e8 | 239 | MP_processor_info((struct mpc_cpu *)mpt); |
a6830278 JSR |
240 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
241 | break; | |
4ef81297 | 242 | case MP_BUS: |
c58603e8 | 243 | MP_bus_info((struct mpc_bus *)mpt); |
a6830278 JSR |
244 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
245 | break; | |
4ef81297 | 246 | case MP_IOAPIC: |
c58603e8 | 247 | MP_ioapic_info((struct mpc_ioapic *)mpt); |
a6830278 JSR |
248 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
249 | break; | |
4ef81297 | 250 | case MP_INTSRC: |
2d8009ba | 251 | mp_save_irq((struct mpc_intsrc *)mpt); |
a6830278 JSR |
252 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
253 | break; | |
4ef81297 | 254 | case MP_LINTSRC: |
c58603e8 | 255 | MP_lintsrc_info((struct mpc_lintsrc *)mpt); |
a6830278 JSR |
256 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
257 | break; | |
4ef81297 | 258 | default: |
711554db | 259 | /* wrong mptable */ |
5a5737ea | 260 | smp_dump_mptable(mpc, mpt); |
6c65da50 | 261 | count = mpc->length; |
711554db | 262 | break; |
1da177e4 | 263 | } |
f4848472 | 264 | x86_init.mpparse.mpc_record(1); |
1da177e4 | 265 | } |
e0da3364 | 266 | |
1da177e4 | 267 | if (!num_processors) |
b1bfd5ea | 268 | pr_err("MPTABLE: no processors registered!\n"); |
1da177e4 LT |
269 | return num_processors; |
270 | } | |
271 | ||
61048c63 AS |
272 | #ifdef CONFIG_X86_IO_APIC |
273 | ||
1da177e4 LT |
274 | static int __init ELCR_trigger(unsigned int irq) |
275 | { | |
276 | unsigned int port; | |
277 | ||
278 | port = 0x4d0 + (irq >> 3); | |
279 | return (inb(port) >> (irq & 7)) & 1; | |
280 | } | |
281 | ||
282 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
283 | { | |
540d4e72 | 284 | struct mpc_intsrc intsrc; |
1da177e4 LT |
285 | int i; |
286 | int ELCR_fallback = 0; | |
287 | ||
e253b396 JSR |
288 | intsrc.type = MP_INTSRC; |
289 | intsrc.irqflag = 0; /* conforming */ | |
290 | intsrc.srcbus = 0; | |
d5371430 | 291 | intsrc.dstapic = mpc_ioapic_id(0); |
1da177e4 | 292 | |
e253b396 | 293 | intsrc.irqtype = mp_INT; |
1da177e4 LT |
294 | |
295 | /* | |
296 | * If true, we have an ISA/PCI system with no IRQ entries | |
297 | * in the MP table. To prevent the PCI interrupts from being set up | |
298 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
299 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
300 | * never be level sensitive, so we simply see if the ELCR agrees. | |
301 | * If it does, we assume it's valid. | |
302 | */ | |
303 | if (mpc_default_type == 5) { | |
b1bfd5ea | 304 | pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); |
1da177e4 | 305 | |
62441bf1 AS |
306 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
307 | ELCR_trigger(13)) | |
b1bfd5ea | 308 | pr_err("ELCR contains invalid data... not using ELCR\n"); |
1da177e4 | 309 | else { |
b1bfd5ea | 310 | pr_info("Using ELCR to identify PCI interrupts\n"); |
1da177e4 LT |
311 | ELCR_fallback = 1; |
312 | } | |
313 | } | |
314 | ||
315 | for (i = 0; i < 16; i++) { | |
316 | switch (mpc_default_type) { | |
317 | case 2: | |
318 | if (i == 0 || i == 13) | |
319 | continue; /* IRQ0 & IRQ13 not connected */ | |
320 | /* fall through */ | |
321 | default: | |
322 | if (i == 2) | |
323 | continue; /* IRQ2 is never connected */ | |
324 | } | |
325 | ||
326 | if (ELCR_fallback) { | |
327 | /* | |
328 | * If the ELCR indicates a level-sensitive interrupt, we | |
329 | * copy that information over to the MP table in the | |
330 | * irqflag field (level sensitive, active high polarity). | |
331 | */ | |
332 | if (ELCR_trigger(i)) | |
e253b396 | 333 | intsrc.irqflag = 13; |
1da177e4 | 334 | else |
e253b396 | 335 | intsrc.irqflag = 0; |
1da177e4 LT |
336 | } |
337 | ||
e253b396 JSR |
338 | intsrc.srcbusirq = i; |
339 | intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
2d8009ba | 340 | mp_save_irq(&intsrc); |
1da177e4 LT |
341 | } |
342 | ||
e253b396 JSR |
343 | intsrc.irqtype = mp_ExtINT; |
344 | intsrc.srcbusirq = 0; | |
345 | intsrc.dstirq = 0; /* 8259A to INTIN0 */ | |
2d8009ba | 346 | mp_save_irq(&intsrc); |
1da177e4 LT |
347 | } |
348 | ||
61048c63 | 349 | |
39e00fe2 | 350 | static void __init construct_ioapic_table(int mpc_default_type) |
1da177e4 | 351 | { |
2b85b5fb | 352 | struct mpc_ioapic ioapic; |
00fb8606 | 353 | struct mpc_bus bus; |
1da177e4 | 354 | |
d4c715fa JSR |
355 | bus.type = MP_BUS; |
356 | bus.busid = 0; | |
1da177e4 | 357 | switch (mpc_default_type) { |
4ef81297 | 358 | default: |
b1bfd5ea | 359 | pr_err("???\nUnknown standard configuration %d\n", |
4ef81297 AS |
360 | mpc_default_type); |
361 | /* fall through */ | |
362 | case 1: | |
363 | case 5: | |
d4c715fa | 364 | memcpy(bus.bustype, "ISA ", 6); |
4ef81297 AS |
365 | break; |
366 | case 2: | |
367 | case 6: | |
368 | case 3: | |
d4c715fa | 369 | memcpy(bus.bustype, "EISA ", 6); |
4ef81297 | 370 | break; |
1da177e4 LT |
371 | } |
372 | MP_bus_info(&bus); | |
373 | if (mpc_default_type > 4) { | |
d4c715fa JSR |
374 | bus.busid = 1; |
375 | memcpy(bus.bustype, "PCI ", 6); | |
1da177e4 LT |
376 | MP_bus_info(&bus); |
377 | } | |
378 | ||
8f3e1df4 CG |
379 | ioapic.type = MP_IOAPIC; |
380 | ioapic.apicid = 2; | |
381 | ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
382 | ioapic.flags = MPC_APIC_USABLE; | |
383 | ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
384 | MP_ioapic_info(&ioapic); |
385 | ||
386 | /* | |
387 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
388 | */ | |
389 | construct_default_ioirq_mptable(mpc_default_type); | |
85cc35fa TG |
390 | } |
391 | #else | |
39e00fe2 | 392 | static inline void __init construct_ioapic_table(int mpc_default_type) { } |
61048c63 | 393 | #endif |
85cc35fa TG |
394 | |
395 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
396 | { | |
f4f21b71 | 397 | struct mpc_cpu processor; |
8fb2952b | 398 | struct mpc_lintsrc lintsrc; |
85cc35fa TG |
399 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
400 | int i; | |
401 | ||
402 | /* | |
403 | * local APIC has default address | |
404 | */ | |
405 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
406 | ||
407 | /* | |
408 | * 2 CPUs, numbered 0 & 1. | |
409 | */ | |
c4563826 | 410 | processor.type = MP_PROCESSOR; |
85cc35fa | 411 | /* Either an integrated APIC or a discrete 82489DX. */ |
c4563826 JSR |
412 | processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
413 | processor.cpuflag = CPU_ENABLED; | |
414 | processor.cpufeature = (boot_cpu_data.x86 << 8) | | |
85cc35fa | 415 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
c4563826 JSR |
416 | processor.featureflag = boot_cpu_data.x86_capability[0]; |
417 | processor.reserved[0] = 0; | |
418 | processor.reserved[1] = 0; | |
85cc35fa | 419 | for (i = 0; i < 2; i++) { |
c4563826 | 420 | processor.apicid = i; |
85cc35fa TG |
421 | MP_processor_info(&processor); |
422 | } | |
423 | ||
424 | construct_ioapic_table(mpc_default_type); | |
425 | ||
b5ced7cd JSR |
426 | lintsrc.type = MP_LINTSRC; |
427 | lintsrc.irqflag = 0; /* conforming */ | |
428 | lintsrc.srcbusid = 0; | |
429 | lintsrc.srcbusirq = 0; | |
430 | lintsrc.destapic = MP_APIC_ALL; | |
1da177e4 | 431 | for (i = 0; i < 2; i++) { |
b5ced7cd JSR |
432 | lintsrc.irqtype = linttypes[i]; |
433 | lintsrc.destapiclint = i; | |
1da177e4 LT |
434 | MP_lintsrc_info(&lintsrc); |
435 | } | |
436 | } | |
437 | ||
41401db6 | 438 | static struct mpf_intel *mpf_found; |
1da177e4 | 439 | |
8d4dd919 YL |
440 | static unsigned long __init get_mpc_size(unsigned long physptr) |
441 | { | |
442 | struct mpc_table *mpc; | |
443 | unsigned long size; | |
444 | ||
445 | mpc = early_ioremap(physptr, PAGE_SIZE); | |
446 | size = mpc->length; | |
447 | early_iounmap(mpc, PAGE_SIZE); | |
448 | apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); | |
449 | ||
450 | return size; | |
451 | } | |
452 | ||
0b3ba0c3 JSR |
453 | static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) |
454 | { | |
455 | struct mpc_table *mpc; | |
456 | unsigned long size; | |
457 | ||
458 | size = get_mpc_size(mpf->physptr); | |
459 | mpc = early_ioremap(mpf->physptr, size); | |
460 | /* | |
461 | * Read the physical hardware table. Anything here will | |
462 | * override the defaults. | |
463 | */ | |
464 | if (!smp_read_mpc(mpc, early)) { | |
465 | #ifdef CONFIG_X86_LOCAL_APIC | |
466 | smp_found_config = 0; | |
467 | #endif | |
b1bfd5ea JL |
468 | pr_err("BIOS bug, MP table errors detected!...\n"); |
469 | pr_cont("... disabling SMP support. (tell your hw vendor)\n"); | |
0b3ba0c3 JSR |
470 | early_iounmap(mpc, size); |
471 | return -1; | |
472 | } | |
473 | early_iounmap(mpc, size); | |
474 | ||
475 | if (early) | |
476 | return -1; | |
477 | ||
478 | #ifdef CONFIG_X86_IO_APIC | |
479 | /* | |
480 | * If there are no explicit MP IRQ entries, then we are | |
481 | * broken. We set up most of the low 16 IO-APIC pins to | |
482 | * ISA defaults and hope it will work. | |
483 | */ | |
484 | if (!mp_irq_entries) { | |
485 | struct mpc_bus bus; | |
486 | ||
b1bfd5ea | 487 | pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); |
0b3ba0c3 JSR |
488 | |
489 | bus.type = MP_BUS; | |
490 | bus.busid = 0; | |
491 | memcpy(bus.bustype, "ISA ", 6); | |
492 | MP_bus_info(&bus); | |
493 | ||
494 | construct_default_ioirq_mptable(0); | |
495 | } | |
496 | #endif | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
1da177e4 LT |
501 | /* |
502 | * Scan the memory blocks for an SMP configuration block. | |
503 | */ | |
b3f1b617 | 504 | void __init default_get_smp_config(unsigned int early) |
1da177e4 | 505 | { |
41401db6 | 506 | struct mpf_intel *mpf = mpf_found; |
1da177e4 | 507 | |
69b88afa YL |
508 | if (!mpf) |
509 | return; | |
510 | ||
888032cd AS |
511 | if (acpi_lapic && early) |
512 | return; | |
69b88afa | 513 | |
1da177e4 | 514 | /* |
69b88afa YL |
515 | * MPS doesn't support hyperthreading, aka only have |
516 | * thread 0 apic id in MPS table | |
1da177e4 | 517 | */ |
69b88afa | 518 | if (acpi_lapic && acpi_ioapic) |
1da177e4 | 519 | return; |
1da177e4 | 520 | |
b1bfd5ea JL |
521 | pr_info("Intel MultiProcessor Specification v1.%d\n", |
522 | mpf->specification); | |
b3e24164 | 523 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
1eb1b3b6 | 524 | if (mpf->feature2 & (1 << 7)) { |
b1bfd5ea | 525 | pr_info(" IMCR and PIC compatibility mode.\n"); |
1da177e4 LT |
526 | pic_mode = 1; |
527 | } else { | |
b1bfd5ea | 528 | pr_info(" Virtual Wire compatibility mode.\n"); |
1da177e4 LT |
529 | pic_mode = 0; |
530 | } | |
4421b1c8 | 531 | #endif |
1da177e4 LT |
532 | /* |
533 | * Now see if we need to read further. | |
534 | */ | |
1eb1b3b6 | 535 | if (mpf->feature1 != 0) { |
888032cd AS |
536 | if (early) { |
537 | /* | |
538 | * local APIC has default address | |
539 | */ | |
540 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
541 | return; | |
542 | } | |
1da177e4 | 543 | |
b1bfd5ea | 544 | pr_info("Default MP configuration #%d\n", mpf->feature1); |
1eb1b3b6 | 545 | construct_default_ISA_mptable(mpf->feature1); |
1da177e4 | 546 | |
1eb1b3b6 | 547 | } else if (mpf->physptr) { |
0b3ba0c3 | 548 | if (check_physptr(mpf, early)) |
1da177e4 | 549 | return; |
1da177e4 LT |
550 | } else |
551 | BUG(); | |
552 | ||
888032cd | 553 | if (!early) |
b1bfd5ea | 554 | pr_info("Processors: %d\n", num_processors); |
1da177e4 LT |
555 | /* |
556 | * Only use the first configuration found. | |
557 | */ | |
558 | } | |
559 | ||
b24c2a92 | 560 | static void __init smp_reserve_memory(struct mpf_intel *mpf) |
a6830278 | 561 | { |
24aa0788 | 562 | memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); |
a6830278 JSR |
563 | } |
564 | ||
b24c2a92 | 565 | static int __init smp_scan_config(unsigned long base, unsigned long length) |
1da177e4 | 566 | { |
92fd4b7a | 567 | unsigned int *bp = phys_to_virt(base); |
41401db6 | 568 | struct mpf_intel *mpf; |
b24c2a92 | 569 | unsigned long mem; |
1da177e4 | 570 | |
365811d6 BH |
571 | apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", |
572 | base, base + length - 1); | |
5d47a271 | 573 | BUILD_BUG_ON(sizeof(*mpf) != 16); |
1da177e4 LT |
574 | |
575 | while (length > 0) { | |
41401db6 | 576 | mpf = (struct mpf_intel *)bp; |
1da177e4 | 577 | if ((*bp == SMP_MAGIC_IDENT) && |
1eb1b3b6 | 578 | (mpf->length == 1) && |
4ef81297 | 579 | !mpf_checksum((unsigned char *)bp, 16) && |
1eb1b3b6 JSR |
580 | ((mpf->specification == 1) |
581 | || (mpf->specification == 4))) { | |
bab4b27c | 582 | #ifdef CONFIG_X86_LOCAL_APIC |
1da177e4 | 583 | smp_found_config = 1; |
bab4b27c | 584 | #endif |
92fd4b7a | 585 | mpf_found = mpf; |
b1f006b6 | 586 | |
b1bfd5ea JL |
587 | pr_info("found SMP MP-table at [mem %#010llx-%#010llx] mapped at [%p]\n", |
588 | (unsigned long long) virt_to_phys(mpf), | |
589 | (unsigned long long) virt_to_phys(mpf) + | |
590 | sizeof(*mpf) - 1, mpf); | |
b1f006b6 | 591 | |
b24c2a92 | 592 | mem = virt_to_phys(mpf); |
24aa0788 | 593 | memblock_reserve(mem, sizeof(*mpf)); |
a6830278 | 594 | if (mpf->physptr) |
b24c2a92 | 595 | smp_reserve_memory(mpf); |
1da177e4 | 596 | |
d2dbf343 | 597 | return 1; |
1da177e4 LT |
598 | } |
599 | bp += 4; | |
600 | length -= 16; | |
601 | } | |
602 | return 0; | |
603 | } | |
604 | ||
b24c2a92 | 605 | void __init default_find_smp_config(void) |
1da177e4 LT |
606 | { |
607 | unsigned int address; | |
608 | ||
609 | /* | |
610 | * FIXME: Linux assumes you have 640K of base ram.. | |
611 | * this continues the error... | |
612 | * | |
613 | * 1) Scan the bottom 1K for a signature | |
614 | * 2) Scan the top 1K of base RAM | |
615 | * 3) Scan the 64K of bios | |
616 | */ | |
b24c2a92 YL |
617 | if (smp_scan_config(0x0, 0x400) || |
618 | smp_scan_config(639 * 0x400, 0x400) || | |
619 | smp_scan_config(0xF0000, 0x10000)) | |
1da177e4 LT |
620 | return; |
621 | /* | |
622 | * If it is an SMP machine we should know now, unless the | |
bb8187d3 | 623 | * configuration is in an EISA bus machine with an |
1da177e4 LT |
624 | * extended bios data area. |
625 | * | |
626 | * there is a real-mode segmented pointer pointing to the | |
627 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
628 | * | |
629 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
630 | * area, and as such this kind of SMP config may be less | |
631 | * trustworthy, simply because the SMP table may have been | |
632 | * stomped on during early boot. These loaders are buggy and | |
633 | * should be fixed. | |
634 | * | |
635 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
636 | */ | |
637 | ||
638 | address = get_bios_ebda(); | |
639 | if (address) | |
b24c2a92 | 640 | smp_scan_config(address, 0x400); |
888032cd AS |
641 | } |
642 | ||
2944e16b YL |
643 | #ifdef CONFIG_X86_IO_APIC |
644 | static u8 __initdata irq_used[MAX_IRQ_SOURCES]; | |
645 | ||
540d4e72 | 646 | static int __init get_MP_intsrc_index(struct mpc_intsrc *m) |
2944e16b YL |
647 | { |
648 | int i; | |
649 | ||
e253b396 | 650 | if (m->irqtype != mp_INT) |
2944e16b YL |
651 | return 0; |
652 | ||
e253b396 | 653 | if (m->irqflag != 0x0f) |
2944e16b YL |
654 | return 0; |
655 | ||
656 | /* not legacy */ | |
657 | ||
658 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 659 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
660 | continue; |
661 | ||
c2c21745 | 662 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
663 | continue; |
664 | ||
c2c21745 | 665 | if (mp_irqs[i].srcbus != m->srcbus) |
2944e16b | 666 | continue; |
c2c21745 | 667 | if (mp_irqs[i].srcbusirq != m->srcbusirq) |
2944e16b YL |
668 | continue; |
669 | if (irq_used[i]) { | |
670 | /* already claimed */ | |
671 | return -2; | |
672 | } | |
673 | irq_used[i] = 1; | |
674 | return i; | |
675 | } | |
676 | ||
677 | /* not found */ | |
678 | return -1; | |
679 | } | |
680 | ||
681 | #define SPARE_SLOT_NUM 20 | |
682 | ||
540d4e72 | 683 | static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM]; |
a6830278 | 684 | |
57592224 | 685 | static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) |
a6830278 JSR |
686 | { |
687 | int i; | |
688 | ||
689 | apic_printk(APIC_VERBOSE, "OLD "); | |
0e3fa13f | 690 | print_mp_irq_info(m); |
a6830278 JSR |
691 | |
692 | i = get_MP_intsrc_index(m); | |
693 | if (i > 0) { | |
0e3fa13f | 694 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
a6830278 JSR |
695 | apic_printk(APIC_VERBOSE, "NEW "); |
696 | print_mp_irq_info(&mp_irqs[i]); | |
697 | return; | |
698 | } | |
699 | if (!i) { | |
700 | /* legacy, do nothing */ | |
701 | return; | |
702 | } | |
703 | if (*nr_m_spare < SPARE_SLOT_NUM) { | |
704 | /* | |
705 | * not found (-1), or duplicated (-2) are invalid entries, | |
706 | * we need to use the slot later | |
707 | */ | |
708 | m_spare[*nr_m_spare] = m; | |
709 | *nr_m_spare += 1; | |
710 | } | |
711 | } | |
a6830278 | 712 | |
64d21fc1 | 713 | static int __init |
ee214558 | 714 | check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) |
a6830278 | 715 | { |
ee214558 YL |
716 | if (!mpc_new_phys || count <= mpc_new_length) { |
717 | WARN(1, "update_mptable: No spare slots (length: %x)\n", count); | |
718 | return -1; | |
a6830278 JSR |
719 | } |
720 | ||
9f1f1bfd | 721 | return 0; |
a6830278 | 722 | } |
cbb84c4c RM |
723 | #else /* CONFIG_X86_IO_APIC */ |
724 | static | |
725 | inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} | |
726 | #endif /* CONFIG_X86_IO_APIC */ | |
2944e16b | 727 | |
f29521e4 | 728 | static int __init replace_intsrc_all(struct mpc_table *mpc, |
2944e16b YL |
729 | unsigned long mpc_new_phys, |
730 | unsigned long mpc_new_length) | |
731 | { | |
732 | #ifdef CONFIG_X86_IO_APIC | |
733 | int i; | |
2944e16b | 734 | #endif |
2944e16b | 735 | int count = sizeof(*mpc); |
a6830278 | 736 | int nr_m_spare = 0; |
2944e16b YL |
737 | unsigned char *mpt = ((unsigned char *)mpc) + count; |
738 | ||
b1bfd5ea | 739 | pr_info("mpc_length %x\n", mpc->length); |
6c65da50 | 740 | while (count < mpc->length) { |
2944e16b YL |
741 | switch (*mpt) { |
742 | case MP_PROCESSOR: | |
a6830278 JSR |
743 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
744 | break; | |
2944e16b | 745 | case MP_BUS: |
a6830278 JSR |
746 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
747 | break; | |
2944e16b | 748 | case MP_IOAPIC: |
a6830278 JSR |
749 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
750 | break; | |
2944e16b | 751 | case MP_INTSRC: |
c58603e8 | 752 | check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare); |
a6830278 JSR |
753 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
754 | break; | |
2944e16b | 755 | case MP_LINTSRC: |
a6830278 JSR |
756 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
757 | break; | |
2944e16b YL |
758 | default: |
759 | /* wrong mptable */ | |
5a5737ea | 760 | smp_dump_mptable(mpc, mpt); |
2944e16b YL |
761 | goto out; |
762 | } | |
763 | } | |
764 | ||
765 | #ifdef CONFIG_X86_IO_APIC | |
766 | for (i = 0; i < mp_irq_entries; i++) { | |
767 | if (irq_used[i]) | |
768 | continue; | |
769 | ||
c2c21745 | 770 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
771 | continue; |
772 | ||
c2c21745 | 773 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
774 | continue; |
775 | ||
776 | if (nr_m_spare > 0) { | |
82034d6f | 777 | apic_printk(APIC_VERBOSE, "*NEW* found\n"); |
2944e16b | 778 | nr_m_spare--; |
0e3fa13f | 779 | memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); |
2944e16b YL |
780 | m_spare[nr_m_spare] = NULL; |
781 | } else { | |
540d4e72 JSR |
782 | struct mpc_intsrc *m = (struct mpc_intsrc *)mpt; |
783 | count += sizeof(struct mpc_intsrc); | |
ee214558 | 784 | if (check_slot(mpc_new_phys, mpc_new_length, count) < 0) |
a6830278 | 785 | goto out; |
0e3fa13f | 786 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
6c65da50 | 787 | mpc->length = count; |
540d4e72 | 788 | mpt += sizeof(struct mpc_intsrc); |
2944e16b YL |
789 | } |
790 | print_mp_irq_info(&mp_irqs[i]); | |
791 | } | |
792 | #endif | |
793 | out: | |
794 | /* update checksum */ | |
6c65da50 JSR |
795 | mpc->checksum = 0; |
796 | mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b YL |
797 | |
798 | return 0; | |
799 | } | |
800 | ||
f1bdb523 | 801 | int enable_update_mptable; |
fcfa146e | 802 | |
2944e16b YL |
803 | static int __init update_mptable_setup(char *str) |
804 | { | |
805 | enable_update_mptable = 1; | |
629e15d2 YL |
806 | #ifdef CONFIG_PCI |
807 | pci_routeirq = 1; | |
808 | #endif | |
2944e16b YL |
809 | return 0; |
810 | } | |
811 | early_param("update_mptable", update_mptable_setup); | |
812 | ||
813 | static unsigned long __initdata mpc_new_phys; | |
814 | static unsigned long mpc_new_length __initdata = 4096; | |
815 | ||
816 | /* alloc_mptable or alloc_mptable=4k */ | |
817 | static int __initdata alloc_mptable; | |
818 | static int __init parse_alloc_mptable_opt(char *p) | |
819 | { | |
820 | enable_update_mptable = 1; | |
629e15d2 YL |
821 | #ifdef CONFIG_PCI |
822 | pci_routeirq = 1; | |
823 | #endif | |
2944e16b YL |
824 | alloc_mptable = 1; |
825 | if (!p) | |
826 | return 0; | |
827 | mpc_new_length = memparse(p, &p); | |
828 | return 0; | |
829 | } | |
830 | early_param("alloc_mptable", parse_alloc_mptable_opt); | |
831 | ||
832 | void __init early_reserve_e820_mpc_new(void) | |
833 | { | |
ab5d140b TH |
834 | if (enable_update_mptable && alloc_mptable) |
835 | mpc_new_phys = early_reserve_e820(mpc_new_length, 4); | |
2944e16b YL |
836 | } |
837 | ||
838 | static int __init update_mp_table(void) | |
839 | { | |
840 | char str[16]; | |
841 | char oem[10]; | |
41401db6 | 842 | struct mpf_intel *mpf; |
f29521e4 | 843 | struct mpc_table *mpc, *mpc_new; |
2944e16b YL |
844 | |
845 | if (!enable_update_mptable) | |
846 | return 0; | |
847 | ||
848 | mpf = mpf_found; | |
849 | if (!mpf) | |
850 | return 0; | |
851 | ||
852 | /* | |
853 | * Now see if we need to go further. | |
854 | */ | |
1eb1b3b6 | 855 | if (mpf->feature1 != 0) |
2944e16b YL |
856 | return 0; |
857 | ||
1eb1b3b6 | 858 | if (!mpf->physptr) |
2944e16b YL |
859 | return 0; |
860 | ||
1eb1b3b6 | 861 | mpc = phys_to_virt(mpf->physptr); |
2944e16b YL |
862 | |
863 | if (!smp_check_mpc(mpc, oem, str)) | |
864 | return 0; | |
865 | ||
b1bfd5ea JL |
866 | pr_info("mpf: %llx\n", (u64)virt_to_phys(mpf)); |
867 | pr_info("physptr: %x\n", mpf->physptr); | |
2944e16b | 868 | |
6c65da50 | 869 | if (mpc_new_phys && mpc->length > mpc_new_length) { |
2944e16b | 870 | mpc_new_phys = 0; |
b1bfd5ea JL |
871 | pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n", |
872 | mpc_new_length); | |
2944e16b YL |
873 | } |
874 | ||
875 | if (!mpc_new_phys) { | |
876 | unsigned char old, new; | |
0d2eb44f | 877 | /* check if we can change the position */ |
6c65da50 JSR |
878 | mpc->checksum = 0; |
879 | old = mpf_checksum((unsigned char *)mpc, mpc->length); | |
880 | mpc->checksum = 0xff; | |
881 | new = mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b | 882 | if (old == new) { |
b1bfd5ea | 883 | pr_info("mpc is readonly, please try alloc_mptable instead\n"); |
2944e16b YL |
884 | return 0; |
885 | } | |
b1bfd5ea | 886 | pr_info("use in-position replacing\n"); |
2944e16b | 887 | } else { |
1eb1b3b6 | 888 | mpf->physptr = mpc_new_phys; |
2944e16b | 889 | mpc_new = phys_to_virt(mpc_new_phys); |
6c65da50 | 890 | memcpy(mpc_new, mpc, mpc->length); |
2944e16b YL |
891 | mpc = mpc_new; |
892 | /* check if we can modify that */ | |
1eb1b3b6 | 893 | if (mpc_new_phys - mpf->physptr) { |
41401db6 | 894 | struct mpf_intel *mpf_new; |
2944e16b | 895 | /* steal 16 bytes from [0, 1k) */ |
b1bfd5ea | 896 | pr_info("mpf new: %x\n", 0x400 - 16); |
2944e16b YL |
897 | mpf_new = phys_to_virt(0x400 - 16); |
898 | memcpy(mpf_new, mpf, 16); | |
899 | mpf = mpf_new; | |
1eb1b3b6 | 900 | mpf->physptr = mpc_new_phys; |
2944e16b | 901 | } |
1eb1b3b6 JSR |
902 | mpf->checksum = 0; |
903 | mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16); | |
b1bfd5ea | 904 | pr_info("physptr new: %x\n", mpf->physptr); |
2944e16b YL |
905 | } |
906 | ||
907 | /* | |
908 | * only replace the one with mp_INT and | |
909 | * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, | |
910 | * already in mp_irqs , stored by ... and mp_config_acpi_gsi, | |
911 | * may need pci=routeirq for all coverage | |
912 | */ | |
913 | replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length); | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | late_initcall(update_mp_table); |