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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
85bdddec | 7 | * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/mm.h> | |
1da177e4 | 11 | #include <linux/init.h> |
1da177e4 | 12 | #include <linux/delay.h> |
1da177e4 | 13 | #include <linux/bootmem.h> |
1da177e4 LT |
14 | #include <linux/kernel_stat.h> |
15 | #include <linux/mc146818rtc.h> | |
16 | #include <linux/bitops.h> | |
85bdddec AS |
17 | #include <linux/acpi.h> |
18 | #include <linux/module.h> | |
1da177e4 LT |
19 | |
20 | #include <asm/smp.h> | |
1da177e4 LT |
21 | #include <asm/mtrr.h> |
22 | #include <asm/mpspec.h> | |
85bdddec | 23 | #include <asm/pgalloc.h> |
1da177e4 | 24 | #include <asm/io_apic.h> |
85bdddec AS |
25 | #include <asm/proto.h> |
26 | #include <asm/acpi.h> | |
ce3fe6b2 | 27 | #include <asm/bios_ebda.h> |
1da177e4 LT |
28 | |
29 | #include <mach_apic.h> | |
85bdddec | 30 | #ifdef CONFIG_X86_32 |
874c4fe3 | 31 | #include <mach_apicdef.h> |
1da177e4 | 32 | #include <mach_mpparse.h> |
85bdddec | 33 | #endif |
1da177e4 LT |
34 | |
35 | /* Have we found an MP table */ | |
36 | int smp_found_config; | |
1da177e4 LT |
37 | |
38 | /* | |
39 | * Various Linux-internal data structures created from the | |
40 | * MP-table. | |
41 | */ | |
c0a282c2 | 42 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
4ef81297 | 43 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
c0a282c2 | 44 | #endif |
85bdddec | 45 | |
a6333c3c | 46 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
4ef81297 | 47 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
85bdddec | 48 | |
1da177e4 LT |
49 | static int mp_current_pci_id; |
50 | ||
1da177e4 | 51 | int pic_mode; |
1da177e4 | 52 | |
1da177e4 LT |
53 | /* |
54 | * Intel MP BIOS table parsing routines: | |
55 | */ | |
56 | ||
1da177e4 LT |
57 | /* |
58 | * Checksum an MP configuration block. | |
59 | */ | |
60 | ||
61 | static int __init mpf_checksum(unsigned char *mp, int len) | |
62 | { | |
63 | int sum = 0; | |
64 | ||
65 | while (len--) | |
66 | sum += *mp++; | |
67 | ||
68 | return sum & 0xFF; | |
69 | } | |
70 | ||
86420506 | 71 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 LT |
72 | /* |
73 | * Have to match translation table entries to main table entries by counter | |
74 | * hence the mpc_record variable .... can't see a less disgusting way of | |
75 | * doing this .... | |
76 | */ | |
77 | ||
4ef81297 AS |
78 | static int mpc_record; |
79 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] | |
80 | __cpuinitdata; | |
86420506 | 81 | #endif |
1da177e4 | 82 | |
c853c676 AS |
83 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
84 | { | |
85 | int apicid; | |
746f2244 | 86 | char *bootup_cpu = ""; |
c853c676 | 87 | |
7b1292e2 GC |
88 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
89 | disabled_cpus++; | |
1da177e4 | 90 | return; |
7b1292e2 | 91 | } |
4655c7de | 92 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 93 | apicid = mpc_apic_id(m, translation_table[mpc_record]); |
4655c7de | 94 | #else |
4655c7de AS |
95 | apicid = m->mpc_apicid; |
96 | #endif | |
1da177e4 | 97 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 98 | bootup_cpu = " (Bootup-CPU)"; |
1da177e4 | 99 | boot_cpu_physical_apicid = m->mpc_apicid; |
1da177e4 LT |
100 | } |
101 | ||
746f2244 | 102 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); |
c853c676 | 103 | generic_processor_info(apicid, m->mpc_apicver); |
1da177e4 LT |
104 | } |
105 | ||
4ef81297 | 106 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
107 | { |
108 | char str[7]; | |
109 | ||
110 | memcpy(str, m->mpc_bustype, 6); | |
111 | str[6] = 0; | |
112 | ||
0ec153af | 113 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 114 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); |
0ec153af AS |
115 | #else |
116 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
117 | #endif | |
1da177e4 | 118 | |
5e4edbb7 | 119 | #if MAX_MP_BUSSES < 256 |
c0ec31ad RD |
120 | if (m->mpc_busid >= MAX_MP_BUSSES) { |
121 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " | |
4ef81297 AS |
122 | " is too large, max. supported is %d\n", |
123 | m->mpc_busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
124 | return; |
125 | } | |
5e4edbb7 | 126 | #endif |
c0ec31ad | 127 | |
f8924e77 AS |
128 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
129 | set_bit(m->mpc_busid, mp_bus_not_pci); | |
130 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) | |
131 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; | |
132 | #endif | |
133 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
d285e338 | 134 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 135 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
d285e338 | 136 | #endif |
a6333c3c | 137 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
138 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
139 | mp_current_pci_id++; | |
c0a282c2 AS |
140 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) |
141 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; | |
4ef81297 | 142 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
9e0a2de2 | 143 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; |
4ef81297 | 144 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) { |
1da177e4 | 145 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; |
c0a282c2 | 146 | #endif |
f8924e77 AS |
147 | } else |
148 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); | |
1da177e4 LT |
149 | } |
150 | ||
61048c63 AS |
151 | #ifdef CONFIG_X86_IO_APIC |
152 | ||
857033a6 AS |
153 | static int bad_ioapic(unsigned long address) |
154 | { | |
155 | if (nr_ioapics >= MAX_IO_APICS) { | |
156 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
157 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
158 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
159 | } | |
160 | if (!address) { | |
161 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
162 | " found in table, skipping!\n"); | |
163 | return 1; | |
164 | } | |
165 | return 0; | |
166 | } | |
167 | ||
4ef81297 | 168 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
169 | { |
170 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
171 | return; | |
172 | ||
64883ab0 | 173 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", |
4ef81297 | 174 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
857033a6 AS |
175 | |
176 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 177 | return; |
857033a6 | 178 | |
1da177e4 LT |
179 | mp_ioapics[nr_ioapics] = *m; |
180 | nr_ioapics++; | |
181 | } | |
182 | ||
4ef81297 | 183 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 184 | { |
4ef81297 | 185 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
186 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
187 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
4ef81297 AS |
188 | m->mpc_irqtype, m->mpc_irqflag & 3, |
189 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
190 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
1da177e4 LT |
191 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
192 | panic("Max # of irq sources exceeded!!\n"); | |
193 | } | |
194 | ||
61048c63 AS |
195 | #endif |
196 | ||
4ef81297 | 197 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
198 | { |
199 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
200 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
4ef81297 AS |
201 | m->mpc_irqtype, m->mpc_irqflag & 3, |
202 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
203 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
204 | } |
205 | ||
206 | #ifdef CONFIG_X86_NUMAQ | |
4ef81297 | 207 | static void __init MP_translation_info(struct mpc_config_translation *m) |
1da177e4 | 208 | { |
4ef81297 AS |
209 | printk(KERN_INFO |
210 | "Translation: record %d, type %d, quad %d, global %d, local %d\n", | |
211 | mpc_record, m->trans_type, m->trans_quad, m->trans_global, | |
212 | m->trans_local); | |
1da177e4 | 213 | |
4ef81297 | 214 | if (mpc_record >= MAX_MPC_ENTRY) |
1da177e4 LT |
215 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); |
216 | else | |
4ef81297 | 217 | translation_table[mpc_record] = m; /* stash this for later */ |
1da177e4 LT |
218 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
219 | node_set_online(m->trans_quad); | |
220 | } | |
221 | ||
222 | /* | |
223 | * Read/parse the MPC oem tables | |
224 | */ | |
225 | ||
4ef81297 AS |
226 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, |
227 | unsigned short oemsize) | |
1da177e4 | 228 | { |
4ef81297 AS |
229 | int count = sizeof(*oemtable); /* the header size */ |
230 | unsigned char *oemptr = ((unsigned char *)oemtable) + count; | |
231 | ||
1da177e4 | 232 | mpc_record = 0; |
4ef81297 AS |
233 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", |
234 | oemtable); | |
235 | if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) { | |
236 | printk(KERN_WARNING | |
237 | "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
238 | oemtable->oem_signature[0], oemtable->oem_signature[1], | |
239 | oemtable->oem_signature[2], oemtable->oem_signature[3]); | |
1da177e4 LT |
240 | return; |
241 | } | |
4ef81297 | 242 | if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) { |
1da177e4 LT |
243 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
244 | return; | |
245 | } | |
246 | while (count < oemtable->oem_length) { | |
247 | switch (*oemptr) { | |
4ef81297 | 248 | case MP_TRANSLATION: |
1da177e4 | 249 | { |
4ef81297 AS |
250 | struct mpc_config_translation *m = |
251 | (struct mpc_config_translation *)oemptr; | |
1da177e4 LT |
252 | MP_translation_info(m); |
253 | oemptr += sizeof(*m); | |
254 | count += sizeof(*m); | |
255 | ++mpc_record; | |
256 | break; | |
257 | } | |
4ef81297 | 258 | default: |
1da177e4 | 259 | { |
4ef81297 AS |
260 | printk(KERN_WARNING |
261 | "Unrecognised OEM table entry type! - %d\n", | |
262 | (int)*oemptr); | |
1da177e4 LT |
263 | return; |
264 | } | |
265 | } | |
4ef81297 | 266 | } |
1da177e4 LT |
267 | } |
268 | ||
269 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, | |
4ef81297 | 270 | char *productid) |
1da177e4 LT |
271 | { |
272 | if (strncmp(oem, "IBM NUMA", 8)) | |
273 | printk("Warning! May not be a NUMA-Q system!\n"); | |
274 | if (mpc->mpc_oemptr) | |
4ef81297 AS |
275 | smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr, |
276 | mpc->mpc_oemsize); | |
1da177e4 | 277 | } |
4ef81297 | 278 | #endif /* CONFIG_X86_NUMAQ */ |
1da177e4 LT |
279 | |
280 | /* | |
281 | * Read/parse the MPC | |
282 | */ | |
283 | ||
888032cd | 284 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
285 | { |
286 | char str[16]; | |
287 | char oem[10]; | |
4ef81297 AS |
288 | int count = sizeof(*mpc); |
289 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
1da177e4 | 290 | |
4ef81297 | 291 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { |
e950bea8 AS |
292 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", |
293 | mpc->mpc_signature[0], mpc->mpc_signature[1], | |
294 | mpc->mpc_signature[2], mpc->mpc_signature[3]); | |
1da177e4 LT |
295 | return 0; |
296 | } | |
4ef81297 | 297 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
e950bea8 | 298 | printk(KERN_ERR "MPTABLE: checksum error!\n"); |
1da177e4 LT |
299 | return 0; |
300 | } | |
4ef81297 | 301 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
e950bea8 | 302 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
4ef81297 | 303 | mpc->mpc_spec); |
1da177e4 LT |
304 | return 0; |
305 | } | |
306 | if (!mpc->mpc_lapic) { | |
e950bea8 | 307 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
308 | return 0; |
309 | } | |
4ef81297 AS |
310 | memcpy(oem, mpc->mpc_oem, 8); |
311 | oem[8] = 0; | |
e950bea8 | 312 | printk(KERN_INFO "MPTABLE: OEM ID: %s ", oem); |
1da177e4 | 313 | |
4ef81297 AS |
314 | memcpy(str, mpc->mpc_productid, 12); |
315 | str[12] = 0; | |
316 | printk("Product ID: %s ", str); | |
1da177e4 | 317 | |
e950bea8 | 318 | #ifdef CONFIG_X86_32 |
1da177e4 | 319 | mps_oem_check(mpc, oem, str); |
e950bea8 AS |
320 | #endif |
321 | printk(KERN_INFO "MPTABLE: Product ID: %s ", str); | |
1da177e4 | 322 | |
e950bea8 | 323 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 | 324 | |
e950bea8 | 325 | /* save the local APIC address, it might be non-default */ |
1da177e4 LT |
326 | if (!acpi_lapic) |
327 | mp_lapic_addr = mpc->mpc_lapic; | |
328 | ||
888032cd AS |
329 | if (early) |
330 | return 1; | |
331 | ||
1da177e4 | 332 | /* |
4ef81297 | 333 | * Now process the configuration blocks. |
1da177e4 | 334 | */ |
86420506 | 335 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 336 | mpc_record = 0; |
86420506 | 337 | #endif |
1da177e4 | 338 | while (count < mpc->mpc_length) { |
4ef81297 AS |
339 | switch (*mpt) { |
340 | case MP_PROCESSOR: | |
1da177e4 | 341 | { |
4ef81297 AS |
342 | struct mpc_config_processor *m = |
343 | (struct mpc_config_processor *)mpt; | |
1da177e4 LT |
344 | /* ACPI may have already provided this data */ |
345 | if (!acpi_lapic) | |
346 | MP_processor_info(m); | |
347 | mpt += sizeof(*m); | |
348 | count += sizeof(*m); | |
349 | break; | |
350 | } | |
4ef81297 | 351 | case MP_BUS: |
1da177e4 | 352 | { |
4ef81297 AS |
353 | struct mpc_config_bus *m = |
354 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
355 | MP_bus_info(m); |
356 | mpt += sizeof(*m); | |
357 | count += sizeof(*m); | |
358 | break; | |
359 | } | |
4ef81297 | 360 | case MP_IOAPIC: |
1da177e4 | 361 | { |
61048c63 | 362 | #ifdef CONFIG_X86_IO_APIC |
4ef81297 AS |
363 | struct mpc_config_ioapic *m = |
364 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 365 | MP_ioapic_info(m); |
61048c63 | 366 | #endif |
4ef81297 AS |
367 | mpt += sizeof(struct mpc_config_ioapic); |
368 | count += sizeof(struct mpc_config_ioapic); | |
1da177e4 LT |
369 | break; |
370 | } | |
4ef81297 | 371 | case MP_INTSRC: |
1da177e4 | 372 | { |
61048c63 | 373 | #ifdef CONFIG_X86_IO_APIC |
4ef81297 AS |
374 | struct mpc_config_intsrc *m = |
375 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
376 | |
377 | MP_intsrc_info(m); | |
61048c63 | 378 | #endif |
4ef81297 AS |
379 | mpt += sizeof(struct mpc_config_intsrc); |
380 | count += sizeof(struct mpc_config_intsrc); | |
1da177e4 LT |
381 | break; |
382 | } | |
4ef81297 | 383 | case MP_LINTSRC: |
1da177e4 | 384 | { |
4ef81297 AS |
385 | struct mpc_config_lintsrc *m = |
386 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 387 | MP_lintsrc_info(m); |
4ef81297 AS |
388 | mpt += sizeof(*m); |
389 | count += sizeof(*m); | |
1da177e4 LT |
390 | break; |
391 | } | |
4ef81297 | 392 | default: |
1da177e4 LT |
393 | { |
394 | count = mpc->mpc_length; | |
395 | break; | |
396 | } | |
397 | } | |
86420506 | 398 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 399 | ++mpc_record; |
86420506 | 400 | #endif |
1da177e4 | 401 | } |
3c43f039 | 402 | setup_apic_routing(); |
1da177e4 | 403 | if (!num_processors) |
e950bea8 | 404 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
405 | return num_processors; |
406 | } | |
407 | ||
61048c63 AS |
408 | #ifdef CONFIG_X86_IO_APIC |
409 | ||
1da177e4 LT |
410 | static int __init ELCR_trigger(unsigned int irq) |
411 | { | |
412 | unsigned int port; | |
413 | ||
414 | port = 0x4d0 + (irq >> 3); | |
415 | return (inb(port) >> (irq & 7)) & 1; | |
416 | } | |
417 | ||
418 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
419 | { | |
420 | struct mpc_config_intsrc intsrc; | |
421 | int i; | |
422 | int ELCR_fallback = 0; | |
423 | ||
424 | intsrc.mpc_type = MP_INTSRC; | |
4ef81297 | 425 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
426 | intsrc.mpc_srcbus = 0; |
427 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
428 | ||
429 | intsrc.mpc_irqtype = mp_INT; | |
430 | ||
431 | /* | |
432 | * If true, we have an ISA/PCI system with no IRQ entries | |
433 | * in the MP table. To prevent the PCI interrupts from being set up | |
434 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
435 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
436 | * never be level sensitive, so we simply see if the ELCR agrees. | |
437 | * If it does, we assume it's valid. | |
438 | */ | |
439 | if (mpc_default_type == 5) { | |
62441bf1 AS |
440 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
441 | "falling back to ELCR\n"); | |
1da177e4 | 442 | |
62441bf1 AS |
443 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
444 | ELCR_trigger(13)) | |
445 | printk(KERN_ERR "ELCR contains invalid data... " | |
446 | "not using ELCR\n"); | |
1da177e4 | 447 | else { |
4ef81297 AS |
448 | printk(KERN_INFO |
449 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
450 | ELCR_fallback = 1; |
451 | } | |
452 | } | |
453 | ||
454 | for (i = 0; i < 16; i++) { | |
455 | switch (mpc_default_type) { | |
456 | case 2: | |
457 | if (i == 0 || i == 13) | |
458 | continue; /* IRQ0 & IRQ13 not connected */ | |
459 | /* fall through */ | |
460 | default: | |
461 | if (i == 2) | |
462 | continue; /* IRQ2 is never connected */ | |
463 | } | |
464 | ||
465 | if (ELCR_fallback) { | |
466 | /* | |
467 | * If the ELCR indicates a level-sensitive interrupt, we | |
468 | * copy that information over to the MP table in the | |
469 | * irqflag field (level sensitive, active high polarity). | |
470 | */ | |
471 | if (ELCR_trigger(i)) | |
472 | intsrc.mpc_irqflag = 13; | |
473 | else | |
474 | intsrc.mpc_irqflag = 0; | |
475 | } | |
476 | ||
477 | intsrc.mpc_srcbusirq = i; | |
4ef81297 | 478 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
479 | MP_intsrc_info(&intsrc); |
480 | } | |
481 | ||
482 | intsrc.mpc_irqtype = mp_ExtINT; | |
483 | intsrc.mpc_srcbusirq = 0; | |
4ef81297 | 484 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
485 | MP_intsrc_info(&intsrc); |
486 | } | |
487 | ||
61048c63 AS |
488 | #endif |
489 | ||
1da177e4 LT |
490 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) |
491 | { | |
492 | struct mpc_config_processor processor; | |
493 | struct mpc_config_bus bus; | |
61048c63 | 494 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 | 495 | struct mpc_config_ioapic ioapic; |
61048c63 | 496 | #endif |
1da177e4 LT |
497 | struct mpc_config_lintsrc lintsrc; |
498 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
499 | int i; | |
500 | ||
501 | /* | |
502 | * local APIC has default address | |
503 | */ | |
504 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
505 | ||
506 | /* | |
507 | * 2 CPUs, numbered 0 & 1. | |
508 | */ | |
509 | processor.mpc_type = MP_PROCESSOR; | |
510 | /* Either an integrated APIC or a discrete 82489DX. */ | |
511 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
512 | processor.mpc_cpuflag = CPU_ENABLED; | |
513 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
4ef81297 | 514 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
1da177e4 LT |
515 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
516 | processor.mpc_reserved[0] = 0; | |
517 | processor.mpc_reserved[1] = 0; | |
518 | for (i = 0; i < 2; i++) { | |
519 | processor.mpc_apicid = i; | |
520 | MP_processor_info(&processor); | |
521 | } | |
522 | ||
523 | bus.mpc_type = MP_BUS; | |
524 | bus.mpc_busid = 0; | |
525 | switch (mpc_default_type) { | |
4ef81297 | 526 | default: |
62441bf1 | 527 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", |
4ef81297 AS |
528 | mpc_default_type); |
529 | /* fall through */ | |
530 | case 1: | |
531 | case 5: | |
532 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
533 | break; | |
534 | case 2: | |
535 | case 6: | |
536 | case 3: | |
537 | memcpy(bus.mpc_bustype, "EISA ", 6); | |
538 | break; | |
539 | case 4: | |
540 | case 7: | |
541 | memcpy(bus.mpc_bustype, "MCA ", 6); | |
1da177e4 LT |
542 | } |
543 | MP_bus_info(&bus); | |
544 | if (mpc_default_type > 4) { | |
545 | bus.mpc_busid = 1; | |
546 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
547 | MP_bus_info(&bus); | |
548 | } | |
549 | ||
61048c63 | 550 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
551 | ioapic.mpc_type = MP_IOAPIC; |
552 | ioapic.mpc_apicid = 2; | |
553 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
554 | ioapic.mpc_flags = MPC_APIC_USABLE; | |
555 | ioapic.mpc_apicaddr = 0xFEC00000; | |
556 | MP_ioapic_info(&ioapic); | |
557 | ||
558 | /* | |
559 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
560 | */ | |
561 | construct_default_ioirq_mptable(mpc_default_type); | |
61048c63 | 562 | #endif |
1da177e4 | 563 | lintsrc.mpc_type = MP_LINTSRC; |
4ef81297 | 564 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
565 | lintsrc.mpc_srcbusid = 0; |
566 | lintsrc.mpc_srcbusirq = 0; | |
567 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
568 | for (i = 0; i < 2; i++) { | |
569 | lintsrc.mpc_irqtype = linttypes[i]; | |
570 | lintsrc.mpc_destapiclint = i; | |
571 | MP_lintsrc_info(&lintsrc); | |
572 | } | |
573 | } | |
574 | ||
575 | static struct intel_mp_floating *mpf_found; | |
576 | ||
577 | /* | |
578 | * Scan the memory blocks for an SMP configuration block. | |
579 | */ | |
888032cd | 580 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
581 | { |
582 | struct intel_mp_floating *mpf = mpf_found; | |
583 | ||
888032cd AS |
584 | if (acpi_lapic && early) |
585 | return; | |
1da177e4 | 586 | /* |
4ef81297 | 587 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
1da177e4 LT |
588 | * processors, where MPS only supports physical. |
589 | */ | |
590 | if (acpi_lapic && acpi_ioapic) { | |
4421b1c8 AS |
591 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " |
592 | "information\n"); | |
1da177e4 | 593 | return; |
4ef81297 | 594 | } else if (acpi_lapic) |
4421b1c8 AS |
595 | printk(KERN_INFO "Using ACPI for processor (LAPIC) " |
596 | "configuration information\n"); | |
1da177e4 | 597 | |
4ef81297 AS |
598 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
599 | mpf->mpf_specification); | |
4421b1c8 | 600 | #ifdef CONFIG_X86_32 |
4ef81297 | 601 | if (mpf->mpf_feature2 & (1 << 7)) { |
1da177e4 LT |
602 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); |
603 | pic_mode = 1; | |
604 | } else { | |
605 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); | |
606 | pic_mode = 0; | |
607 | } | |
4421b1c8 | 608 | #endif |
1da177e4 LT |
609 | /* |
610 | * Now see if we need to read further. | |
611 | */ | |
612 | if (mpf->mpf_feature1 != 0) { | |
888032cd AS |
613 | if (early) { |
614 | /* | |
615 | * local APIC has default address | |
616 | */ | |
617 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
618 | return; | |
619 | } | |
1da177e4 | 620 | |
4ef81297 AS |
621 | printk(KERN_INFO "Default MP configuration #%d\n", |
622 | mpf->mpf_feature1); | |
1da177e4 LT |
623 | construct_default_ISA_mptable(mpf->mpf_feature1); |
624 | ||
625 | } else if (mpf->mpf_physptr) { | |
626 | ||
627 | /* | |
628 | * Read the physical hardware table. Anything here will | |
629 | * override the defaults. | |
630 | */ | |
888032cd | 631 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 632 | smp_found_config = 0; |
4ef81297 AS |
633 | printk(KERN_ERR |
634 | "BIOS bug, MP table errors detected!...\n"); | |
4421b1c8 AS |
635 | printk(KERN_ERR "... disabling SMP support. " |
636 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
637 | return; |
638 | } | |
61048c63 | 639 | |
888032cd AS |
640 | if (early) |
641 | return; | |
61048c63 | 642 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
643 | /* |
644 | * If there are no explicit MP IRQ entries, then we are | |
645 | * broken. We set up most of the low 16 IO-APIC pins to | |
646 | * ISA defaults and hope it will work. | |
647 | */ | |
648 | if (!mp_irq_entries) { | |
649 | struct mpc_config_bus bus; | |
650 | ||
4421b1c8 AS |
651 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " |
652 | "using default mptable. " | |
653 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
654 | |
655 | bus.mpc_type = MP_BUS; | |
656 | bus.mpc_busid = 0; | |
657 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
658 | MP_bus_info(&bus); | |
659 | ||
660 | construct_default_ioirq_mptable(0); | |
661 | } | |
61048c63 | 662 | #endif |
1da177e4 LT |
663 | } else |
664 | BUG(); | |
665 | ||
888032cd AS |
666 | if (!early) |
667 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
668 | /* |
669 | * Only use the first configuration found. | |
670 | */ | |
671 | } | |
672 | ||
888032cd AS |
673 | void __init early_get_smp_config(void) |
674 | { | |
675 | __get_smp_config(1); | |
676 | } | |
677 | ||
678 | void __init get_smp_config(void) | |
679 | { | |
680 | __get_smp_config(0); | |
681 | } | |
682 | ||
683 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
684 | unsigned reserve) | |
1da177e4 | 685 | { |
92fd4b7a AS |
686 | extern void __bad_mpf_size(void); |
687 | unsigned int *bp = phys_to_virt(base); | |
1da177e4 LT |
688 | struct intel_mp_floating *mpf; |
689 | ||
92fd4b7a | 690 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 | 691 | if (sizeof(*mpf) != 16) |
92fd4b7a | 692 | __bad_mpf_size(); |
1da177e4 LT |
693 | |
694 | while (length > 0) { | |
695 | mpf = (struct intel_mp_floating *)bp; | |
696 | if ((*bp == SMP_MAGIC_IDENT) && | |
4ef81297 AS |
697 | (mpf->mpf_length == 1) && |
698 | !mpf_checksum((unsigned char *)bp, 16) && | |
699 | ((mpf->mpf_specification == 1) | |
700 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
701 | |
702 | smp_found_config = 1; | |
92fd4b7a AS |
703 | mpf_found = mpf; |
704 | #ifdef CONFIG_X86_32 | |
e91a3b43 | 705 | printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n", |
4ef81297 | 706 | mpf, virt_to_phys(mpf)); |
72a7fe39 BW |
707 | reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE, |
708 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
709 | if (mpf->mpf_physptr) { |
710 | /* | |
711 | * We cannot access to MPC table to compute | |
712 | * table size yet, as only few megabytes from | |
713 | * the bottom is mapped now. | |
714 | * PC-9800's MPC table places on the very last | |
715 | * of physical memory; so that simply reserving | |
716 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() | |
717 | * in reserve_bootmem. | |
718 | */ | |
719 | unsigned long size = PAGE_SIZE; | |
720 | unsigned long end = max_low_pfn * PAGE_SIZE; | |
721 | if (mpf->mpf_physptr + size > end) | |
722 | size = end - mpf->mpf_physptr; | |
72a7fe39 BW |
723 | reserve_bootmem(mpf->mpf_physptr, size, |
724 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
725 | } |
726 | ||
92fd4b7a AS |
727 | #else |
728 | if (!reserve) | |
729 | return 1; | |
730 | ||
731 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); | |
732 | if (mpf->mpf_physptr) | |
733 | reserve_bootmem_generic(mpf->mpf_physptr, | |
734 | PAGE_SIZE); | |
735 | #endif | |
736 | return 1; | |
1da177e4 LT |
737 | } |
738 | bp += 4; | |
739 | length -= 16; | |
740 | } | |
741 | return 0; | |
742 | } | |
743 | ||
888032cd | 744 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
745 | { |
746 | unsigned int address; | |
747 | ||
748 | /* | |
749 | * FIXME: Linux assumes you have 640K of base ram.. | |
750 | * this continues the error... | |
751 | * | |
752 | * 1) Scan the bottom 1K for a signature | |
753 | * 2) Scan the top 1K of base RAM | |
754 | * 3) Scan the 64K of bios | |
755 | */ | |
888032cd AS |
756 | if (smp_scan_config(0x0, 0x400, reserve) || |
757 | smp_scan_config(639 * 0x400, 0x400, reserve) || | |
758 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
759 | return; |
760 | /* | |
761 | * If it is an SMP machine we should know now, unless the | |
762 | * configuration is in an EISA/MCA bus machine with an | |
763 | * extended bios data area. | |
764 | * | |
765 | * there is a real-mode segmented pointer pointing to the | |
766 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
767 | * | |
768 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
769 | * area, and as such this kind of SMP config may be less | |
770 | * trustworthy, simply because the SMP table may have been | |
771 | * stomped on during early boot. These loaders are buggy and | |
772 | * should be fixed. | |
773 | * | |
774 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
775 | */ | |
776 | ||
777 | address = get_bios_ebda(); | |
778 | if (address) | |
888032cd AS |
779 | smp_scan_config(address, 0x400, reserve); |
780 | } | |
781 | ||
782 | void __init early_find_smp_config(void) | |
783 | { | |
784 | __find_smp_config(0); | |
785 | } | |
786 | ||
787 | void __init find_smp_config(void) | |
788 | { | |
789 | __find_smp_config(1); | |
1da177e4 LT |
790 | } |
791 | ||
792 | /* -------------------------------------------------------------------------- | |
793 | ACPI-based MP Configuration | |
794 | -------------------------------------------------------------------------- */ | |
795 | ||
888ba6c6 | 796 | #ifdef CONFIG_ACPI |
1da177e4 | 797 | |
8466361a | 798 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
799 | |
800 | #define MP_ISA_BUS 0 | |
801 | #define MP_MAX_IOAPIC_PIN 127 | |
802 | ||
9e5c5f1d | 803 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 804 | |
4ef81297 | 805 | static int mp_find_ioapic(int gsi) |
1da177e4 | 806 | { |
19f03ffe | 807 | int i = 0; |
1da177e4 LT |
808 | |
809 | /* Find the IOAPIC that manages this GSI. */ | |
810 | for (i = 0; i < nr_ioapics; i++) { | |
811 | if ((gsi >= mp_ioapic_routing[i].gsi_base) | |
4ef81297 | 812 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
813 | return i; |
814 | } | |
815 | ||
816 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
817 | return -1; |
818 | } | |
1da177e4 | 819 | |
e3e3ffa2 AS |
820 | static u8 uniq_ioapic_id(u8 id) |
821 | { | |
22cbb4bd | 822 | #ifdef CONFIG_X86_32 |
e3e3ffa2 AS |
823 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
824 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
825 | return io_apic_get_unique_id(nr_ioapics, id); | |
826 | else | |
827 | return id; | |
22cbb4bd AS |
828 | #else |
829 | int i; | |
830 | DECLARE_BITMAP(used, 256); | |
831 | bitmap_zero(used, 256); | |
832 | for (i = 0; i < nr_ioapics; i++) { | |
833 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
834 | __set_bit(ia->mpc_apicid, used); | |
835 | } | |
836 | if (!test_bit(id, used)) | |
837 | return id; | |
838 | return find_first_zero_bit(used, 256); | |
839 | #endif | |
e3e3ffa2 AS |
840 | } |
841 | ||
a65d1d64 | 842 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 843 | { |
19f03ffe | 844 | int idx = 0; |
1da177e4 | 845 | |
857033a6 | 846 | if (bad_ioapic(address)) |
1da177e4 | 847 | return; |
1da177e4 | 848 | |
e3e3ffa2 | 849 | idx = nr_ioapics; |
1da177e4 LT |
850 | |
851 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
852 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
853 | mp_ioapics[idx].mpc_apicaddr = address; | |
854 | ||
855 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
e3e3ffa2 | 856 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
57b733e9 | 857 | #ifdef CONFIG_X86_32 |
1da177e4 | 858 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
57b733e9 AS |
859 | #else |
860 | mp_ioapics[idx].mpc_apicver = 0; | |
861 | #endif | |
4ef81297 | 862 | /* |
1da177e4 LT |
863 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
864 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
865 | */ | |
866 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
867 | mp_ioapic_routing[idx].gsi_base = gsi_base; | |
64883ab0 | 868 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
4ef81297 | 869 | io_apic_get_redir_entries(idx); |
1da177e4 | 870 | |
57b733e9 | 871 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
64883ab0 | 872 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
57b733e9 | 873 | mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, |
4ef81297 | 874 | mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end); |
e3e3ffa2 AS |
875 | |
876 | nr_ioapics++; | |
1da177e4 LT |
877 | } |
878 | ||
4ef81297 | 879 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
880 | { |
881 | struct mpc_config_intsrc intsrc; | |
4ef81297 AS |
882 | int ioapic = -1; |
883 | int pin = -1; | |
1da177e4 | 884 | |
4ef81297 | 885 | /* |
1da177e4 LT |
886 | * Convert 'gsi' to 'ioapic.pin'. |
887 | */ | |
888 | ioapic = mp_find_ioapic(gsi); | |
889 | if (ioapic < 0) | |
890 | return; | |
891 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
892 | ||
893 | /* | |
894 | * TBD: This check is for faulty timer entries, where the override | |
4ef81297 | 895 | * erroneously sets the trigger to level, resulting in a HUGE |
1da177e4 LT |
896 | * increase of timer interrupts! |
897 | */ | |
898 | if ((bus_irq == 0) && (trigger == 3)) | |
899 | trigger = 1; | |
900 | ||
901 | intsrc.mpc_type = MP_INTSRC; | |
902 | intsrc.mpc_irqtype = mp_INT; | |
903 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
904 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
4ef81297 AS |
905 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
906 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
907 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 LT |
908 | |
909 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
4ef81297 AS |
910 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
911 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
912 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
913 | ||
914 | mp_irqs[mp_irq_entries] = intsrc; | |
915 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
916 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
917 | } |
918 | ||
2df29726 AS |
919 | int es7000_plat; |
920 | ||
4ef81297 | 921 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
922 | { |
923 | struct mpc_config_intsrc intsrc; | |
19f03ffe AK |
924 | int i = 0; |
925 | int ioapic = -1; | |
1da177e4 | 926 | |
c0a282c2 | 927 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
4ef81297 | 928 | /* |
1da177e4 LT |
929 | * Fabricate the legacy ISA bus (bus #31). |
930 | */ | |
931 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; | |
c0a282c2 | 932 | #endif |
a6333c3c | 933 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
934 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
935 | ||
936 | /* | |
937 | * Older generations of ES7000 have no legacy identity mappings | |
938 | */ | |
939 | if (es7000_plat == 1) | |
940 | return; | |
941 | ||
4ef81297 AS |
942 | /* |
943 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
1da177e4 LT |
944 | */ |
945 | ioapic = mp_find_ioapic(0); | |
946 | if (ioapic < 0) | |
947 | return; | |
948 | ||
949 | intsrc.mpc_type = MP_INTSRC; | |
4ef81297 | 950 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 | 951 | intsrc.mpc_srcbus = MP_ISA_BUS; |
61048c63 | 952 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 | 953 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; |
61048c63 | 954 | #endif |
4ef81297 | 955 | /* |
1da177e4 | 956 | * Use the default configuration for the IRQs 0-15. Unless |
27b46d76 | 957 | * overridden by (MADT) interrupt source override entries. |
1da177e4 LT |
958 | */ |
959 | for (i = 0; i < 16; i++) { | |
960 | int idx; | |
961 | ||
962 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
963 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
964 | ||
965 | /* Do we already have a mapping for this ISA IRQ? */ | |
4ef81297 AS |
966 | if (irq->mpc_srcbus == MP_ISA_BUS |
967 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
968 | break; |
969 | ||
970 | /* Do we already have a mapping for this IOAPIC pin */ | |
971 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
4ef81297 | 972 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
973 | break; |
974 | } | |
975 | ||
976 | if (idx != mp_irq_entries) { | |
977 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
4ef81297 | 978 | continue; /* IRQ already used */ |
1da177e4 LT |
979 | } |
980 | ||
981 | intsrc.mpc_irqtype = mp_INT; | |
4ef81297 | 982 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
983 | intsrc.mpc_dstirq = i; |
984 | ||
985 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
4ef81297 AS |
986 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
987 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
988 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
989 | intsrc.mpc_dstirq); |
990 | ||
991 | mp_irqs[mp_irq_entries] = intsrc; | |
992 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
993 | panic("Max # of irq sources exceeded!\n"); | |
994 | } | |
995 | } | |
996 | ||
19f03ffe | 997 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 998 | { |
19f03ffe AK |
999 | int ioapic = -1; |
1000 | int ioapic_pin = 0; | |
1001 | int idx, bit = 0; | |
cfa08d6c AS |
1002 | #ifdef CONFIG_X86_32 |
1003 | #define MAX_GSI_NUM 4096 | |
1004 | #define IRQ_COMPRESSION_START 64 | |
1005 | ||
2ba7deef | 1006 | static int pci_irq = IRQ_COMPRESSION_START; |
c434b7a6 | 1007 | /* |
ab4a574e | 1008 | * Mapping between Global System Interrupts, which |
c434b7a6 NP |
1009 | * represent all possible interrupts, and IRQs |
1010 | * assigned to actual devices. | |
1011 | */ | |
4ef81297 | 1012 | static int gsi_to_irq[MAX_GSI_NUM]; |
cfa08d6c AS |
1013 | #else |
1014 | ||
1015 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
1016 | return gsi; | |
1017 | #endif | |
1da177e4 | 1018 | |
1da177e4 | 1019 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 1020 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 1021 | return gsi; |
1da177e4 LT |
1022 | |
1023 | ioapic = mp_find_ioapic(gsi); | |
1024 | if (ioapic < 0) { | |
1025 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
1026 | return gsi; | |
1027 | } | |
1028 | ||
1029 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
1030 | ||
cfa08d6c | 1031 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1032 | if (ioapic_renumber_irq) |
1033 | gsi = ioapic_renumber_irq(ioapic, gsi); | |
cfa08d6c | 1034 | #endif |
1da177e4 | 1035 | |
4ef81297 AS |
1036 | /* |
1037 | * Avoid pin reprogramming. PRTs typically include entries | |
1da177e4 LT |
1038 | * with redundant pin->gsi mappings (but unique PCI devices); |
1039 | * we only program the IOAPIC on the first. | |
1040 | */ | |
1041 | bit = ioapic_pin % 32; | |
1042 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
1043 | if (idx > 3) { | |
1044 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
4ef81297 AS |
1045 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
1046 | ioapic_pin); | |
1da177e4 LT |
1047 | return gsi; |
1048 | } | |
4ef81297 | 1049 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
1050 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
1051 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cfa08d6c | 1052 | #ifdef CONFIG_X86_32 |
2ba7deef | 1053 | return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]); |
cfa08d6c AS |
1054 | #else |
1055 | return gsi; | |
1056 | #endif | |
1da177e4 LT |
1057 | } |
1058 | ||
4ef81297 | 1059 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
cfa08d6c | 1060 | #ifdef CONFIG_X86_32 |
2ba7deef LB |
1061 | /* |
1062 | * For GSI >= 64, use IRQ compression | |
1063 | */ | |
1064 | if ((gsi >= IRQ_COMPRESSION_START) | |
4ef81297 | 1065 | && (triggering == ACPI_LEVEL_SENSITIVE)) { |
c434b7a6 NP |
1066 | /* |
1067 | * For PCI devices assign IRQs in order, avoiding gaps | |
1068 | * due to unused I/O APIC pins. | |
1069 | */ | |
1070 | int irq = gsi; | |
1071 | if (gsi < MAX_GSI_NUM) { | |
e0c1e9bf KM |
1072 | /* |
1073 | * Retain the VIA chipset work-around (gsi > 15), but | |
1074 | * avoid a problem where the 8254 timer (IRQ0) is setup | |
1075 | * via an override (so it's not on pin 0 of the ioapic), | |
1076 | * and at the same time, the pin 0 interrupt is a PCI | |
1077 | * type. The gsi > 15 test could cause these two pins | |
1078 | * to be shared as IRQ0, and they are not shareable. | |
1079 | * So test for this condition, and if necessary, avoid | |
1080 | * the pin collision. | |
1081 | */ | |
ede1389f | 1082 | gsi = pci_irq++; |
e1afc3f5 NP |
1083 | /* |
1084 | * Don't assign IRQ used by ACPI SCI | |
1085 | */ | |
cee324b1 | 1086 | if (gsi == acpi_gbl_FADT.sci_interrupt) |
e1afc3f5 | 1087 | gsi = pci_irq++; |
c434b7a6 NP |
1088 | gsi_to_irq[irq] = gsi; |
1089 | } else { | |
1090 | printk(KERN_ERR "GSI %u is too high\n", gsi); | |
1091 | return gsi; | |
1092 | } | |
1093 | } | |
cfa08d6c | 1094 | #endif |
1da177e4 | 1095 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
4ef81297 AS |
1096 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
1097 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
1098 | return gsi; |
1099 | } | |
1100 | ||
8466361a | 1101 | #endif /* CONFIG_X86_IO_APIC */ |
888ba6c6 | 1102 | #endif /* CONFIG_ACPI */ |