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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
11113f84 | 3 | * Intel Multiprocessor Specification 1.1 and 1.4 |
1da177e4 LT |
4 | * compliant MP-table parsing routines. |
5 | * | |
87c6fe26 | 6 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 7 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
85bdddec | 8 | * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/mm.h> | |
1da177e4 | 12 | #include <linux/init.h> |
1da177e4 | 13 | #include <linux/delay.h> |
1da177e4 | 14 | #include <linux/bootmem.h> |
72d7c3b3 | 15 | #include <linux/memblock.h> |
1da177e4 LT |
16 | #include <linux/kernel_stat.h> |
17 | #include <linux/mc146818rtc.h> | |
18 | #include <linux/bitops.h> | |
85bdddec | 19 | #include <linux/acpi.h> |
103ceffb | 20 | #include <linux/smp.h> |
629e15d2 | 21 | #include <linux/pci.h> |
1da177e4 | 22 | |
f7a0c786 | 23 | #include <asm/irqdomain.h> |
1da177e4 LT |
24 | #include <asm/mtrr.h> |
25 | #include <asm/mpspec.h> | |
85bdddec | 26 | #include <asm/pgalloc.h> |
1da177e4 | 27 | #include <asm/io_apic.h> |
85bdddec | 28 | #include <asm/proto.h> |
ce3fe6b2 | 29 | #include <asm/bios_ebda.h> |
66441bd3 | 30 | #include <asm/e820/api.h> |
3c9cb6de | 31 | #include <asm/setup.h> |
4884d8e6 | 32 | #include <asm/smp.h> |
1da177e4 | 33 | |
7b6aa335 | 34 | #include <asm/apic.h> |
1da177e4 LT |
35 | /* |
36 | * Checksum an MP configuration block. | |
37 | */ | |
38 | ||
39 | static int __init mpf_checksum(unsigned char *mp, int len) | |
40 | { | |
41 | int sum = 0; | |
42 | ||
43 | while (len--) | |
44 | sum += *mp++; | |
45 | ||
46 | return sum & 0xFF; | |
47 | } | |
48 | ||
fd6c6661 TG |
49 | int __init default_mpc_apic_id(struct mpc_cpu *m) |
50 | { | |
51 | return m->apicid; | |
52 | } | |
53 | ||
f4f21b71 | 54 | static void __init MP_processor_info(struct mpc_cpu *m) |
c853c676 AS |
55 | { |
56 | int apicid; | |
746f2244 | 57 | char *bootup_cpu = ""; |
c853c676 | 58 | |
c4563826 | 59 | if (!(m->cpuflag & CPU_ENABLED)) { |
7b1292e2 | 60 | disabled_cpus++; |
1da177e4 | 61 | return; |
7b1292e2 | 62 | } |
64898a8b | 63 | |
fd6c6661 | 64 | apicid = x86_init.mpparse.mpc_apic_id(m); |
64898a8b | 65 | |
c4563826 | 66 | if (m->cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 67 | bootup_cpu = " (Bootup-CPU)"; |
c4563826 | 68 | boot_cpu_physical_apicid = m->apicid; |
1da177e4 LT |
69 | } |
70 | ||
b1bfd5ea | 71 | pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); |
c4563826 | 72 | generic_processor_info(apicid, m->apicver); |
1da177e4 LT |
73 | } |
74 | ||
85cc35fa | 75 | #ifdef CONFIG_X86_IO_APIC |
90e1c696 | 76 | void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str) |
1da177e4 | 77 | { |
d4c715fa | 78 | memcpy(str, m->bustype, 6); |
1da177e4 | 79 | str[6] = 0; |
90e1c696 TG |
80 | apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); |
81 | } | |
1da177e4 | 82 | |
90e1c696 TG |
83 | static void __init MP_bus_info(struct mpc_bus *m) |
84 | { | |
85 | char str[7]; | |
1da177e4 | 86 | |
90e1c696 | 87 | x86_init.mpparse.mpc_oem_bus_info(m, str); |
1da177e4 | 88 | |
5e4edbb7 | 89 | #if MAX_MP_BUSSES < 256 |
d4c715fa | 90 | if (m->busid >= MAX_MP_BUSSES) { |
b1bfd5ea JL |
91 | pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n", |
92 | m->busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
93 | return; |
94 | } | |
5e4edbb7 | 95 | #endif |
c0ec31ad | 96 | |
9e686668 | 97 | set_bit(m->busid, mp_bus_not_pci); |
f8924e77 | 98 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
bb8187d3 | 99 | #ifdef CONFIG_EISA |
d4c715fa | 100 | mp_bus_id_to_type[m->busid] = MP_BUS_ISA; |
f8924e77 AS |
101 | #endif |
102 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
52fdb568 TG |
103 | if (x86_init.mpparse.mpc_oem_pci_bus) |
104 | x86_init.mpparse.mpc_oem_pci_bus(m); | |
64898a8b | 105 | |
d4c715fa | 106 | clear_bit(m->busid, mp_bus_not_pci); |
bb8187d3 | 107 | #ifdef CONFIG_EISA |
d4c715fa | 108 | mp_bus_id_to_type[m->busid] = MP_BUS_PCI; |
4ef81297 | 109 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
d4c715fa | 110 | mp_bus_id_to_type[m->busid] = MP_BUS_EISA; |
c0a282c2 | 111 | #endif |
f8924e77 | 112 | } else |
b1bfd5ea | 113 | pr_warn("Unknown bustype %s - ignoring\n", str); |
1da177e4 | 114 | } |
61048c63 | 115 | |
2b85b5fb | 116 | static void __init MP_ioapic_info(struct mpc_ioapic *m) |
1da177e4 | 117 | { |
74501edc JL |
118 | struct ioapic_domain_cfg cfg = { |
119 | .type = IOAPIC_DOMAIN_LEGACY, | |
120 | .ops = &mp_ioapic_irqdomain_ops, | |
121 | }; | |
122 | ||
0e3fa13f | 123 | if (m->flags & MPC_APIC_USABLE) |
74501edc | 124 | mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg); |
2944e16b YL |
125 | } |
126 | ||
c2c21745 | 127 | static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) |
2944e16b | 128 | { |
b1bfd5ea JL |
129 | apic_printk(APIC_VERBOSE, |
130 | "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
c2c21745 JSR |
131 | mp_irq->irqtype, mp_irq->irqflag & 3, |
132 | (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus, | |
133 | mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); | |
2944e16b YL |
134 | } |
135 | ||
a6830278 JSR |
136 | #else /* CONFIG_X86_IO_APIC */ |
137 | static inline void __init MP_bus_info(struct mpc_bus *m) {} | |
138 | static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {} | |
a6830278 | 139 | #endif /* CONFIG_X86_IO_APIC */ |
1da177e4 | 140 | |
8fb2952b | 141 | static void __init MP_lintsrc_info(struct mpc_lintsrc *m) |
1da177e4 | 142 | { |
b1bfd5ea JL |
143 | apic_printk(APIC_VERBOSE, |
144 | "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
b5ced7cd JSR |
145 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid, |
146 | m->srcbusirq, m->destapic, m->destapiclint); | |
1da177e4 LT |
147 | } |
148 | ||
1da177e4 LT |
149 | /* |
150 | * Read/parse the MPC | |
151 | */ | |
f29521e4 | 152 | static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str) |
1da177e4 | 153 | { |
1da177e4 | 154 | |
6c65da50 | 155 | if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) { |
b1bfd5ea | 156 | pr_err("MPTABLE: bad signature [%c%c%c%c]!\n", |
6c65da50 JSR |
157 | mpc->signature[0], mpc->signature[1], |
158 | mpc->signature[2], mpc->signature[3]); | |
1da177e4 LT |
159 | return 0; |
160 | } | |
6c65da50 | 161 | if (mpf_checksum((unsigned char *)mpc, mpc->length)) { |
b1bfd5ea | 162 | pr_err("MPTABLE: checksum error!\n"); |
1da177e4 LT |
163 | return 0; |
164 | } | |
6c65da50 | 165 | if (mpc->spec != 0x01 && mpc->spec != 0x04) { |
b1bfd5ea | 166 | pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec); |
1da177e4 LT |
167 | return 0; |
168 | } | |
6c65da50 | 169 | if (!mpc->lapic) { |
b1bfd5ea | 170 | pr_err("MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
171 | return 0; |
172 | } | |
6c65da50 | 173 | memcpy(oem, mpc->oem, 8); |
4ef81297 | 174 | oem[8] = 0; |
b1bfd5ea | 175 | pr_info("MPTABLE: OEM ID: %s\n", oem); |
1da177e4 | 176 | |
6c65da50 | 177 | memcpy(str, mpc->productid, 12); |
4ef81297 | 178 | str[12] = 0; |
1da177e4 | 179 | |
b1bfd5ea | 180 | pr_info("MPTABLE: Product ID: %s\n", str); |
1da177e4 | 181 | |
b1bfd5ea | 182 | pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic); |
1da177e4 | 183 | |
2944e16b YL |
184 | return 1; |
185 | } | |
186 | ||
a6830278 JSR |
187 | static void skip_entry(unsigned char **ptr, int *count, int size) |
188 | { | |
189 | *ptr += size; | |
190 | *count += size; | |
191 | } | |
192 | ||
5a5737ea JSR |
193 | static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) |
194 | { | |
b1bfd5ea JL |
195 | pr_err("Your mptable is wrong, contact your HW vendor!\n"); |
196 | pr_cont("type %x\n", *mpt); | |
5a5737ea JSR |
197 | print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, |
198 | 1, mpc, mpc->length, 1); | |
199 | } | |
200 | ||
72302142 TG |
201 | void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } |
202 | ||
f29521e4 | 203 | static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) |
2944e16b YL |
204 | { |
205 | char str[16]; | |
206 | char oem[10]; | |
207 | ||
208 | int count = sizeof(*mpc); | |
209 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
210 | ||
211 | if (!smp_check_mpc(mpc, oem, str)) | |
212 | return 0; | |
213 | ||
f1157141 | 214 | /* Initialize the lapic mapping */ |
1da177e4 | 215 | if (!acpi_lapic) |
f1157141 | 216 | register_lapic_address(mpc->lapic); |
1da177e4 | 217 | |
888032cd AS |
218 | if (early) |
219 | return 1; | |
220 | ||
72302142 TG |
221 | if (mpc->oemptr) |
222 | x86_init.mpparse.smp_read_mpc_oem(mpc); | |
64898a8b | 223 | |
1da177e4 | 224 | /* |
4ef81297 | 225 | * Now process the configuration blocks. |
1da177e4 | 226 | */ |
f4848472 | 227 | x86_init.mpparse.mpc_record(0); |
64898a8b | 228 | |
6c65da50 | 229 | while (count < mpc->length) { |
4ef81297 AS |
230 | switch (*mpt) { |
231 | case MP_PROCESSOR: | |
a6830278 JSR |
232 | /* ACPI may have already provided this data */ |
233 | if (!acpi_lapic) | |
c58603e8 | 234 | MP_processor_info((struct mpc_cpu *)mpt); |
a6830278 JSR |
235 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
236 | break; | |
4ef81297 | 237 | case MP_BUS: |
c58603e8 | 238 | MP_bus_info((struct mpc_bus *)mpt); |
a6830278 JSR |
239 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
240 | break; | |
4ef81297 | 241 | case MP_IOAPIC: |
c58603e8 | 242 | MP_ioapic_info((struct mpc_ioapic *)mpt); |
a6830278 JSR |
243 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
244 | break; | |
4ef81297 | 245 | case MP_INTSRC: |
2d8009ba | 246 | mp_save_irq((struct mpc_intsrc *)mpt); |
a6830278 JSR |
247 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
248 | break; | |
4ef81297 | 249 | case MP_LINTSRC: |
c58603e8 | 250 | MP_lintsrc_info((struct mpc_lintsrc *)mpt); |
a6830278 JSR |
251 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
252 | break; | |
4ef81297 | 253 | default: |
711554db | 254 | /* wrong mptable */ |
5a5737ea | 255 | smp_dump_mptable(mpc, mpt); |
6c65da50 | 256 | count = mpc->length; |
711554db | 257 | break; |
1da177e4 | 258 | } |
f4848472 | 259 | x86_init.mpparse.mpc_record(1); |
1da177e4 | 260 | } |
e0da3364 | 261 | |
1da177e4 | 262 | if (!num_processors) |
b1bfd5ea | 263 | pr_err("MPTABLE: no processors registered!\n"); |
1da177e4 LT |
264 | return num_processors; |
265 | } | |
266 | ||
61048c63 AS |
267 | #ifdef CONFIG_X86_IO_APIC |
268 | ||
1da177e4 LT |
269 | static int __init ELCR_trigger(unsigned int irq) |
270 | { | |
271 | unsigned int port; | |
272 | ||
273 | port = 0x4d0 + (irq >> 3); | |
274 | return (inb(port) >> (irq & 7)) & 1; | |
275 | } | |
276 | ||
277 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
278 | { | |
540d4e72 | 279 | struct mpc_intsrc intsrc; |
1da177e4 LT |
280 | int i; |
281 | int ELCR_fallback = 0; | |
282 | ||
e253b396 JSR |
283 | intsrc.type = MP_INTSRC; |
284 | intsrc.irqflag = 0; /* conforming */ | |
285 | intsrc.srcbus = 0; | |
d5371430 | 286 | intsrc.dstapic = mpc_ioapic_id(0); |
1da177e4 | 287 | |
e253b396 | 288 | intsrc.irqtype = mp_INT; |
1da177e4 LT |
289 | |
290 | /* | |
291 | * If true, we have an ISA/PCI system with no IRQ entries | |
292 | * in the MP table. To prevent the PCI interrupts from being set up | |
293 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
294 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
295 | * never be level sensitive, so we simply see if the ELCR agrees. | |
296 | * If it does, we assume it's valid. | |
297 | */ | |
298 | if (mpc_default_type == 5) { | |
b1bfd5ea | 299 | pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); |
1da177e4 | 300 | |
62441bf1 AS |
301 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
302 | ELCR_trigger(13)) | |
b1bfd5ea | 303 | pr_err("ELCR contains invalid data... not using ELCR\n"); |
1da177e4 | 304 | else { |
b1bfd5ea | 305 | pr_info("Using ELCR to identify PCI interrupts\n"); |
1da177e4 LT |
306 | ELCR_fallback = 1; |
307 | } | |
308 | } | |
309 | ||
310 | for (i = 0; i < 16; i++) { | |
311 | switch (mpc_default_type) { | |
312 | case 2: | |
313 | if (i == 0 || i == 13) | |
314 | continue; /* IRQ0 & IRQ13 not connected */ | |
315 | /* fall through */ | |
316 | default: | |
317 | if (i == 2) | |
318 | continue; /* IRQ2 is never connected */ | |
319 | } | |
320 | ||
321 | if (ELCR_fallback) { | |
322 | /* | |
323 | * If the ELCR indicates a level-sensitive interrupt, we | |
324 | * copy that information over to the MP table in the | |
325 | * irqflag field (level sensitive, active high polarity). | |
326 | */ | |
327 | if (ELCR_trigger(i)) | |
e253b396 | 328 | intsrc.irqflag = 13; |
1da177e4 | 329 | else |
e253b396 | 330 | intsrc.irqflag = 0; |
1da177e4 LT |
331 | } |
332 | ||
e253b396 JSR |
333 | intsrc.srcbusirq = i; |
334 | intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
2d8009ba | 335 | mp_save_irq(&intsrc); |
1da177e4 LT |
336 | } |
337 | ||
e253b396 JSR |
338 | intsrc.irqtype = mp_ExtINT; |
339 | intsrc.srcbusirq = 0; | |
340 | intsrc.dstirq = 0; /* 8259A to INTIN0 */ | |
2d8009ba | 341 | mp_save_irq(&intsrc); |
1da177e4 LT |
342 | } |
343 | ||
61048c63 | 344 | |
39e00fe2 | 345 | static void __init construct_ioapic_table(int mpc_default_type) |
1da177e4 | 346 | { |
2b85b5fb | 347 | struct mpc_ioapic ioapic; |
00fb8606 | 348 | struct mpc_bus bus; |
1da177e4 | 349 | |
d4c715fa JSR |
350 | bus.type = MP_BUS; |
351 | bus.busid = 0; | |
1da177e4 | 352 | switch (mpc_default_type) { |
4ef81297 | 353 | default: |
b1bfd5ea | 354 | pr_err("???\nUnknown standard configuration %d\n", |
4ef81297 AS |
355 | mpc_default_type); |
356 | /* fall through */ | |
357 | case 1: | |
358 | case 5: | |
d4c715fa | 359 | memcpy(bus.bustype, "ISA ", 6); |
4ef81297 AS |
360 | break; |
361 | case 2: | |
362 | case 6: | |
363 | case 3: | |
d4c715fa | 364 | memcpy(bus.bustype, "EISA ", 6); |
4ef81297 | 365 | break; |
1da177e4 LT |
366 | } |
367 | MP_bus_info(&bus); | |
368 | if (mpc_default_type > 4) { | |
d4c715fa JSR |
369 | bus.busid = 1; |
370 | memcpy(bus.bustype, "PCI ", 6); | |
1da177e4 LT |
371 | MP_bus_info(&bus); |
372 | } | |
373 | ||
8f3e1df4 CG |
374 | ioapic.type = MP_IOAPIC; |
375 | ioapic.apicid = 2; | |
376 | ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
377 | ioapic.flags = MPC_APIC_USABLE; | |
378 | ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
379 | MP_ioapic_info(&ioapic); |
380 | ||
381 | /* | |
382 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
383 | */ | |
384 | construct_default_ioirq_mptable(mpc_default_type); | |
85cc35fa TG |
385 | } |
386 | #else | |
39e00fe2 | 387 | static inline void __init construct_ioapic_table(int mpc_default_type) { } |
61048c63 | 388 | #endif |
85cc35fa TG |
389 | |
390 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
391 | { | |
f4f21b71 | 392 | struct mpc_cpu processor; |
8fb2952b | 393 | struct mpc_lintsrc lintsrc; |
85cc35fa TG |
394 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
395 | int i; | |
396 | ||
397 | /* | |
398 | * local APIC has default address | |
399 | */ | |
400 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
401 | ||
402 | /* | |
403 | * 2 CPUs, numbered 0 & 1. | |
404 | */ | |
c4563826 | 405 | processor.type = MP_PROCESSOR; |
85cc35fa | 406 | /* Either an integrated APIC or a discrete 82489DX. */ |
c4563826 JSR |
407 | processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
408 | processor.cpuflag = CPU_ENABLED; | |
409 | processor.cpufeature = (boot_cpu_data.x86 << 8) | | |
85cc35fa | 410 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
16aaa537 | 411 | processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX]; |
c4563826 JSR |
412 | processor.reserved[0] = 0; |
413 | processor.reserved[1] = 0; | |
85cc35fa | 414 | for (i = 0; i < 2; i++) { |
c4563826 | 415 | processor.apicid = i; |
85cc35fa TG |
416 | MP_processor_info(&processor); |
417 | } | |
418 | ||
419 | construct_ioapic_table(mpc_default_type); | |
420 | ||
b5ced7cd JSR |
421 | lintsrc.type = MP_LINTSRC; |
422 | lintsrc.irqflag = 0; /* conforming */ | |
423 | lintsrc.srcbusid = 0; | |
424 | lintsrc.srcbusirq = 0; | |
425 | lintsrc.destapic = MP_APIC_ALL; | |
1da177e4 | 426 | for (i = 0; i < 2; i++) { |
b5ced7cd JSR |
427 | lintsrc.irqtype = linttypes[i]; |
428 | lintsrc.destapiclint = i; | |
1da177e4 LT |
429 | MP_lintsrc_info(&lintsrc); |
430 | } | |
431 | } | |
432 | ||
5997efb9 | 433 | static unsigned long mpf_base; |
1da177e4 | 434 | |
8d4dd919 YL |
435 | static unsigned long __init get_mpc_size(unsigned long physptr) |
436 | { | |
437 | struct mpc_table *mpc; | |
438 | unsigned long size; | |
439 | ||
f7750a79 | 440 | mpc = early_memremap(physptr, PAGE_SIZE); |
8d4dd919 | 441 | size = mpc->length; |
f7750a79 | 442 | early_memunmap(mpc, PAGE_SIZE); |
8d4dd919 YL |
443 | apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); |
444 | ||
445 | return size; | |
446 | } | |
447 | ||
0b3ba0c3 JSR |
448 | static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) |
449 | { | |
450 | struct mpc_table *mpc; | |
451 | unsigned long size; | |
452 | ||
453 | size = get_mpc_size(mpf->physptr); | |
f7750a79 | 454 | mpc = early_memremap(mpf->physptr, size); |
5997efb9 | 455 | |
0b3ba0c3 JSR |
456 | /* |
457 | * Read the physical hardware table. Anything here will | |
458 | * override the defaults. | |
459 | */ | |
460 | if (!smp_read_mpc(mpc, early)) { | |
461 | #ifdef CONFIG_X86_LOCAL_APIC | |
462 | smp_found_config = 0; | |
463 | #endif | |
b1bfd5ea JL |
464 | pr_err("BIOS bug, MP table errors detected!...\n"); |
465 | pr_cont("... disabling SMP support. (tell your hw vendor)\n"); | |
f7750a79 | 466 | early_memunmap(mpc, size); |
0b3ba0c3 JSR |
467 | return -1; |
468 | } | |
f7750a79 | 469 | early_memunmap(mpc, size); |
0b3ba0c3 JSR |
470 | |
471 | if (early) | |
472 | return -1; | |
473 | ||
474 | #ifdef CONFIG_X86_IO_APIC | |
475 | /* | |
476 | * If there are no explicit MP IRQ entries, then we are | |
477 | * broken. We set up most of the low 16 IO-APIC pins to | |
478 | * ISA defaults and hope it will work. | |
479 | */ | |
480 | if (!mp_irq_entries) { | |
481 | struct mpc_bus bus; | |
482 | ||
b1bfd5ea | 483 | pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); |
0b3ba0c3 JSR |
484 | |
485 | bus.type = MP_BUS; | |
486 | bus.busid = 0; | |
487 | memcpy(bus.bustype, "ISA ", 6); | |
488 | MP_bus_info(&bus); | |
489 | ||
490 | construct_default_ioirq_mptable(0); | |
491 | } | |
492 | #endif | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
1da177e4 LT |
497 | /* |
498 | * Scan the memory blocks for an SMP configuration block. | |
499 | */ | |
b3f1b617 | 500 | void __init default_get_smp_config(unsigned int early) |
1da177e4 | 501 | { |
5997efb9 | 502 | struct mpf_intel *mpf; |
1da177e4 | 503 | |
a91bf718 BH |
504 | if (!smp_found_config) |
505 | return; | |
506 | ||
5997efb9 | 507 | if (!mpf_base) |
69b88afa YL |
508 | return; |
509 | ||
888032cd AS |
510 | if (acpi_lapic && early) |
511 | return; | |
69b88afa | 512 | |
1da177e4 | 513 | /* |
69b88afa YL |
514 | * MPS doesn't support hyperthreading, aka only have |
515 | * thread 0 apic id in MPS table | |
1da177e4 | 516 | */ |
69b88afa | 517 | if (acpi_lapic && acpi_ioapic) |
1da177e4 | 518 | return; |
1da177e4 | 519 | |
5997efb9 TL |
520 | mpf = early_memremap(mpf_base, sizeof(*mpf)); |
521 | if (!mpf) { | |
522 | pr_err("MPTABLE: error mapping MP table\n"); | |
523 | return; | |
524 | } | |
525 | ||
b1bfd5ea JL |
526 | pr_info("Intel MultiProcessor Specification v1.%d\n", |
527 | mpf->specification); | |
b3e24164 | 528 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
1eb1b3b6 | 529 | if (mpf->feature2 & (1 << 7)) { |
b1bfd5ea | 530 | pr_info(" IMCR and PIC compatibility mode.\n"); |
1da177e4 LT |
531 | pic_mode = 1; |
532 | } else { | |
b1bfd5ea | 533 | pr_info(" Virtual Wire compatibility mode.\n"); |
1da177e4 LT |
534 | pic_mode = 0; |
535 | } | |
4421b1c8 | 536 | #endif |
1da177e4 LT |
537 | /* |
538 | * Now see if we need to read further. | |
539 | */ | |
5997efb9 | 540 | if (mpf->feature1) { |
888032cd AS |
541 | if (early) { |
542 | /* | |
543 | * local APIC has default address | |
544 | */ | |
545 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
546 | return; | |
547 | } | |
1da177e4 | 548 | |
b1bfd5ea | 549 | pr_info("Default MP configuration #%d\n", mpf->feature1); |
1eb1b3b6 | 550 | construct_default_ISA_mptable(mpf->feature1); |
1da177e4 | 551 | |
1eb1b3b6 | 552 | } else if (mpf->physptr) { |
5997efb9 TL |
553 | if (check_physptr(mpf, early)) { |
554 | early_memunmap(mpf, sizeof(*mpf)); | |
1da177e4 | 555 | return; |
5997efb9 | 556 | } |
1da177e4 LT |
557 | } else |
558 | BUG(); | |
559 | ||
888032cd | 560 | if (!early) |
b1bfd5ea | 561 | pr_info("Processors: %d\n", num_processors); |
1da177e4 LT |
562 | /* |
563 | * Only use the first configuration found. | |
564 | */ | |
5997efb9 TL |
565 | |
566 | early_memunmap(mpf, sizeof(*mpf)); | |
1da177e4 LT |
567 | } |
568 | ||
b24c2a92 | 569 | static void __init smp_reserve_memory(struct mpf_intel *mpf) |
a6830278 | 570 | { |
24aa0788 | 571 | memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); |
a6830278 JSR |
572 | } |
573 | ||
b24c2a92 | 574 | static int __init smp_scan_config(unsigned long base, unsigned long length) |
1da177e4 | 575 | { |
5997efb9 | 576 | unsigned int *bp; |
41401db6 | 577 | struct mpf_intel *mpf; |
5997efb9 | 578 | int ret = 0; |
1da177e4 | 579 | |
365811d6 BH |
580 | apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", |
581 | base, base + length - 1); | |
5d47a271 | 582 | BUILD_BUG_ON(sizeof(*mpf) != 16); |
1da177e4 LT |
583 | |
584 | while (length > 0) { | |
5997efb9 | 585 | bp = early_memremap(base, length); |
41401db6 | 586 | mpf = (struct mpf_intel *)bp; |
1da177e4 | 587 | if ((*bp == SMP_MAGIC_IDENT) && |
1eb1b3b6 | 588 | (mpf->length == 1) && |
4ef81297 | 589 | !mpf_checksum((unsigned char *)bp, 16) && |
1eb1b3b6 JSR |
590 | ((mpf->specification == 1) |
591 | || (mpf->specification == 4))) { | |
bab4b27c | 592 | #ifdef CONFIG_X86_LOCAL_APIC |
1da177e4 | 593 | smp_found_config = 1; |
bab4b27c | 594 | #endif |
5997efb9 | 595 | mpf_base = base; |
b1f006b6 | 596 | |
5997efb9 TL |
597 | pr_info("found SMP MP-table at [mem %#010lx-%#010lx] mapped at [%p]\n", |
598 | base, base + sizeof(*mpf) - 1, mpf); | |
b1f006b6 | 599 | |
5997efb9 | 600 | memblock_reserve(base, sizeof(*mpf)); |
a6830278 | 601 | if (mpf->physptr) |
b24c2a92 | 602 | smp_reserve_memory(mpf); |
1da177e4 | 603 | |
5997efb9 | 604 | ret = 1; |
1da177e4 | 605 | } |
5997efb9 TL |
606 | early_memunmap(bp, length); |
607 | ||
608 | if (ret) | |
609 | break; | |
610 | ||
611 | base += 16; | |
1da177e4 LT |
612 | length -= 16; |
613 | } | |
5997efb9 | 614 | return ret; |
1da177e4 LT |
615 | } |
616 | ||
b24c2a92 | 617 | void __init default_find_smp_config(void) |
1da177e4 LT |
618 | { |
619 | unsigned int address; | |
620 | ||
621 | /* | |
622 | * FIXME: Linux assumes you have 640K of base ram.. | |
623 | * this continues the error... | |
624 | * | |
625 | * 1) Scan the bottom 1K for a signature | |
626 | * 2) Scan the top 1K of base RAM | |
627 | * 3) Scan the 64K of bios | |
628 | */ | |
b24c2a92 YL |
629 | if (smp_scan_config(0x0, 0x400) || |
630 | smp_scan_config(639 * 0x400, 0x400) || | |
631 | smp_scan_config(0xF0000, 0x10000)) | |
1da177e4 LT |
632 | return; |
633 | /* | |
634 | * If it is an SMP machine we should know now, unless the | |
bb8187d3 | 635 | * configuration is in an EISA bus machine with an |
1da177e4 LT |
636 | * extended bios data area. |
637 | * | |
638 | * there is a real-mode segmented pointer pointing to the | |
639 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
640 | * | |
641 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
642 | * area, and as such this kind of SMP config may be less | |
643 | * trustworthy, simply because the SMP table may have been | |
644 | * stomped on during early boot. These loaders are buggy and | |
645 | * should be fixed. | |
646 | * | |
647 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
648 | */ | |
649 | ||
650 | address = get_bios_ebda(); | |
651 | if (address) | |
b24c2a92 | 652 | smp_scan_config(address, 0x400); |
888032cd AS |
653 | } |
654 | ||
2944e16b YL |
655 | #ifdef CONFIG_X86_IO_APIC |
656 | static u8 __initdata irq_used[MAX_IRQ_SOURCES]; | |
657 | ||
540d4e72 | 658 | static int __init get_MP_intsrc_index(struct mpc_intsrc *m) |
2944e16b YL |
659 | { |
660 | int i; | |
661 | ||
e253b396 | 662 | if (m->irqtype != mp_INT) |
2944e16b YL |
663 | return 0; |
664 | ||
e253b396 | 665 | if (m->irqflag != 0x0f) |
2944e16b YL |
666 | return 0; |
667 | ||
668 | /* not legacy */ | |
669 | ||
670 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 671 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
672 | continue; |
673 | ||
c2c21745 | 674 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
675 | continue; |
676 | ||
c2c21745 | 677 | if (mp_irqs[i].srcbus != m->srcbus) |
2944e16b | 678 | continue; |
c2c21745 | 679 | if (mp_irqs[i].srcbusirq != m->srcbusirq) |
2944e16b YL |
680 | continue; |
681 | if (irq_used[i]) { | |
682 | /* already claimed */ | |
683 | return -2; | |
684 | } | |
685 | irq_used[i] = 1; | |
686 | return i; | |
687 | } | |
688 | ||
689 | /* not found */ | |
690 | return -1; | |
691 | } | |
692 | ||
693 | #define SPARE_SLOT_NUM 20 | |
694 | ||
540d4e72 | 695 | static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM]; |
a6830278 | 696 | |
57592224 | 697 | static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) |
a6830278 JSR |
698 | { |
699 | int i; | |
700 | ||
701 | apic_printk(APIC_VERBOSE, "OLD "); | |
0e3fa13f | 702 | print_mp_irq_info(m); |
a6830278 JSR |
703 | |
704 | i = get_MP_intsrc_index(m); | |
705 | if (i > 0) { | |
0e3fa13f | 706 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
a6830278 JSR |
707 | apic_printk(APIC_VERBOSE, "NEW "); |
708 | print_mp_irq_info(&mp_irqs[i]); | |
709 | return; | |
710 | } | |
711 | if (!i) { | |
712 | /* legacy, do nothing */ | |
713 | return; | |
714 | } | |
715 | if (*nr_m_spare < SPARE_SLOT_NUM) { | |
716 | /* | |
717 | * not found (-1), or duplicated (-2) are invalid entries, | |
718 | * we need to use the slot later | |
719 | */ | |
720 | m_spare[*nr_m_spare] = m; | |
721 | *nr_m_spare += 1; | |
722 | } | |
723 | } | |
a6830278 | 724 | |
64d21fc1 | 725 | static int __init |
ee214558 | 726 | check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) |
a6830278 | 727 | { |
ee214558 YL |
728 | if (!mpc_new_phys || count <= mpc_new_length) { |
729 | WARN(1, "update_mptable: No spare slots (length: %x)\n", count); | |
730 | return -1; | |
a6830278 JSR |
731 | } |
732 | ||
9f1f1bfd | 733 | return 0; |
a6830278 | 734 | } |
cbb84c4c RM |
735 | #else /* CONFIG_X86_IO_APIC */ |
736 | static | |
737 | inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} | |
738 | #endif /* CONFIG_X86_IO_APIC */ | |
2944e16b | 739 | |
f29521e4 | 740 | static int __init replace_intsrc_all(struct mpc_table *mpc, |
2944e16b YL |
741 | unsigned long mpc_new_phys, |
742 | unsigned long mpc_new_length) | |
743 | { | |
744 | #ifdef CONFIG_X86_IO_APIC | |
745 | int i; | |
2944e16b | 746 | #endif |
2944e16b | 747 | int count = sizeof(*mpc); |
a6830278 | 748 | int nr_m_spare = 0; |
2944e16b YL |
749 | unsigned char *mpt = ((unsigned char *)mpc) + count; |
750 | ||
b1bfd5ea | 751 | pr_info("mpc_length %x\n", mpc->length); |
6c65da50 | 752 | while (count < mpc->length) { |
2944e16b YL |
753 | switch (*mpt) { |
754 | case MP_PROCESSOR: | |
a6830278 JSR |
755 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
756 | break; | |
2944e16b | 757 | case MP_BUS: |
a6830278 JSR |
758 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
759 | break; | |
2944e16b | 760 | case MP_IOAPIC: |
a6830278 JSR |
761 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
762 | break; | |
2944e16b | 763 | case MP_INTSRC: |
c58603e8 | 764 | check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare); |
a6830278 JSR |
765 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
766 | break; | |
2944e16b | 767 | case MP_LINTSRC: |
a6830278 JSR |
768 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
769 | break; | |
2944e16b YL |
770 | default: |
771 | /* wrong mptable */ | |
5a5737ea | 772 | smp_dump_mptable(mpc, mpt); |
2944e16b YL |
773 | goto out; |
774 | } | |
775 | } | |
776 | ||
777 | #ifdef CONFIG_X86_IO_APIC | |
778 | for (i = 0; i < mp_irq_entries; i++) { | |
779 | if (irq_used[i]) | |
780 | continue; | |
781 | ||
c2c21745 | 782 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
783 | continue; |
784 | ||
c2c21745 | 785 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
786 | continue; |
787 | ||
788 | if (nr_m_spare > 0) { | |
82034d6f | 789 | apic_printk(APIC_VERBOSE, "*NEW* found\n"); |
2944e16b | 790 | nr_m_spare--; |
0e3fa13f | 791 | memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); |
2944e16b YL |
792 | m_spare[nr_m_spare] = NULL; |
793 | } else { | |
540d4e72 JSR |
794 | struct mpc_intsrc *m = (struct mpc_intsrc *)mpt; |
795 | count += sizeof(struct mpc_intsrc); | |
ee214558 | 796 | if (check_slot(mpc_new_phys, mpc_new_length, count) < 0) |
a6830278 | 797 | goto out; |
0e3fa13f | 798 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
6c65da50 | 799 | mpc->length = count; |
540d4e72 | 800 | mpt += sizeof(struct mpc_intsrc); |
2944e16b YL |
801 | } |
802 | print_mp_irq_info(&mp_irqs[i]); | |
803 | } | |
804 | #endif | |
805 | out: | |
806 | /* update checksum */ | |
6c65da50 JSR |
807 | mpc->checksum = 0; |
808 | mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b YL |
809 | |
810 | return 0; | |
811 | } | |
812 | ||
f1bdb523 | 813 | int enable_update_mptable; |
fcfa146e | 814 | |
2944e16b YL |
815 | static int __init update_mptable_setup(char *str) |
816 | { | |
817 | enable_update_mptable = 1; | |
629e15d2 YL |
818 | #ifdef CONFIG_PCI |
819 | pci_routeirq = 1; | |
820 | #endif | |
2944e16b YL |
821 | return 0; |
822 | } | |
823 | early_param("update_mptable", update_mptable_setup); | |
824 | ||
825 | static unsigned long __initdata mpc_new_phys; | |
826 | static unsigned long mpc_new_length __initdata = 4096; | |
827 | ||
828 | /* alloc_mptable or alloc_mptable=4k */ | |
829 | static int __initdata alloc_mptable; | |
830 | static int __init parse_alloc_mptable_opt(char *p) | |
831 | { | |
832 | enable_update_mptable = 1; | |
629e15d2 YL |
833 | #ifdef CONFIG_PCI |
834 | pci_routeirq = 1; | |
835 | #endif | |
2944e16b YL |
836 | alloc_mptable = 1; |
837 | if (!p) | |
838 | return 0; | |
839 | mpc_new_length = memparse(p, &p); | |
840 | return 0; | |
841 | } | |
842 | early_param("alloc_mptable", parse_alloc_mptable_opt); | |
843 | ||
5da217ca | 844 | void __init e820__memblock_alloc_reserved_mpc_new(void) |
2944e16b | 845 | { |
ab5d140b | 846 | if (enable_update_mptable && alloc_mptable) |
5da217ca | 847 | mpc_new_phys = e820__memblock_alloc_reserved(mpc_new_length, 4); |
2944e16b YL |
848 | } |
849 | ||
850 | static int __init update_mp_table(void) | |
851 | { | |
852 | char str[16]; | |
853 | char oem[10]; | |
41401db6 | 854 | struct mpf_intel *mpf; |
f29521e4 | 855 | struct mpc_table *mpc, *mpc_new; |
5997efb9 | 856 | unsigned long size; |
2944e16b YL |
857 | |
858 | if (!enable_update_mptable) | |
859 | return 0; | |
860 | ||
5997efb9 TL |
861 | if (!mpf_base) |
862 | return 0; | |
863 | ||
864 | mpf = early_memremap(mpf_base, sizeof(*mpf)); | |
865 | if (!mpf) { | |
866 | pr_err("MPTABLE: mpf early_memremap() failed\n"); | |
2944e16b | 867 | return 0; |
5997efb9 | 868 | } |
2944e16b YL |
869 | |
870 | /* | |
871 | * Now see if we need to go further. | |
872 | */ | |
5997efb9 TL |
873 | if (mpf->feature1) |
874 | goto do_unmap_mpf; | |
2944e16b | 875 | |
1eb1b3b6 | 876 | if (!mpf->physptr) |
5997efb9 | 877 | goto do_unmap_mpf; |
2944e16b | 878 | |
5997efb9 TL |
879 | size = get_mpc_size(mpf->physptr); |
880 | mpc = early_memremap(mpf->physptr, size); | |
881 | if (!mpc) { | |
882 | pr_err("MPTABLE: mpc early_memremap() failed\n"); | |
883 | goto do_unmap_mpf; | |
884 | } | |
2944e16b YL |
885 | |
886 | if (!smp_check_mpc(mpc, oem, str)) | |
5997efb9 | 887 | goto do_unmap_mpc; |
2944e16b | 888 | |
5997efb9 | 889 | pr_info("mpf: %llx\n", (u64)mpf_base); |
b1bfd5ea | 890 | pr_info("physptr: %x\n", mpf->physptr); |
2944e16b | 891 | |
6c65da50 | 892 | if (mpc_new_phys && mpc->length > mpc_new_length) { |
2944e16b | 893 | mpc_new_phys = 0; |
b1bfd5ea JL |
894 | pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n", |
895 | mpc_new_length); | |
2944e16b YL |
896 | } |
897 | ||
898 | if (!mpc_new_phys) { | |
899 | unsigned char old, new; | |
0d2eb44f | 900 | /* check if we can change the position */ |
6c65da50 JSR |
901 | mpc->checksum = 0; |
902 | old = mpf_checksum((unsigned char *)mpc, mpc->length); | |
903 | mpc->checksum = 0xff; | |
904 | new = mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b | 905 | if (old == new) { |
b1bfd5ea | 906 | pr_info("mpc is readonly, please try alloc_mptable instead\n"); |
5997efb9 | 907 | goto do_unmap_mpc; |
2944e16b | 908 | } |
b1bfd5ea | 909 | pr_info("use in-position replacing\n"); |
2944e16b | 910 | } else { |
5997efb9 TL |
911 | mpc_new = early_memremap(mpc_new_phys, mpc_new_length); |
912 | if (!mpc_new) { | |
913 | pr_err("MPTABLE: new mpc early_memremap() failed\n"); | |
914 | goto do_unmap_mpc; | |
915 | } | |
1eb1b3b6 | 916 | mpf->physptr = mpc_new_phys; |
6c65da50 | 917 | memcpy(mpc_new, mpc, mpc->length); |
5997efb9 | 918 | early_memunmap(mpc, size); |
2944e16b | 919 | mpc = mpc_new; |
5997efb9 | 920 | size = mpc_new_length; |
2944e16b | 921 | /* check if we can modify that */ |
1eb1b3b6 | 922 | if (mpc_new_phys - mpf->physptr) { |
41401db6 | 923 | struct mpf_intel *mpf_new; |
2944e16b | 924 | /* steal 16 bytes from [0, 1k) */ |
5997efb9 TL |
925 | mpf_new = early_memremap(0x400 - 16, sizeof(*mpf_new)); |
926 | if (!mpf_new) { | |
927 | pr_err("MPTABLE: new mpf early_memremap() failed\n"); | |
928 | goto do_unmap_mpc; | |
929 | } | |
b1bfd5ea | 930 | pr_info("mpf new: %x\n", 0x400 - 16); |
2944e16b | 931 | memcpy(mpf_new, mpf, 16); |
5997efb9 | 932 | early_memunmap(mpf, sizeof(*mpf)); |
2944e16b | 933 | mpf = mpf_new; |
1eb1b3b6 | 934 | mpf->physptr = mpc_new_phys; |
2944e16b | 935 | } |
1eb1b3b6 JSR |
936 | mpf->checksum = 0; |
937 | mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16); | |
b1bfd5ea | 938 | pr_info("physptr new: %x\n", mpf->physptr); |
2944e16b YL |
939 | } |
940 | ||
941 | /* | |
942 | * only replace the one with mp_INT and | |
943 | * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, | |
944 | * already in mp_irqs , stored by ... and mp_config_acpi_gsi, | |
945 | * may need pci=routeirq for all coverage | |
946 | */ | |
947 | replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length); | |
948 | ||
5997efb9 TL |
949 | do_unmap_mpc: |
950 | early_memunmap(mpc, size); | |
951 | ||
952 | do_unmap_mpf: | |
953 | early_memunmap(mpf, sizeof(*mpf)); | |
954 | ||
2944e16b YL |
955 | return 0; |
956 | } | |
957 | ||
958 | late_initcall(update_mp_table); |