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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/acpi.h> | |
19 | #include <linux/delay.h> | |
1da177e4 | 20 | #include <linux/bootmem.h> |
1da177e4 LT |
21 | #include <linux/kernel_stat.h> |
22 | #include <linux/mc146818rtc.h> | |
23 | #include <linux/bitops.h> | |
24 | ||
25 | #include <asm/smp.h> | |
26 | #include <asm/acpi.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/mpspec.h> | |
29 | #include <asm/io_apic.h> | |
ce3fe6b2 | 30 | #include <asm/bios_ebda.h> |
1da177e4 LT |
31 | |
32 | #include <mach_apic.h> | |
874c4fe3 | 33 | #include <mach_apicdef.h> |
1da177e4 | 34 | #include <mach_mpparse.h> |
1da177e4 LT |
35 | |
36 | /* Have we found an MP table */ | |
37 | int smp_found_config; | |
4a5d107a | 38 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1da177e4 LT |
39 | |
40 | /* | |
41 | * Various Linux-internal data structures created from the | |
42 | * MP-table. | |
43 | */ | |
44 | int apic_version [MAX_APICS]; | |
c0a282c2 | 45 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
1da177e4 | 46 | int mp_bus_id_to_type [MAX_MP_BUSSES]; |
c0a282c2 | 47 | #endif |
a6333c3c | 48 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 LT |
49 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
50 | static int mp_current_pci_id; | |
51 | ||
52 | /* I/O APIC entries */ | |
53 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
54 | ||
55 | /* # of MP IRQ source entries */ | |
56 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
57 | ||
58 | /* MP IRQ source entries */ | |
59 | int mp_irq_entries; | |
60 | ||
61 | int nr_ioapics; | |
62 | ||
63 | int pic_mode; | |
64 | unsigned long mp_lapic_addr; | |
65 | ||
911a62d4 VP |
66 | unsigned int def_to_bigsmp = 0; |
67 | ||
1da177e4 LT |
68 | /* Processor that is doing the boot up */ |
69 | unsigned int boot_cpu_physical_apicid = -1U; | |
1da177e4 | 70 | /* Internal processor count */ |
87d7e980 | 71 | unsigned int num_processors; |
1da177e4 | 72 | |
7b1292e2 GC |
73 | unsigned disabled_cpus __cpuinitdata; |
74 | ||
1da177e4 LT |
75 | /* Bitmask of physically existing CPUs */ |
76 | physid_mask_t phys_cpu_present_map; | |
77 | ||
1161705b IM |
78 | #ifndef CONFIG_SMP |
79 | DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID; | |
80 | #endif | |
81 | ||
1da177e4 LT |
82 | /* |
83 | * Intel MP BIOS table parsing routines: | |
84 | */ | |
85 | ||
86 | ||
87 | /* | |
88 | * Checksum an MP configuration block. | |
89 | */ | |
90 | ||
91 | static int __init mpf_checksum(unsigned char *mp, int len) | |
92 | { | |
93 | int sum = 0; | |
94 | ||
95 | while (len--) | |
96 | sum += *mp++; | |
97 | ||
98 | return sum & 0xFF; | |
99 | } | |
100 | ||
86420506 | 101 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 LT |
102 | /* |
103 | * Have to match translation table entries to main table entries by counter | |
104 | * hence the mpc_record variable .... can't see a less disgusting way of | |
105 | * doing this .... | |
106 | */ | |
107 | ||
108 | static int mpc_record; | |
4a5d107a | 109 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata; |
86420506 | 110 | #endif |
1da177e4 | 111 | |
4a5d107a | 112 | static void __cpuinit MP_processor_info (struct mpc_config_processor *m) |
1da177e4 | 113 | { |
a6c422cc GOC |
114 | int ver, apicid, cpu; |
115 | cpumask_t tmp_map; | |
1299232b | 116 | physid_mask_t phys_cpu; |
1da177e4 | 117 | |
7b1292e2 GC |
118 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
119 | disabled_cpus++; | |
1da177e4 | 120 | return; |
7b1292e2 | 121 | } |
1da177e4 | 122 | |
4655c7de | 123 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 124 | apicid = mpc_apic_id(m, translation_table[mpc_record]); |
4655c7de AS |
125 | #else |
126 | Dprintk("Processor #%d %u:%u APIC version %d\n", | |
127 | m->mpc_apicid, | |
128 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, | |
129 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, | |
130 | m->mpc_apicver); | |
131 | apicid = m->mpc_apicid; | |
132 | #endif | |
1da177e4 LT |
133 | |
134 | if (m->mpc_featureflag&(1<<0)) | |
135 | Dprintk(" Floating point unit present.\n"); | |
136 | if (m->mpc_featureflag&(1<<7)) | |
137 | Dprintk(" Machine Exception supported.\n"); | |
138 | if (m->mpc_featureflag&(1<<8)) | |
139 | Dprintk(" 64 bit compare & exchange supported.\n"); | |
140 | if (m->mpc_featureflag&(1<<9)) | |
141 | Dprintk(" Internal APIC present.\n"); | |
142 | if (m->mpc_featureflag&(1<<11)) | |
143 | Dprintk(" SEP present.\n"); | |
144 | if (m->mpc_featureflag&(1<<12)) | |
145 | Dprintk(" MTRR present.\n"); | |
146 | if (m->mpc_featureflag&(1<<13)) | |
147 | Dprintk(" PGE present.\n"); | |
148 | if (m->mpc_featureflag&(1<<14)) | |
149 | Dprintk(" MCA present.\n"); | |
150 | if (m->mpc_featureflag&(1<<15)) | |
151 | Dprintk(" CMOV present.\n"); | |
152 | if (m->mpc_featureflag&(1<<16)) | |
153 | Dprintk(" PAT present.\n"); | |
154 | if (m->mpc_featureflag&(1<<17)) | |
155 | Dprintk(" PSE present.\n"); | |
156 | if (m->mpc_featureflag&(1<<18)) | |
157 | Dprintk(" PSN present.\n"); | |
158 | if (m->mpc_featureflag&(1<<19)) | |
159 | Dprintk(" Cache Line Flush Instruction present.\n"); | |
160 | /* 20 Reserved */ | |
161 | if (m->mpc_featureflag&(1<<21)) | |
162 | Dprintk(" Debug Trace and EMON Store present.\n"); | |
163 | if (m->mpc_featureflag&(1<<22)) | |
164 | Dprintk(" ACPI Thermal Throttle Registers present.\n"); | |
165 | if (m->mpc_featureflag&(1<<23)) | |
166 | Dprintk(" MMX present.\n"); | |
167 | if (m->mpc_featureflag&(1<<24)) | |
168 | Dprintk(" FXSR present.\n"); | |
169 | if (m->mpc_featureflag&(1<<25)) | |
170 | Dprintk(" XMM present.\n"); | |
171 | if (m->mpc_featureflag&(1<<26)) | |
172 | Dprintk(" Willamette New Instructions present.\n"); | |
173 | if (m->mpc_featureflag&(1<<27)) | |
174 | Dprintk(" Self Snoop present.\n"); | |
175 | if (m->mpc_featureflag&(1<<28)) | |
176 | Dprintk(" HT present.\n"); | |
177 | if (m->mpc_featureflag&(1<<29)) | |
178 | Dprintk(" Thermal Monitor present.\n"); | |
179 | /* 30, 31 Reserved */ | |
180 | ||
181 | ||
182 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { | |
183 | Dprintk(" Bootup CPU\n"); | |
184 | boot_cpu_physical_apicid = m->mpc_apicid; | |
1da177e4 LT |
185 | } |
186 | ||
1da177e4 LT |
187 | ver = m->mpc_apicver; |
188 | ||
1da177e4 LT |
189 | /* |
190 | * Validate version | |
191 | */ | |
192 | if (ver == 0x0) { | |
1299232b AM |
193 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " |
194 | "fixing up to 0x10. (tell your hw vendor)\n", | |
195 | m->mpc_apicid); | |
1da177e4 LT |
196 | ver = 0x10; |
197 | } | |
198 | apic_version[m->mpc_apicid] = ver; | |
6c180d94 EB |
199 | |
200 | phys_cpu = apicid_to_cpu_present(apicid); | |
201 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); | |
202 | ||
203 | if (num_processors >= NR_CPUS) { | |
204 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
205 | " Processor ignored.\n", NR_CPUS); | |
206 | return; | |
207 | } | |
208 | ||
209 | if (num_processors >= maxcpus) { | |
210 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
211 | " Processor ignored.\n", maxcpus); | |
212 | return; | |
213 | } | |
214 | ||
6c180d94 | 215 | num_processors++; |
a6c422cc GOC |
216 | cpus_complement(tmp_map, cpu_present_map); |
217 | cpu = first_cpu(tmp_map); | |
218 | ||
219 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) | |
220 | /* | |
221 | * x86_bios_cpu_apicid is required to have processors listed | |
222 | * in same order as logical cpu numbers. Hence the first | |
223 | * entry is BSP, and so on. | |
224 | */ | |
225 | cpu = 0; | |
6c180d94 | 226 | |
6cf272ac AR |
227 | /* |
228 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
229 | * but we need to work other dependencies like SMP_SUSPEND etc | |
230 | * before this can be done without some confusion. | |
231 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
232 | * - Ashok Raj <ashok.raj@intel.com> | |
233 | */ | |
234 | if (num_processors > 8) { | |
e72c8585 AR |
235 | switch (boot_cpu_data.x86_vendor) { |
236 | case X86_VENDOR_INTEL: | |
237 | if (!APIC_XAPIC(ver)) { | |
238 | def_to_bigsmp = 0; | |
239 | break; | |
240 | } | |
241 | /* If P4 and above fall through */ | |
242 | case X86_VENDOR_AMD: | |
243 | def_to_bigsmp = 1; | |
244 | } | |
245 | } | |
1161705b | 246 | #ifdef CONFIG_SMP |
73bf102b GOC |
247 | /* are we being called early in kernel startup? */ |
248 | if (x86_cpu_to_apicid_early_ptr) { | |
a6c422cc | 249 | u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr; |
73bf102b | 250 | u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr; |
a6c422cc GOC |
251 | |
252 | cpu_to_apicid[cpu] = m->mpc_apicid; | |
89bda4fc | 253 | bios_cpu_apicid[cpu] = m->mpc_apicid; |
73bf102b | 254 | } else { |
a6c422cc | 255 | per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid; |
73bf102b GOC |
256 | per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid; |
257 | } | |
1161705b | 258 | #endif |
89bda4fc | 259 | cpu_set(cpu, cpu_possible_map); |
a6c422cc | 260 | cpu_set(cpu, cpu_present_map); |
1da177e4 LT |
261 | } |
262 | ||
263 | static void __init MP_bus_info (struct mpc_config_bus *m) | |
264 | { | |
265 | char str[7]; | |
266 | ||
267 | memcpy(str, m->mpc_bustype, 6); | |
268 | str[6] = 0; | |
269 | ||
0ec153af | 270 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 271 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); |
0ec153af AS |
272 | #else |
273 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
274 | #endif | |
1da177e4 | 275 | |
5e4edbb7 | 276 | #if MAX_MP_BUSSES < 256 |
c0ec31ad RD |
277 | if (m->mpc_busid >= MAX_MP_BUSSES) { |
278 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " | |
279 | " is too large, max. supported is %d\n", | |
280 | m->mpc_busid, str, MAX_MP_BUSSES - 1); | |
281 | return; | |
282 | } | |
5e4edbb7 | 283 | #endif |
c0ec31ad | 284 | |
a6333c3c | 285 | set_bit(m->mpc_busid, mp_bus_not_pci); |
9e0a2de2 | 286 | if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) { |
d285e338 | 287 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 288 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
d285e338 | 289 | #endif |
a6333c3c | 290 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
291 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
292 | mp_current_pci_id++; | |
c0a282c2 AS |
293 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) |
294 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; | |
9e0a2de2 AS |
295 | } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) { |
296 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; | |
297 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) { | |
298 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; | |
1da177e4 LT |
299 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) { |
300 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; | |
1da177e4 LT |
301 | } else { |
302 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); | |
c0a282c2 | 303 | #endif |
1da177e4 LT |
304 | } |
305 | } | |
306 | ||
857033a6 AS |
307 | static int bad_ioapic(unsigned long address) |
308 | { | |
309 | if (nr_ioapics >= MAX_IO_APICS) { | |
310 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
311 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
312 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
313 | } | |
314 | if (!address) { | |
315 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
316 | " found in table, skipping!\n"); | |
317 | return 1; | |
318 | } | |
319 | return 0; | |
320 | } | |
321 | ||
1da177e4 LT |
322 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) |
323 | { | |
324 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
325 | return; | |
326 | ||
64883ab0 | 327 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", |
1da177e4 | 328 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
857033a6 AS |
329 | |
330 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 331 | return; |
857033a6 | 332 | |
1da177e4 LT |
333 | mp_ioapics[nr_ioapics] = *m; |
334 | nr_ioapics++; | |
335 | } | |
336 | ||
337 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) | |
338 | { | |
339 | mp_irqs [mp_irq_entries] = *m; | |
340 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," | |
341 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
342 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
343 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
344 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
345 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
346 | panic("Max # of irq sources exceeded!!\n"); | |
347 | } | |
348 | ||
349 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) | |
350 | { | |
351 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
352 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
353 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
354 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, | |
355 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
356 | } |
357 | ||
358 | #ifdef CONFIG_X86_NUMAQ | |
359 | static void __init MP_translation_info (struct mpc_config_translation *m) | |
360 | { | |
361 | printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local); | |
362 | ||
363 | if (mpc_record >= MAX_MPC_ENTRY) | |
364 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); | |
365 | else | |
366 | translation_table[mpc_record] = m; /* stash this for later */ | |
367 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) | |
368 | node_set_online(m->trans_quad); | |
369 | } | |
370 | ||
371 | /* | |
372 | * Read/parse the MPC oem tables | |
373 | */ | |
374 | ||
375 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \ | |
376 | unsigned short oemsize) | |
377 | { | |
378 | int count = sizeof (*oemtable); /* the header size */ | |
379 | unsigned char *oemptr = ((unsigned char *)oemtable)+count; | |
380 | ||
381 | mpc_record = 0; | |
382 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable); | |
383 | if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4)) | |
384 | { | |
385 | printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
386 | oemtable->oem_signature[0], | |
387 | oemtable->oem_signature[1], | |
388 | oemtable->oem_signature[2], | |
389 | oemtable->oem_signature[3]); | |
390 | return; | |
391 | } | |
392 | if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length)) | |
393 | { | |
394 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); | |
395 | return; | |
396 | } | |
397 | while (count < oemtable->oem_length) { | |
398 | switch (*oemptr) { | |
399 | case MP_TRANSLATION: | |
400 | { | |
401 | struct mpc_config_translation *m= | |
402 | (struct mpc_config_translation *)oemptr; | |
403 | MP_translation_info(m); | |
404 | oemptr += sizeof(*m); | |
405 | count += sizeof(*m); | |
406 | ++mpc_record; | |
407 | break; | |
408 | } | |
409 | default: | |
410 | { | |
411 | printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr); | |
412 | return; | |
413 | } | |
414 | } | |
415 | } | |
416 | } | |
417 | ||
418 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, | |
419 | char *productid) | |
420 | { | |
421 | if (strncmp(oem, "IBM NUMA", 8)) | |
422 | printk("Warning! May not be a NUMA-Q system!\n"); | |
423 | if (mpc->mpc_oemptr) | |
424 | smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr, | |
425 | mpc->mpc_oemsize); | |
426 | } | |
427 | #endif /* CONFIG_X86_NUMAQ */ | |
428 | ||
429 | /* | |
430 | * Read/parse the MPC | |
431 | */ | |
432 | ||
433 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
434 | { | |
435 | char str[16]; | |
436 | char oem[10]; | |
437 | int count=sizeof(*mpc); | |
438 | unsigned char *mpt=((unsigned char *)mpc)+count; | |
439 | ||
440 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { | |
441 | printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n", | |
442 | *(u32 *)mpc->mpc_signature); | |
443 | return 0; | |
444 | } | |
445 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { | |
446 | printk(KERN_ERR "SMP mptable: checksum error!\n"); | |
447 | return 0; | |
448 | } | |
449 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { | |
450 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", | |
451 | mpc->mpc_spec); | |
452 | return 0; | |
453 | } | |
454 | if (!mpc->mpc_lapic) { | |
455 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); | |
456 | return 0; | |
457 | } | |
458 | memcpy(oem,mpc->mpc_oem,8); | |
459 | oem[8]=0; | |
460 | printk(KERN_INFO "OEM ID: %s ",oem); | |
461 | ||
462 | memcpy(str,mpc->mpc_productid,12); | |
463 | str[12]=0; | |
464 | printk("Product ID: %s ",str); | |
465 | ||
466 | mps_oem_check(mpc, oem, str); | |
467 | ||
64883ab0 | 468 | printk("APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 | 469 | |
64883ab0 | 470 | /* |
1da177e4 LT |
471 | * Save the local APIC address (it might be non-default) -- but only |
472 | * if we're not using ACPI. | |
473 | */ | |
474 | if (!acpi_lapic) | |
475 | mp_lapic_addr = mpc->mpc_lapic; | |
476 | ||
477 | /* | |
478 | * Now process the configuration blocks. | |
479 | */ | |
86420506 | 480 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 481 | mpc_record = 0; |
86420506 | 482 | #endif |
1da177e4 LT |
483 | while (count < mpc->mpc_length) { |
484 | switch(*mpt) { | |
485 | case MP_PROCESSOR: | |
486 | { | |
487 | struct mpc_config_processor *m= | |
488 | (struct mpc_config_processor *)mpt; | |
489 | /* ACPI may have already provided this data */ | |
490 | if (!acpi_lapic) | |
491 | MP_processor_info(m); | |
492 | mpt += sizeof(*m); | |
493 | count += sizeof(*m); | |
494 | break; | |
495 | } | |
496 | case MP_BUS: | |
497 | { | |
498 | struct mpc_config_bus *m= | |
499 | (struct mpc_config_bus *)mpt; | |
500 | MP_bus_info(m); | |
501 | mpt += sizeof(*m); | |
502 | count += sizeof(*m); | |
503 | break; | |
504 | } | |
505 | case MP_IOAPIC: | |
506 | { | |
507 | struct mpc_config_ioapic *m= | |
508 | (struct mpc_config_ioapic *)mpt; | |
509 | MP_ioapic_info(m); | |
510 | mpt+=sizeof(*m); | |
511 | count+=sizeof(*m); | |
512 | break; | |
513 | } | |
514 | case MP_INTSRC: | |
515 | { | |
516 | struct mpc_config_intsrc *m= | |
517 | (struct mpc_config_intsrc *)mpt; | |
518 | ||
519 | MP_intsrc_info(m); | |
520 | mpt+=sizeof(*m); | |
521 | count+=sizeof(*m); | |
522 | break; | |
523 | } | |
524 | case MP_LINTSRC: | |
525 | { | |
526 | struct mpc_config_lintsrc *m= | |
527 | (struct mpc_config_lintsrc *)mpt; | |
528 | MP_lintsrc_info(m); | |
529 | mpt+=sizeof(*m); | |
530 | count+=sizeof(*m); | |
531 | break; | |
532 | } | |
533 | default: | |
534 | { | |
535 | count = mpc->mpc_length; | |
536 | break; | |
537 | } | |
538 | } | |
86420506 | 539 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 540 | ++mpc_record; |
86420506 | 541 | #endif |
1da177e4 | 542 | } |
3c43f039 | 543 | setup_apic_routing(); |
1da177e4 LT |
544 | if (!num_processors) |
545 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); | |
546 | return num_processors; | |
547 | } | |
548 | ||
549 | static int __init ELCR_trigger(unsigned int irq) | |
550 | { | |
551 | unsigned int port; | |
552 | ||
553 | port = 0x4d0 + (irq >> 3); | |
554 | return (inb(port) >> (irq & 7)) & 1; | |
555 | } | |
556 | ||
557 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
558 | { | |
559 | struct mpc_config_intsrc intsrc; | |
560 | int i; | |
561 | int ELCR_fallback = 0; | |
562 | ||
563 | intsrc.mpc_type = MP_INTSRC; | |
564 | intsrc.mpc_irqflag = 0; /* conforming */ | |
565 | intsrc.mpc_srcbus = 0; | |
566 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
567 | ||
568 | intsrc.mpc_irqtype = mp_INT; | |
569 | ||
570 | /* | |
571 | * If true, we have an ISA/PCI system with no IRQ entries | |
572 | * in the MP table. To prevent the PCI interrupts from being set up | |
573 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
574 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
575 | * never be level sensitive, so we simply see if the ELCR agrees. | |
576 | * If it does, we assume it's valid. | |
577 | */ | |
578 | if (mpc_default_type == 5) { | |
579 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
580 | ||
581 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) | |
582 | printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n"); | |
583 | else { | |
584 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); | |
585 | ELCR_fallback = 1; | |
586 | } | |
587 | } | |
588 | ||
589 | for (i = 0; i < 16; i++) { | |
590 | switch (mpc_default_type) { | |
591 | case 2: | |
592 | if (i == 0 || i == 13) | |
593 | continue; /* IRQ0 & IRQ13 not connected */ | |
594 | /* fall through */ | |
595 | default: | |
596 | if (i == 2) | |
597 | continue; /* IRQ2 is never connected */ | |
598 | } | |
599 | ||
600 | if (ELCR_fallback) { | |
601 | /* | |
602 | * If the ELCR indicates a level-sensitive interrupt, we | |
603 | * copy that information over to the MP table in the | |
604 | * irqflag field (level sensitive, active high polarity). | |
605 | */ | |
606 | if (ELCR_trigger(i)) | |
607 | intsrc.mpc_irqflag = 13; | |
608 | else | |
609 | intsrc.mpc_irqflag = 0; | |
610 | } | |
611 | ||
612 | intsrc.mpc_srcbusirq = i; | |
613 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
614 | MP_intsrc_info(&intsrc); | |
615 | } | |
616 | ||
617 | intsrc.mpc_irqtype = mp_ExtINT; | |
618 | intsrc.mpc_srcbusirq = 0; | |
619 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ | |
620 | MP_intsrc_info(&intsrc); | |
621 | } | |
622 | ||
623 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
624 | { | |
625 | struct mpc_config_processor processor; | |
626 | struct mpc_config_bus bus; | |
627 | struct mpc_config_ioapic ioapic; | |
628 | struct mpc_config_lintsrc lintsrc; | |
629 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
630 | int i; | |
631 | ||
632 | /* | |
633 | * local APIC has default address | |
634 | */ | |
635 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
636 | ||
637 | /* | |
638 | * 2 CPUs, numbered 0 & 1. | |
639 | */ | |
640 | processor.mpc_type = MP_PROCESSOR; | |
641 | /* Either an integrated APIC or a discrete 82489DX. */ | |
642 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
643 | processor.mpc_cpuflag = CPU_ENABLED; | |
644 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
645 | (boot_cpu_data.x86_model << 4) | | |
646 | boot_cpu_data.x86_mask; | |
647 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; | |
648 | processor.mpc_reserved[0] = 0; | |
649 | processor.mpc_reserved[1] = 0; | |
650 | for (i = 0; i < 2; i++) { | |
651 | processor.mpc_apicid = i; | |
652 | MP_processor_info(&processor); | |
653 | } | |
654 | ||
655 | bus.mpc_type = MP_BUS; | |
656 | bus.mpc_busid = 0; | |
657 | switch (mpc_default_type) { | |
658 | default: | |
659 | printk("???\n"); | |
660 | printk(KERN_ERR "Unknown standard configuration %d\n", | |
661 | mpc_default_type); | |
662 | /* fall through */ | |
663 | case 1: | |
664 | case 5: | |
665 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
666 | break; | |
667 | case 2: | |
668 | case 6: | |
669 | case 3: | |
670 | memcpy(bus.mpc_bustype, "EISA ", 6); | |
671 | break; | |
672 | case 4: | |
673 | case 7: | |
674 | memcpy(bus.mpc_bustype, "MCA ", 6); | |
675 | } | |
676 | MP_bus_info(&bus); | |
677 | if (mpc_default_type > 4) { | |
678 | bus.mpc_busid = 1; | |
679 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
680 | MP_bus_info(&bus); | |
681 | } | |
682 | ||
683 | ioapic.mpc_type = MP_IOAPIC; | |
684 | ioapic.mpc_apicid = 2; | |
685 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
686 | ioapic.mpc_flags = MPC_APIC_USABLE; | |
687 | ioapic.mpc_apicaddr = 0xFEC00000; | |
688 | MP_ioapic_info(&ioapic); | |
689 | ||
690 | /* | |
691 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
692 | */ | |
693 | construct_default_ioirq_mptable(mpc_default_type); | |
694 | ||
695 | lintsrc.mpc_type = MP_LINTSRC; | |
696 | lintsrc.mpc_irqflag = 0; /* conforming */ | |
697 | lintsrc.mpc_srcbusid = 0; | |
698 | lintsrc.mpc_srcbusirq = 0; | |
699 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
700 | for (i = 0; i < 2; i++) { | |
701 | lintsrc.mpc_irqtype = linttypes[i]; | |
702 | lintsrc.mpc_destapiclint = i; | |
703 | MP_lintsrc_info(&lintsrc); | |
704 | } | |
705 | } | |
706 | ||
707 | static struct intel_mp_floating *mpf_found; | |
708 | ||
709 | /* | |
710 | * Scan the memory blocks for an SMP configuration block. | |
711 | */ | |
712 | void __init get_smp_config (void) | |
713 | { | |
714 | struct intel_mp_floating *mpf = mpf_found; | |
715 | ||
716 | /* | |
1da177e4 LT |
717 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
718 | * processors, where MPS only supports physical. | |
719 | */ | |
720 | if (acpi_lapic && acpi_ioapic) { | |
721 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); | |
722 | return; | |
723 | } | |
724 | else if (acpi_lapic) | |
725 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); | |
726 | ||
727 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); | |
728 | if (mpf->mpf_feature2 & (1<<7)) { | |
729 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); | |
730 | pic_mode = 1; | |
731 | } else { | |
732 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); | |
733 | pic_mode = 0; | |
734 | } | |
735 | ||
736 | /* | |
737 | * Now see if we need to read further. | |
738 | */ | |
739 | if (mpf->mpf_feature1 != 0) { | |
740 | ||
741 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); | |
742 | construct_default_ISA_mptable(mpf->mpf_feature1); | |
743 | ||
744 | } else if (mpf->mpf_physptr) { | |
745 | ||
746 | /* | |
747 | * Read the physical hardware table. Anything here will | |
748 | * override the defaults. | |
749 | */ | |
7d4c8e56 | 750 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 LT |
751 | smp_found_config = 0; |
752 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); | |
753 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); | |
754 | return; | |
755 | } | |
756 | /* | |
757 | * If there are no explicit MP IRQ entries, then we are | |
758 | * broken. We set up most of the low 16 IO-APIC pins to | |
759 | * ISA defaults and hope it will work. | |
760 | */ | |
761 | if (!mp_irq_entries) { | |
762 | struct mpc_config_bus bus; | |
763 | ||
764 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
765 | ||
766 | bus.mpc_type = MP_BUS; | |
767 | bus.mpc_busid = 0; | |
768 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
769 | MP_bus_info(&bus); | |
770 | ||
771 | construct_default_ioirq_mptable(0); | |
772 | } | |
773 | ||
774 | } else | |
775 | BUG(); | |
776 | ||
777 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
778 | /* | |
779 | * Only use the first configuration found. | |
780 | */ | |
781 | } | |
782 | ||
783 | static int __init smp_scan_config (unsigned long base, unsigned long length) | |
784 | { | |
785 | unsigned long *bp = phys_to_virt(base); | |
786 | struct intel_mp_floating *mpf; | |
787 | ||
e91a3b43 | 788 | printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length); |
1da177e4 LT |
789 | if (sizeof(*mpf) != 16) |
790 | printk("Error: MPF size\n"); | |
791 | ||
792 | while (length > 0) { | |
793 | mpf = (struct intel_mp_floating *)bp; | |
794 | if ((*bp == SMP_MAGIC_IDENT) && | |
795 | (mpf->mpf_length == 1) && | |
796 | !mpf_checksum((unsigned char *)bp, 16) && | |
797 | ((mpf->mpf_specification == 1) | |
798 | || (mpf->mpf_specification == 4)) ) { | |
799 | ||
800 | smp_found_config = 1; | |
e91a3b43 IM |
801 | printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n", |
802 | mpf, virt_to_phys(mpf)); | |
72a7fe39 BW |
803 | reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE, |
804 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
805 | if (mpf->mpf_physptr) { |
806 | /* | |
807 | * We cannot access to MPC table to compute | |
808 | * table size yet, as only few megabytes from | |
809 | * the bottom is mapped now. | |
810 | * PC-9800's MPC table places on the very last | |
811 | * of physical memory; so that simply reserving | |
812 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() | |
813 | * in reserve_bootmem. | |
814 | */ | |
815 | unsigned long size = PAGE_SIZE; | |
816 | unsigned long end = max_low_pfn * PAGE_SIZE; | |
817 | if (mpf->mpf_physptr + size > end) | |
818 | size = end - mpf->mpf_physptr; | |
72a7fe39 BW |
819 | reserve_bootmem(mpf->mpf_physptr, size, |
820 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
821 | } |
822 | ||
823 | mpf_found = mpf; | |
824 | return 1; | |
825 | } | |
826 | bp += 4; | |
827 | length -= 16; | |
828 | } | |
829 | return 0; | |
830 | } | |
831 | ||
832 | void __init find_smp_config (void) | |
833 | { | |
834 | unsigned int address; | |
835 | ||
836 | /* | |
837 | * FIXME: Linux assumes you have 640K of base ram.. | |
838 | * this continues the error... | |
839 | * | |
840 | * 1) Scan the bottom 1K for a signature | |
841 | * 2) Scan the top 1K of base RAM | |
842 | * 3) Scan the 64K of bios | |
843 | */ | |
844 | if (smp_scan_config(0x0,0x400) || | |
845 | smp_scan_config(639*0x400,0x400) || | |
846 | smp_scan_config(0xF0000,0x10000)) | |
847 | return; | |
848 | /* | |
849 | * If it is an SMP machine we should know now, unless the | |
850 | * configuration is in an EISA/MCA bus machine with an | |
851 | * extended bios data area. | |
852 | * | |
853 | * there is a real-mode segmented pointer pointing to the | |
854 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
855 | * | |
856 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
857 | * area, and as such this kind of SMP config may be less | |
858 | * trustworthy, simply because the SMP table may have been | |
859 | * stomped on during early boot. These loaders are buggy and | |
860 | * should be fixed. | |
861 | * | |
862 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
863 | */ | |
864 | ||
865 | address = get_bios_ebda(); | |
866 | if (address) | |
867 | smp_scan_config(address, 0x400); | |
868 | } | |
869 | ||
870 | /* -------------------------------------------------------------------------- | |
871 | ACPI-based MP Configuration | |
872 | -------------------------------------------------------------------------- */ | |
873 | ||
888ba6c6 | 874 | #ifdef CONFIG_ACPI |
1da177e4 | 875 | |
19f03ffe | 876 | void __init mp_register_lapic_address(u64 address) |
1da177e4 LT |
877 | { |
878 | mp_lapic_addr = (unsigned long) address; | |
879 | ||
880 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); | |
881 | ||
882 | if (boot_cpu_physical_apicid == -1U) | |
883 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
884 | ||
885 | Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid); | |
886 | } | |
887 | ||
4a5d107a | 888 | void __cpuinit mp_register_lapic (u8 id, u8 enabled) |
1da177e4 LT |
889 | { |
890 | struct mpc_config_processor processor; | |
19f03ffe | 891 | int boot_cpu = 0; |
1da177e4 LT |
892 | |
893 | if (MAX_APICS - id <= 0) { | |
894 | printk(KERN_WARNING "Processor #%d invalid (max %d)\n", | |
895 | id, MAX_APICS); | |
896 | return; | |
897 | } | |
987dd2d4 AS |
898 | if (!enabled) { |
899 | ++disabled_cpus; | |
900 | return; | |
901 | } | |
1da177e4 LT |
902 | |
903 | if (id == boot_cpu_physical_apicid) | |
904 | boot_cpu = 1; | |
905 | ||
906 | processor.mpc_type = MP_PROCESSOR; | |
907 | processor.mpc_apicid = id; | |
908 | processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
909 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); | |
910 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); | |
911 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
912 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; | |
913 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; | |
914 | processor.mpc_reserved[0] = 0; | |
915 | processor.mpc_reserved[1] = 0; | |
916 | ||
917 | MP_processor_info(&processor); | |
918 | } | |
919 | ||
8466361a | 920 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
921 | |
922 | #define MP_ISA_BUS 0 | |
923 | #define MP_MAX_IOAPIC_PIN 127 | |
924 | ||
925 | static struct mp_ioapic_routing { | |
926 | int apic_id; | |
927 | int gsi_base; | |
928 | int gsi_end; | |
929 | u32 pin_programmed[4]; | |
930 | } mp_ioapic_routing[MAX_IO_APICS]; | |
931 | ||
19f03ffe | 932 | static int mp_find_ioapic (int gsi) |
1da177e4 | 933 | { |
19f03ffe | 934 | int i = 0; |
1da177e4 LT |
935 | |
936 | /* Find the IOAPIC that manages this GSI. */ | |
937 | for (i = 0; i < nr_ioapics; i++) { | |
938 | if ((gsi >= mp_ioapic_routing[i].gsi_base) | |
939 | && (gsi <= mp_ioapic_routing[i].gsi_end)) | |
940 | return i; | |
941 | } | |
942 | ||
943 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
944 | ||
945 | return -1; | |
946 | } | |
1da177e4 | 947 | |
e3e3ffa2 AS |
948 | static u8 uniq_ioapic_id(u8 id) |
949 | { | |
950 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
951 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
952 | return io_apic_get_unique_id(nr_ioapics, id); | |
953 | else | |
954 | return id; | |
955 | } | |
956 | ||
19f03ffe | 957 | void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) |
1da177e4 | 958 | { |
19f03ffe | 959 | int idx = 0; |
1da177e4 | 960 | |
857033a6 | 961 | if (bad_ioapic(address)) |
1da177e4 | 962 | return; |
1da177e4 | 963 | |
e3e3ffa2 | 964 | idx = nr_ioapics; |
1da177e4 LT |
965 | |
966 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
967 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
968 | mp_ioapics[idx].mpc_apicaddr = address; | |
969 | ||
970 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
e3e3ffa2 | 971 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
1da177e4 LT |
972 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
973 | ||
974 | /* | |
975 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
976 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
977 | */ | |
978 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
979 | mp_ioapic_routing[idx].gsi_base = gsi_base; | |
64883ab0 | 980 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
1da177e4 LT |
981 | io_apic_get_redir_entries(idx); |
982 | ||
64883ab0 TG |
983 | printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
984 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, | |
e3e3ffa2 AS |
985 | mp_ioapics[idx].mpc_apicver, |
986 | mp_ioapics[idx].mpc_apicaddr, | |
64883ab0 TG |
987 | mp_ioapic_routing[idx].gsi_base, |
988 | mp_ioapic_routing[idx].gsi_end); | |
e3e3ffa2 AS |
989 | |
990 | nr_ioapics++; | |
1da177e4 LT |
991 | } |
992 | ||
19f03ffe AK |
993 | void __init |
994 | mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) | |
1da177e4 LT |
995 | { |
996 | struct mpc_config_intsrc intsrc; | |
997 | int ioapic = -1; | |
998 | int pin = -1; | |
999 | ||
1000 | /* | |
1001 | * Convert 'gsi' to 'ioapic.pin'. | |
1002 | */ | |
1003 | ioapic = mp_find_ioapic(gsi); | |
1004 | if (ioapic < 0) | |
1005 | return; | |
1006 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
1007 | ||
1008 | /* | |
1009 | * TBD: This check is for faulty timer entries, where the override | |
1010 | * erroneously sets the trigger to level, resulting in a HUGE | |
1011 | * increase of timer interrupts! | |
1012 | */ | |
1013 | if ((bus_irq == 0) && (trigger == 3)) | |
1014 | trigger = 1; | |
1015 | ||
1016 | intsrc.mpc_type = MP_INTSRC; | |
1017 | intsrc.mpc_irqtype = mp_INT; | |
1018 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
1019 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
1020 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ | |
1021 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
1022 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1023 | ||
1024 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
1025 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
1026 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1027 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); | |
1028 | ||
1029 | mp_irqs[mp_irq_entries] = intsrc; | |
1030 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
1031 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
1032 | } |
1033 | ||
2df29726 AS |
1034 | int es7000_plat; |
1035 | ||
1da177e4 LT |
1036 | void __init mp_config_acpi_legacy_irqs (void) |
1037 | { | |
1038 | struct mpc_config_intsrc intsrc; | |
19f03ffe AK |
1039 | int i = 0; |
1040 | int ioapic = -1; | |
1da177e4 | 1041 | |
c0a282c2 | 1042 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
1da177e4 LT |
1043 | /* |
1044 | * Fabricate the legacy ISA bus (bus #31). | |
1045 | */ | |
1046 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; | |
c0a282c2 | 1047 | #endif |
a6333c3c | 1048 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
1049 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
1050 | ||
1051 | /* | |
1052 | * Older generations of ES7000 have no legacy identity mappings | |
1053 | */ | |
1054 | if (es7000_plat == 1) | |
1055 | return; | |
1056 | ||
1057 | /* | |
1058 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
1059 | */ | |
1060 | ioapic = mp_find_ioapic(0); | |
1061 | if (ioapic < 0) | |
1062 | return; | |
1063 | ||
1064 | intsrc.mpc_type = MP_INTSRC; | |
1065 | intsrc.mpc_irqflag = 0; /* Conforming */ | |
1066 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
1067 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
1068 | ||
1069 | /* | |
1070 | * Use the default configuration for the IRQs 0-15. Unless | |
27b46d76 | 1071 | * overridden by (MADT) interrupt source override entries. |
1da177e4 LT |
1072 | */ |
1073 | for (i = 0; i < 16; i++) { | |
1074 | int idx; | |
1075 | ||
1076 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
1077 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
1078 | ||
1079 | /* Do we already have a mapping for this ISA IRQ? */ | |
1080 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) | |
1081 | break; | |
1082 | ||
1083 | /* Do we already have a mapping for this IOAPIC pin */ | |
1084 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
1085 | (irq->mpc_dstirq == i)) | |
1086 | break; | |
1087 | } | |
1088 | ||
1089 | if (idx != mp_irq_entries) { | |
1090 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
1091 | continue; /* IRQ already used */ | |
1092 | } | |
1093 | ||
1094 | intsrc.mpc_irqtype = mp_INT; | |
1095 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ | |
1096 | intsrc.mpc_dstirq = i; | |
1097 | ||
1098 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
1099 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
1100 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1101 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1102 | intsrc.mpc_dstirq); | |
1103 | ||
1104 | mp_irqs[mp_irq_entries] = intsrc; | |
1105 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
1106 | panic("Max # of irq sources exceeded!\n"); | |
1107 | } | |
1108 | } | |
1109 | ||
c434b7a6 | 1110 | #define MAX_GSI_NUM 4096 |
2ba7deef | 1111 | #define IRQ_COMPRESSION_START 64 |
c434b7a6 | 1112 | |
19f03ffe | 1113 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 1114 | { |
19f03ffe AK |
1115 | int ioapic = -1; |
1116 | int ioapic_pin = 0; | |
1117 | int idx, bit = 0; | |
2ba7deef | 1118 | static int pci_irq = IRQ_COMPRESSION_START; |
c434b7a6 | 1119 | /* |
ab4a574e | 1120 | * Mapping between Global System Interrupts, which |
c434b7a6 NP |
1121 | * represent all possible interrupts, and IRQs |
1122 | * assigned to actual devices. | |
1123 | */ | |
1124 | static int gsi_to_irq[MAX_GSI_NUM]; | |
1da177e4 | 1125 | |
1da177e4 | 1126 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 1127 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 1128 | return gsi; |
1da177e4 LT |
1129 | |
1130 | ioapic = mp_find_ioapic(gsi); | |
1131 | if (ioapic < 0) { | |
1132 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
1133 | return gsi; | |
1134 | } | |
1135 | ||
1136 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
1137 | ||
1138 | if (ioapic_renumber_irq) | |
1139 | gsi = ioapic_renumber_irq(ioapic, gsi); | |
1140 | ||
1141 | /* | |
1142 | * Avoid pin reprogramming. PRTs typically include entries | |
1143 | * with redundant pin->gsi mappings (but unique PCI devices); | |
1144 | * we only program the IOAPIC on the first. | |
1145 | */ | |
1146 | bit = ioapic_pin % 32; | |
1147 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
1148 | if (idx > 3) { | |
1149 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
1150 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, | |
1151 | ioapic_pin); | |
1152 | return gsi; | |
1153 | } | |
1154 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { | |
1155 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", | |
1156 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
2ba7deef | 1157 | return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]); |
1da177e4 LT |
1158 | } |
1159 | ||
1160 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); | |
1161 | ||
2ba7deef LB |
1162 | /* |
1163 | * For GSI >= 64, use IRQ compression | |
1164 | */ | |
1165 | if ((gsi >= IRQ_COMPRESSION_START) | |
1166 | && (triggering == ACPI_LEVEL_SENSITIVE)) { | |
c434b7a6 NP |
1167 | /* |
1168 | * For PCI devices assign IRQs in order, avoiding gaps | |
1169 | * due to unused I/O APIC pins. | |
1170 | */ | |
1171 | int irq = gsi; | |
1172 | if (gsi < MAX_GSI_NUM) { | |
e0c1e9bf KM |
1173 | /* |
1174 | * Retain the VIA chipset work-around (gsi > 15), but | |
1175 | * avoid a problem where the 8254 timer (IRQ0) is setup | |
1176 | * via an override (so it's not on pin 0 of the ioapic), | |
1177 | * and at the same time, the pin 0 interrupt is a PCI | |
1178 | * type. The gsi > 15 test could cause these two pins | |
1179 | * to be shared as IRQ0, and they are not shareable. | |
1180 | * So test for this condition, and if necessary, avoid | |
1181 | * the pin collision. | |
1182 | */ | |
ede1389f | 1183 | gsi = pci_irq++; |
e1afc3f5 NP |
1184 | /* |
1185 | * Don't assign IRQ used by ACPI SCI | |
1186 | */ | |
cee324b1 | 1187 | if (gsi == acpi_gbl_FADT.sci_interrupt) |
e1afc3f5 | 1188 | gsi = pci_irq++; |
c434b7a6 NP |
1189 | gsi_to_irq[irq] = gsi; |
1190 | } else { | |
1191 | printk(KERN_ERR "GSI %u is too high\n", gsi); | |
1192 | return gsi; | |
1193 | } | |
1194 | } | |
1195 | ||
1da177e4 | 1196 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
cb654695 LB |
1197 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
1198 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
1199 | return gsi; |
1200 | } | |
1201 | ||
8466361a | 1202 | #endif /* CONFIG_X86_IO_APIC */ |
888ba6c6 | 1203 | #endif /* CONFIG_ACPI */ |