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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
1da177e4 LT |
32 | |
33 | /* Have we found an MP table */ | |
34 | int smp_found_config; | |
89b08200 | 35 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1da177e4 | 36 | |
1da177e4 LT |
37 | /* |
38 | * Various Linux-internal data structures created from the | |
39 | * MP-table. | |
40 | */ | |
55f05ffa | 41 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 | 42 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
1da177e4 LT |
43 | |
44 | static int mp_current_pci_id = 0; | |
45 | /* I/O APIC entries */ | |
46 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
47 | ||
48 | /* # of MP IRQ source entries */ | |
49 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
50 | ||
51 | /* MP IRQ source entries */ | |
52 | int mp_irq_entries; | |
53 | ||
54 | int nr_ioapics; | |
1da177e4 LT |
55 | unsigned long mp_lapic_addr = 0; |
56 | ||
57 | ||
58 | ||
59 | /* Processor that is doing the boot up */ | |
60 | unsigned int boot_cpu_id = -1U; | |
71b31233 MT |
61 | EXPORT_SYMBOL(boot_cpu_id); |
62 | ||
1da177e4 | 63 | /* Internal processor count */ |
87d7e980 | 64 | unsigned int num_processors; |
420f8f68 | 65 | |
43999d9e | 66 | unsigned disabled_cpus __cpuinitdata; |
1da177e4 LT |
67 | |
68 | /* Bitmask of physically existing CPUs */ | |
69 | physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE; | |
70 | ||
e8c10ef9 | 71 | u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata |
72 | = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
73 | void *x86_bios_cpu_apicid_early_ptr; | |
74 | DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID; | |
75 | EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
1da177e4 LT |
76 | |
77 | ||
78 | /* | |
79 | * Intel MP BIOS table parsing routines: | |
80 | */ | |
81 | ||
82 | /* | |
83 | * Checksum an MP configuration block. | |
84 | */ | |
85 | ||
86 | static int __init mpf_checksum(unsigned char *mp, int len) | |
87 | { | |
88 | int sum = 0; | |
89 | ||
90 | while (len--) | |
91 | sum += *mp++; | |
92 | ||
93 | return sum & 0xFF; | |
94 | } | |
95 | ||
71fff5e6 | 96 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
1da177e4 | 97 | { |
8893166f | 98 | int cpu; |
51f62e18 | 99 | cpumask_t tmp_map; |
f2c2cca3 | 100 | char *bootup_cpu = ""; |
1da177e4 | 101 | |
420f8f68 AK |
102 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
103 | disabled_cpus++; | |
1da177e4 | 104 | return; |
420f8f68 | 105 | } |
1da177e4 | 106 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
f2c2cca3 | 107 | bootup_cpu = " (Bootup-CPU)"; |
1da177e4 LT |
108 | boot_cpu_id = m->mpc_apicid; |
109 | } | |
f2c2cca3 AK |
110 | |
111 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
112 | ||
1da177e4 LT |
113 | if (num_processors >= NR_CPUS) { |
114 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
115 | " Processor ignored.\n", NR_CPUS); | |
116 | return; | |
117 | } | |
1da177e4 | 118 | |
89b08200 GC |
119 | if (num_processors >= maxcpus) { |
120 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
121 | " Processor ignored.\n", maxcpus); | |
122 | return; | |
123 | } | |
124 | ||
51f62e18 AR |
125 | num_processors++; |
126 | cpus_complement(tmp_map, cpu_present_map); | |
127 | cpu = first_cpu(tmp_map); | |
128 | ||
1da177e4 | 129 | physid_set(m->mpc_apicid, phys_cpu_present_map); |
18a2b647 AK |
130 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
131 | /* | |
693e3c56 | 132 | * x86_bios_cpu_apicid is required to have processors listed |
18a2b647 AK |
133 | * in same order as logical cpu numbers. Hence the first |
134 | * entry is BSP, and so on. | |
135 | */ | |
61b1b2d0 | 136 | cpu = 0; |
51f62e18 | 137 | } |
3b419089 | 138 | /* are we being called early in kernel startup? */ |
139 | if (x86_cpu_to_apicid_early_ptr) { | |
693e3c56 MT |
140 | u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr; |
141 | u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr; | |
e8c10ef9 | 142 | |
143 | cpu_to_apicid[cpu] = m->mpc_apicid; | |
144 | bios_cpu_apicid[cpu] = m->mpc_apicid; | |
71fff5e6 MT |
145 | } else { |
146 | per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid; | |
e8c10ef9 | 147 | per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid; |
71fff5e6 | 148 | } |
61b1b2d0 AK |
149 | |
150 | cpu_set(cpu, cpu_possible_map); | |
151 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
152 | } |
153 | ||
154 | static void __init MP_bus_info (struct mpc_config_bus *m) | |
155 | { | |
156 | char str[7]; | |
157 | ||
158 | memcpy(str, m->mpc_bustype, 6); | |
159 | str[6] = 0; | |
160 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
161 | ||
162 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 163 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 164 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 165 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
166 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
167 | mp_current_pci_id++; | |
1da177e4 LT |
168 | } else { |
169 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
170 | } | |
171 | } | |
172 | ||
013bf2c5 AK |
173 | static int bad_ioapic(unsigned long address) |
174 | { | |
175 | if (nr_ioapics >= MAX_IO_APICS) { | |
176 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
177 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
178 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
179 | } | |
180 | if (!address) { | |
181 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
182 | " found in table, skipping!\n"); | |
183 | return 1; | |
184 | } | |
185 | return 0; | |
186 | } | |
187 | ||
1da177e4 LT |
188 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) |
189 | { | |
190 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
191 | return; | |
192 | ||
f2c2cca3 AK |
193 | printk("I/O APIC #%d at 0x%X.\n", |
194 | m->mpc_apicid, m->mpc_apicaddr); | |
013bf2c5 AK |
195 | |
196 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 197 | return; |
013bf2c5 | 198 | |
1da177e4 LT |
199 | mp_ioapics[nr_ioapics] = *m; |
200 | nr_ioapics++; | |
201 | } | |
202 | ||
203 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) | |
204 | { | |
205 | mp_irqs [mp_irq_entries] = *m; | |
206 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," | |
207 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
208 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
209 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
210 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 211 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
212 | panic("Max # of irq sources exceeded!!\n"); |
213 | } | |
214 | ||
215 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) | |
216 | { | |
217 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
218 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
219 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
220 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, | |
221 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
222 | } |
223 | ||
224 | /* | |
225 | * Read/parse the MPC | |
226 | */ | |
227 | ||
228 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
229 | { | |
230 | char str[16]; | |
231 | int count=sizeof(*mpc); | |
232 | unsigned char *mpt=((unsigned char *)mpc)+count; | |
233 | ||
234 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { | |
aecc6361 | 235 | printk("MPTABLE: bad signature [%c%c%c%c]!\n", |
1da177e4 LT |
236 | mpc->mpc_signature[0], |
237 | mpc->mpc_signature[1], | |
238 | mpc->mpc_signature[2], | |
239 | mpc->mpc_signature[3]); | |
240 | return 0; | |
241 | } | |
242 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { | |
aecc6361 | 243 | printk("MPTABLE: checksum error!\n"); |
1da177e4 LT |
244 | return 0; |
245 | } | |
246 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { | |
aecc6361 | 247 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
1da177e4 LT |
248 | mpc->mpc_spec); |
249 | return 0; | |
250 | } | |
251 | if (!mpc->mpc_lapic) { | |
aecc6361 | 252 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
253 | return 0; |
254 | } | |
255 | memcpy(str,mpc->mpc_oem,8); | |
aecc6361 AK |
256 | str[8] = 0; |
257 | printk(KERN_INFO "MPTABLE: OEM ID: %s ",str); | |
1da177e4 LT |
258 | |
259 | memcpy(str,mpc->mpc_productid,12); | |
aecc6361 AK |
260 | str[12] = 0; |
261 | printk("MPTABLE: Product ID: %s ",str); | |
1da177e4 | 262 | |
aecc6361 | 263 | printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic); |
1da177e4 LT |
264 | |
265 | /* save the local APIC address, it might be non-default */ | |
266 | if (!acpi_lapic) | |
aecc6361 | 267 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 LT |
268 | |
269 | /* | |
270 | * Now process the configuration blocks. | |
271 | */ | |
272 | while (count < mpc->mpc_length) { | |
273 | switch(*mpt) { | |
274 | case MP_PROCESSOR: | |
275 | { | |
276 | struct mpc_config_processor *m= | |
277 | (struct mpc_config_processor *)mpt; | |
278 | if (!acpi_lapic) | |
aecc6361 | 279 | MP_processor_info(m); |
1da177e4 LT |
280 | mpt += sizeof(*m); |
281 | count += sizeof(*m); | |
282 | break; | |
283 | } | |
284 | case MP_BUS: | |
285 | { | |
286 | struct mpc_config_bus *m= | |
287 | (struct mpc_config_bus *)mpt; | |
288 | MP_bus_info(m); | |
289 | mpt += sizeof(*m); | |
290 | count += sizeof(*m); | |
291 | break; | |
292 | } | |
293 | case MP_IOAPIC: | |
294 | { | |
295 | struct mpc_config_ioapic *m= | |
296 | (struct mpc_config_ioapic *)mpt; | |
297 | MP_ioapic_info(m); | |
aecc6361 AK |
298 | mpt += sizeof(*m); |
299 | count += sizeof(*m); | |
1da177e4 LT |
300 | break; |
301 | } | |
302 | case MP_INTSRC: | |
303 | { | |
304 | struct mpc_config_intsrc *m= | |
305 | (struct mpc_config_intsrc *)mpt; | |
306 | ||
307 | MP_intsrc_info(m); | |
aecc6361 AK |
308 | mpt += sizeof(*m); |
309 | count += sizeof(*m); | |
1da177e4 LT |
310 | break; |
311 | } | |
312 | case MP_LINTSRC: | |
313 | { | |
314 | struct mpc_config_lintsrc *m= | |
315 | (struct mpc_config_lintsrc *)mpt; | |
316 | MP_lintsrc_info(m); | |
aecc6361 AK |
317 | mpt += sizeof(*m); |
318 | count += sizeof(*m); | |
1da177e4 LT |
319 | break; |
320 | } | |
321 | } | |
322 | } | |
3c43f039 | 323 | setup_apic_routing(); |
1da177e4 | 324 | if (!num_processors) |
aecc6361 | 325 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
326 | return num_processors; |
327 | } | |
328 | ||
329 | static int __init ELCR_trigger(unsigned int irq) | |
330 | { | |
331 | unsigned int port; | |
332 | ||
333 | port = 0x4d0 + (irq >> 3); | |
334 | return (inb(port) >> (irq & 7)) & 1; | |
335 | } | |
336 | ||
337 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
338 | { | |
339 | struct mpc_config_intsrc intsrc; | |
340 | int i; | |
341 | int ELCR_fallback = 0; | |
342 | ||
343 | intsrc.mpc_type = MP_INTSRC; | |
344 | intsrc.mpc_irqflag = 0; /* conforming */ | |
345 | intsrc.mpc_srcbus = 0; | |
346 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
347 | ||
348 | intsrc.mpc_irqtype = mp_INT; | |
349 | ||
350 | /* | |
351 | * If true, we have an ISA/PCI system with no IRQ entries | |
352 | * in the MP table. To prevent the PCI interrupts from being set up | |
353 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
354 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
355 | * never be level sensitive, so we simply see if the ELCR agrees. | |
356 | * If it does, we assume it's valid. | |
357 | */ | |
358 | if (mpc_default_type == 5) { | |
359 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
360 | ||
361 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) | |
362 | printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n"); | |
363 | else { | |
364 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); | |
365 | ELCR_fallback = 1; | |
366 | } | |
367 | } | |
368 | ||
369 | for (i = 0; i < 16; i++) { | |
370 | switch (mpc_default_type) { | |
371 | case 2: | |
372 | if (i == 0 || i == 13) | |
373 | continue; /* IRQ0 & IRQ13 not connected */ | |
374 | /* fall through */ | |
375 | default: | |
376 | if (i == 2) | |
377 | continue; /* IRQ2 is never connected */ | |
378 | } | |
379 | ||
380 | if (ELCR_fallback) { | |
381 | /* | |
382 | * If the ELCR indicates a level-sensitive interrupt, we | |
383 | * copy that information over to the MP table in the | |
384 | * irqflag field (level sensitive, active high polarity). | |
385 | */ | |
386 | if (ELCR_trigger(i)) | |
387 | intsrc.mpc_irqflag = 13; | |
388 | else | |
389 | intsrc.mpc_irqflag = 0; | |
390 | } | |
391 | ||
392 | intsrc.mpc_srcbusirq = i; | |
393 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
394 | MP_intsrc_info(&intsrc); | |
395 | } | |
396 | ||
397 | intsrc.mpc_irqtype = mp_ExtINT; | |
398 | intsrc.mpc_srcbusirq = 0; | |
399 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ | |
400 | MP_intsrc_info(&intsrc); | |
401 | } | |
402 | ||
403 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
404 | { | |
405 | struct mpc_config_processor processor; | |
406 | struct mpc_config_bus bus; | |
407 | struct mpc_config_ioapic ioapic; | |
408 | struct mpc_config_lintsrc lintsrc; | |
409 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
410 | int i; | |
411 | ||
412 | /* | |
413 | * local APIC has default address | |
414 | */ | |
415 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
416 | ||
417 | /* | |
418 | * 2 CPUs, numbered 0 & 1. | |
419 | */ | |
420 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 421 | processor.mpc_apicver = 0; |
1da177e4 | 422 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
423 | processor.mpc_cpufeature = 0; |
424 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
425 | processor.mpc_reserved[0] = 0; |
426 | processor.mpc_reserved[1] = 0; | |
427 | for (i = 0; i < 2; i++) { | |
428 | processor.mpc_apicid = i; | |
429 | MP_processor_info(&processor); | |
430 | } | |
431 | ||
432 | bus.mpc_type = MP_BUS; | |
433 | bus.mpc_busid = 0; | |
434 | switch (mpc_default_type) { | |
435 | default: | |
436 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
437 | mpc_default_type); | |
438 | /* fall through */ | |
439 | case 1: | |
440 | case 5: | |
441 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
442 | break; | |
1da177e4 LT |
443 | } |
444 | MP_bus_info(&bus); | |
445 | if (mpc_default_type > 4) { | |
446 | bus.mpc_busid = 1; | |
447 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
448 | MP_bus_info(&bus); | |
449 | } | |
450 | ||
451 | ioapic.mpc_type = MP_IOAPIC; | |
452 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 453 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
454 | ioapic.mpc_flags = MPC_APIC_USABLE; |
455 | ioapic.mpc_apicaddr = 0xFEC00000; | |
456 | MP_ioapic_info(&ioapic); | |
457 | ||
458 | /* | |
459 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
460 | */ | |
461 | construct_default_ioirq_mptable(mpc_default_type); | |
462 | ||
463 | lintsrc.mpc_type = MP_LINTSRC; | |
464 | lintsrc.mpc_irqflag = 0; /* conforming */ | |
465 | lintsrc.mpc_srcbusid = 0; | |
466 | lintsrc.mpc_srcbusirq = 0; | |
467 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
468 | for (i = 0; i < 2; i++) { | |
469 | lintsrc.mpc_irqtype = linttypes[i]; | |
470 | lintsrc.mpc_destapiclint = i; | |
471 | MP_lintsrc_info(&lintsrc); | |
472 | } | |
473 | } | |
474 | ||
475 | static struct intel_mp_floating *mpf_found; | |
476 | ||
477 | /* | |
478 | * Scan the memory blocks for an SMP configuration block. | |
479 | */ | |
480 | void __init get_smp_config (void) | |
481 | { | |
482 | struct intel_mp_floating *mpf = mpf_found; | |
483 | ||
484 | /* | |
1da177e4 LT |
485 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
486 | * processors, where MPS only supports physical. | |
487 | */ | |
488 | if (acpi_lapic && acpi_ioapic) { | |
489 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); | |
490 | return; | |
491 | } | |
492 | else if (acpi_lapic) | |
493 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); | |
494 | ||
495 | printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); | |
1da177e4 LT |
496 | |
497 | /* | |
498 | * Now see if we need to read further. | |
499 | */ | |
500 | if (mpf->mpf_feature1 != 0) { | |
501 | ||
502 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); | |
503 | construct_default_ISA_mptable(mpf->mpf_feature1); | |
504 | ||
505 | } else if (mpf->mpf_physptr) { | |
506 | ||
507 | /* | |
508 | * Read the physical hardware table. Anything here will | |
509 | * override the defaults. | |
510 | */ | |
f6c2e333 | 511 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 LT |
512 | smp_found_config = 0; |
513 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); | |
514 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); | |
515 | return; | |
516 | } | |
517 | /* | |
518 | * If there are no explicit MP IRQ entries, then we are | |
519 | * broken. We set up most of the low 16 IO-APIC pins to | |
520 | * ISA defaults and hope it will work. | |
521 | */ | |
522 | if (!mp_irq_entries) { | |
523 | struct mpc_config_bus bus; | |
524 | ||
525 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
526 | ||
527 | bus.mpc_type = MP_BUS; | |
528 | bus.mpc_busid = 0; | |
529 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
530 | MP_bus_info(&bus); | |
531 | ||
532 | construct_default_ioirq_mptable(0); | |
533 | } | |
534 | ||
535 | } else | |
536 | BUG(); | |
537 | ||
538 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
539 | /* | |
540 | * Only use the first configuration found. | |
541 | */ | |
542 | } | |
543 | ||
544 | static int __init smp_scan_config (unsigned long base, unsigned long length) | |
545 | { | |
546 | extern void __bad_mpf_size(void); | |
547 | unsigned int *bp = phys_to_virt(base); | |
548 | struct intel_mp_floating *mpf; | |
549 | ||
550 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); | |
551 | if (sizeof(*mpf) != 16) | |
552 | __bad_mpf_size(); | |
553 | ||
554 | while (length > 0) { | |
555 | mpf = (struct intel_mp_floating *)bp; | |
556 | if ((*bp == SMP_MAGIC_IDENT) && | |
557 | (mpf->mpf_length == 1) && | |
558 | !mpf_checksum((unsigned char *)bp, 16) && | |
559 | ((mpf->mpf_specification == 1) | |
560 | || (mpf->mpf_specification == 4)) ) { | |
561 | ||
562 | smp_found_config = 1; | |
563 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); | |
564 | if (mpf->mpf_physptr) | |
565 | reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE); | |
566 | mpf_found = mpf; | |
567 | return 1; | |
568 | } | |
569 | bp += 4; | |
570 | length -= 16; | |
571 | } | |
572 | return 0; | |
573 | } | |
574 | ||
a01fd3ba | 575 | void __init find_smp_config(void) |
1da177e4 LT |
576 | { |
577 | unsigned int address; | |
578 | ||
579 | /* | |
580 | * FIXME: Linux assumes you have 640K of base ram.. | |
581 | * this continues the error... | |
582 | * | |
583 | * 1) Scan the bottom 1K for a signature | |
584 | * 2) Scan the top 1K of base RAM | |
585 | * 3) Scan the 64K of bios | |
586 | */ | |
587 | if (smp_scan_config(0x0,0x400) || | |
588 | smp_scan_config(639*0x400,0x400) || | |
589 | smp_scan_config(0xF0000,0x10000)) | |
590 | return; | |
591 | /* | |
e5099134 | 592 | * If it is an SMP machine we should know now. |
1da177e4 LT |
593 | * |
594 | * there is a real-mode segmented pointer pointing to the | |
595 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
596 | * | |
597 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
598 | * area, and as such this kind of SMP config may be less | |
599 | * trustworthy, simply because the SMP table may have been | |
600 | * stomped on during early boot. These loaders are buggy and | |
601 | * should be fixed. | |
602 | */ | |
603 | ||
604 | address = *(unsigned short *)phys_to_virt(0x40E); | |
605 | address <<= 4; | |
606 | if (smp_scan_config(address, 0x1000)) | |
607 | return; | |
608 | ||
609 | /* If we have come this far, we did not find an MP table */ | |
610 | printk(KERN_INFO "No mptable found.\n"); | |
611 | } | |
612 | ||
1da177e4 LT |
613 | /* -------------------------------------------------------------------------- |
614 | ACPI-based MP Configuration | |
615 | -------------------------------------------------------------------------- */ | |
616 | ||
888ba6c6 | 617 | #ifdef CONFIG_ACPI |
1da177e4 | 618 | |
efec3b9a | 619 | void __init mp_register_lapic_address(u64 address) |
1da177e4 LT |
620 | { |
621 | mp_lapic_addr = (unsigned long) address; | |
1da177e4 | 622 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
1da177e4 LT |
623 | if (boot_cpu_id == -1U) |
624 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
625 | } |
626 | ||
efec3b9a | 627 | void __cpuinit mp_register_lapic (u8 id, u8 enabled) |
1da177e4 LT |
628 | { |
629 | struct mpc_config_processor processor; | |
630 | int boot_cpu = 0; | |
631 | ||
e4251e13 | 632 | if (id == boot_cpu_id) |
1da177e4 LT |
633 | boot_cpu = 1; |
634 | ||
635 | processor.mpc_type = MP_PROCESSOR; | |
636 | processor.mpc_apicid = id; | |
f2c2cca3 | 637 | processor.mpc_apicver = 0; |
1da177e4 LT |
638 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); |
639 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); | |
f2c2cca3 AK |
640 | processor.mpc_cpufeature = 0; |
641 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
642 | processor.mpc_reserved[0] = 0; |
643 | processor.mpc_reserved[1] = 0; | |
644 | ||
645 | MP_processor_info(&processor); | |
646 | } | |
647 | ||
1da177e4 LT |
648 | #define MP_ISA_BUS 0 |
649 | #define MP_MAX_IOAPIC_PIN 127 | |
650 | ||
651 | static struct mp_ioapic_routing { | |
652 | int apic_id; | |
653 | int gsi_start; | |
654 | int gsi_end; | |
655 | u32 pin_programmed[4]; | |
656 | } mp_ioapic_routing[MAX_IO_APICS]; | |
657 | ||
efec3b9a | 658 | static int mp_find_ioapic(int gsi) |
1da177e4 | 659 | { |
efec3b9a | 660 | int i = 0; |
1da177e4 LT |
661 | |
662 | /* Find the IOAPIC that manages this GSI. */ | |
663 | for (i = 0; i < nr_ioapics; i++) { | |
664 | if ((gsi >= mp_ioapic_routing[i].gsi_start) | |
665 | && (gsi <= mp_ioapic_routing[i].gsi_end)) | |
666 | return i; | |
667 | } | |
668 | ||
669 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
670 | return -1; |
671 | } | |
1da177e4 | 672 | |
78b599ae AK |
673 | static u8 uniq_ioapic_id(u8 id) |
674 | { | |
675 | int i; | |
676 | DECLARE_BITMAP(used, 256); | |
677 | bitmap_zero(used, 256); | |
678 | for (i = 0; i < nr_ioapics; i++) { | |
679 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
680 | __set_bit(ia->mpc_apicid, used); | |
681 | } | |
682 | if (!test_bit(id, used)) | |
683 | return id; | |
684 | return find_first_zero_bit(used, 256); | |
685 | } | |
686 | ||
efec3b9a | 687 | void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) |
1da177e4 | 688 | { |
efec3b9a | 689 | int idx = 0; |
1da177e4 | 690 | |
013bf2c5 | 691 | if (bad_ioapic(address)) |
1da177e4 | 692 | return; |
1da177e4 | 693 | |
78b599ae | 694 | idx = nr_ioapics; |
1da177e4 LT |
695 | |
696 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
697 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
698 | mp_ioapics[idx].mpc_apicaddr = address; | |
699 | ||
700 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 701 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 702 | mp_ioapics[idx].mpc_apicver = 0; |
1da177e4 LT |
703 | |
704 | /* | |
705 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
706 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
707 | */ | |
708 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
709 | mp_ioapic_routing[idx].gsi_start = gsi_base; | |
710 | mp_ioapic_routing[idx].gsi_end = gsi_base + | |
711 | io_apic_get_redir_entries(idx); | |
712 | ||
f2c2cca3 | 713 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
1da177e4 | 714 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
f2c2cca3 | 715 | mp_ioapics[idx].mpc_apicaddr, |
1da177e4 LT |
716 | mp_ioapic_routing[idx].gsi_start, |
717 | mp_ioapic_routing[idx].gsi_end); | |
78b599ae AK |
718 | |
719 | nr_ioapics++; | |
1da177e4 LT |
720 | } |
721 | ||
efec3b9a AK |
722 | void __init |
723 | mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) | |
1da177e4 LT |
724 | { |
725 | struct mpc_config_intsrc intsrc; | |
726 | int ioapic = -1; | |
727 | int pin = -1; | |
728 | ||
729 | /* | |
730 | * Convert 'gsi' to 'ioapic.pin'. | |
731 | */ | |
732 | ioapic = mp_find_ioapic(gsi); | |
733 | if (ioapic < 0) | |
734 | return; | |
735 | pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
736 | ||
737 | /* | |
738 | * TBD: This check is for faulty timer entries, where the override | |
739 | * erroneously sets the trigger to level, resulting in a HUGE | |
740 | * increase of timer interrupts! | |
741 | */ | |
742 | if ((bus_irq == 0) && (trigger == 3)) | |
743 | trigger = 1; | |
744 | ||
745 | intsrc.mpc_type = MP_INTSRC; | |
746 | intsrc.mpc_irqtype = mp_INT; | |
747 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
748 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
749 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ | |
750 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
751 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
752 | ||
753 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
754 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
755 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
756 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); | |
757 | ||
758 | mp_irqs[mp_irq_entries] = intsrc; | |
759 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
760 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
761 | } |
762 | ||
efec3b9a | 763 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
764 | { |
765 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
766 | int i = 0; |
767 | int ioapic = -1; | |
1da177e4 LT |
768 | |
769 | /* | |
770 | * Fabricate the legacy ISA bus (bus #31). | |
771 | */ | |
55f05ffa | 772 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
773 | |
774 | /* | |
775 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
776 | */ | |
777 | ioapic = mp_find_ioapic(0); | |
778 | if (ioapic < 0) | |
779 | return; | |
780 | ||
781 | intsrc.mpc_type = MP_INTSRC; | |
782 | intsrc.mpc_irqflag = 0; /* Conforming */ | |
783 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
784 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
785 | ||
786 | /* | |
787 | * Use the default configuration for the IRQs 0-15. Unless | |
788 | * overridden by (MADT) interrupt source override entries. | |
789 | */ | |
790 | for (i = 0; i < 16; i++) { | |
791 | int idx; | |
792 | ||
793 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
794 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
795 | ||
796 | /* Do we already have a mapping for this ISA IRQ? */ | |
797 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) | |
798 | break; | |
799 | ||
800 | /* Do we already have a mapping for this IOAPIC pin */ | |
801 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
802 | (irq->mpc_dstirq == i)) | |
803 | break; | |
804 | } | |
805 | ||
806 | if (idx != mp_irq_entries) { | |
807 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
808 | continue; /* IRQ already used */ | |
809 | } | |
810 | ||
811 | intsrc.mpc_irqtype = mp_INT; | |
812 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ | |
813 | intsrc.mpc_dstirq = i; | |
814 | ||
815 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
816 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
817 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
818 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
819 | intsrc.mpc_dstirq); | |
820 | ||
821 | mp_irqs[mp_irq_entries] = intsrc; | |
822 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
823 | panic("Max # of irq sources exceeded!\n"); | |
824 | } | |
1da177e4 LT |
825 | } |
826 | ||
50eca3eb | 827 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 828 | { |
efec3b9a AK |
829 | int ioapic = -1; |
830 | int ioapic_pin = 0; | |
831 | int idx, bit = 0; | |
1da177e4 LT |
832 | |
833 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
834 | return gsi; | |
835 | ||
1da177e4 | 836 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 837 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 838 | return gsi; |
1da177e4 LT |
839 | |
840 | ioapic = mp_find_ioapic(gsi); | |
841 | if (ioapic < 0) { | |
842 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
843 | return gsi; | |
844 | } | |
845 | ||
846 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
847 | ||
848 | /* | |
849 | * Avoid pin reprogramming. PRTs typically include entries | |
850 | * with redundant pin->gsi mappings (but unique PCI devices); | |
851 | * we only program the IOAPIC on the first. | |
852 | */ | |
853 | bit = ioapic_pin % 32; | |
854 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
855 | if (idx > 3) { | |
856 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
857 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, | |
858 | ioapic_pin); | |
859 | return gsi; | |
860 | } | |
861 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { | |
862 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", | |
863 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 864 | return gsi; |
1da177e4 LT |
865 | } |
866 | ||
867 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); | |
868 | ||
869 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
50eca3eb BM |
870 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
871 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
872 | return gsi; |
873 | } | |
888ba6c6 | 874 | #endif /*CONFIG_ACPI*/ |