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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
ce3fe6b2 | 32 | #include <asm/bios_ebda.h> |
1da177e4 | 33 | |
f6bc4029 GOC |
34 | #include <mach_apic.h> |
35 | ||
1da177e4 LT |
36 | /* Have we found an MP table */ |
37 | int smp_found_config; | |
1da177e4 | 38 | |
1da177e4 LT |
39 | /* |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
55f05ffa | 43 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
d2953315 | 44 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
45 | |
46 | static int mp_current_pci_id = 0; | |
47 | /* I/O APIC entries */ | |
48 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
49 | ||
50 | /* # of MP IRQ source entries */ | |
51 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
52 | ||
53 | /* MP IRQ source entries */ | |
54 | int mp_irq_entries; | |
55 | ||
56 | int nr_ioapics; | |
1da177e4 | 57 | |
7abb3cca | 58 | #ifdef CONFIG_SMP |
e8c10ef9 | 59 | u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata |
d2953315 | 60 | = {[0 ... NR_CPUS - 1] = BAD_APICID }; |
e8c10ef9 | 61 | void *x86_bios_cpu_apicid_early_ptr; |
7abb3cca | 62 | #endif |
e8c10ef9 | 63 | DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID; |
64 | EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
1da177e4 | 65 | |
e937fcf2 IM |
66 | /* Make it easy to share the UP and SMP code: */ |
67 | #ifndef CONFIG_X86_SMP | |
68 | unsigned int num_processors; | |
69 | unsigned disabled_cpus __cpuinitdata; | |
70 | #ifndef CONFIG_X86_LOCAL_APIC | |
71 | unsigned int boot_cpu_physical_apicid = -1U; | |
72 | #endif | |
73 | #endif | |
74 | ||
75 | /* Make it easy to share the UP and SMP code: */ | |
76 | #ifndef CONFIG_X86_SMP | |
77 | physid_mask_t phys_cpu_present_map; | |
78 | #endif | |
79 | ||
1da177e4 LT |
80 | /* |
81 | * Intel MP BIOS table parsing routines: | |
82 | */ | |
83 | ||
84 | /* | |
85 | * Checksum an MP configuration block. | |
86 | */ | |
87 | ||
88 | static int __init mpf_checksum(unsigned char *mp, int len) | |
89 | { | |
90 | int sum = 0; | |
91 | ||
92 | while (len--) | |
93 | sum += *mp++; | |
94 | ||
95 | return sum & 0xFF; | |
96 | } | |
97 | ||
0e01c00c AS |
98 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
99 | { | |
100 | char *bootup_cpu = ""; | |
101 | ||
102 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { | |
103 | disabled_cpus++; | |
104 | return; | |
105 | } | |
106 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { | |
107 | bootup_cpu = " (Bootup-CPU)"; | |
108 | boot_cpu_physical_apicid = m->mpc_apicid; | |
109 | } | |
110 | ||
111 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
112 | generic_processor_info(m->mpc_apicid, 0); | |
113 | } | |
114 | ||
d2953315 | 115 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
116 | { |
117 | char str[7]; | |
118 | ||
119 | memcpy(str, m->mpc_bustype, 6); | |
120 | str[6] = 0; | |
121 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
122 | ||
123 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 124 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 125 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 126 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
127 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
128 | mp_current_pci_id++; | |
1da177e4 LT |
129 | } else { |
130 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
131 | } | |
132 | } | |
133 | ||
013bf2c5 AK |
134 | static int bad_ioapic(unsigned long address) |
135 | { | |
136 | if (nr_ioapics >= MAX_IO_APICS) { | |
137 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
d2953315 | 138 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
013bf2c5 AK |
139 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
140 | } | |
141 | if (!address) { | |
142 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
d2953315 | 143 | " found in table, skipping!\n"); |
013bf2c5 AK |
144 | return 1; |
145 | } | |
146 | return 0; | |
147 | } | |
148 | ||
d2953315 | 149 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
150 | { |
151 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
152 | return; | |
153 | ||
d2953315 AS |
154 | printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid, |
155 | m->mpc_apicaddr); | |
013bf2c5 AK |
156 | |
157 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 158 | return; |
013bf2c5 | 159 | |
1da177e4 LT |
160 | mp_ioapics[nr_ioapics] = *m; |
161 | nr_ioapics++; | |
162 | } | |
163 | ||
d2953315 | 164 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 165 | { |
d2953315 | 166 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
167 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
168 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
d2953315 AS |
169 | m->mpc_irqtype, m->mpc_irqflag & 3, |
170 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
171 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 172 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
173 | panic("Max # of irq sources exceeded!!\n"); |
174 | } | |
175 | ||
d2953315 | 176 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
177 | { |
178 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
179 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
d2953315 AS |
180 | m->mpc_irqtype, m->mpc_irqflag & 3, |
181 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
182 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
183 | } |
184 | ||
185 | /* | |
186 | * Read/parse the MPC | |
187 | */ | |
8643f9d0 | 188 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
189 | { |
190 | char str[16]; | |
d2953315 AS |
191 | int count = sizeof(*mpc); |
192 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
193 | ||
194 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { | |
195 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", | |
196 | mpc->mpc_signature[0], | |
197 | mpc->mpc_signature[1], | |
198 | mpc->mpc_signature[2], mpc->mpc_signature[3]); | |
1da177e4 LT |
199 | return 0; |
200 | } | |
d2953315 AS |
201 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
202 | printk(KERN_ERR "MPTABLE: checksum error!\n"); | |
1da177e4 LT |
203 | return 0; |
204 | } | |
d2953315 | 205 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
aecc6361 | 206 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
d2953315 | 207 | mpc->mpc_spec); |
1da177e4 LT |
208 | return 0; |
209 | } | |
210 | if (!mpc->mpc_lapic) { | |
aecc6361 | 211 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
212 | return 0; |
213 | } | |
d2953315 | 214 | memcpy(str, mpc->mpc_oem, 8); |
aecc6361 | 215 | str[8] = 0; |
d2953315 | 216 | printk(KERN_INFO "MPTABLE: OEM ID: %s ", str); |
1da177e4 | 217 | |
d2953315 | 218 | memcpy(str, mpc->mpc_productid, 12); |
aecc6361 | 219 | str[12] = 0; |
d2953315 | 220 | printk(KERN_INFO "MPTABLE: Product ID: %s ", str); |
1da177e4 | 221 | |
d2953315 | 222 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 LT |
223 | |
224 | /* save the local APIC address, it might be non-default */ | |
225 | if (!acpi_lapic) | |
aecc6361 | 226 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 | 227 | |
8643f9d0 YL |
228 | if (early) |
229 | return 1; | |
230 | ||
1da177e4 | 231 | /* |
d2953315 | 232 | * Now process the configuration blocks. |
1da177e4 LT |
233 | */ |
234 | while (count < mpc->mpc_length) { | |
d2953315 AS |
235 | switch (*mpt) { |
236 | case MP_PROCESSOR: | |
1da177e4 | 237 | { |
d2953315 AS |
238 | struct mpc_config_processor *m = |
239 | (struct mpc_config_processor *)mpt; | |
1da177e4 | 240 | if (!acpi_lapic) |
aecc6361 | 241 | MP_processor_info(m); |
1da177e4 LT |
242 | mpt += sizeof(*m); |
243 | count += sizeof(*m); | |
244 | break; | |
245 | } | |
d2953315 | 246 | case MP_BUS: |
1da177e4 | 247 | { |
d2953315 AS |
248 | struct mpc_config_bus *m = |
249 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
250 | MP_bus_info(m); |
251 | mpt += sizeof(*m); | |
252 | count += sizeof(*m); | |
253 | break; | |
254 | } | |
d2953315 | 255 | case MP_IOAPIC: |
1da177e4 | 256 | { |
d2953315 AS |
257 | struct mpc_config_ioapic *m = |
258 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 259 | MP_ioapic_info(m); |
aecc6361 AK |
260 | mpt += sizeof(*m); |
261 | count += sizeof(*m); | |
1da177e4 LT |
262 | break; |
263 | } | |
d2953315 | 264 | case MP_INTSRC: |
1da177e4 | 265 | { |
d2953315 AS |
266 | struct mpc_config_intsrc *m = |
267 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
268 | |
269 | MP_intsrc_info(m); | |
aecc6361 AK |
270 | mpt += sizeof(*m); |
271 | count += sizeof(*m); | |
1da177e4 LT |
272 | break; |
273 | } | |
d2953315 | 274 | case MP_LINTSRC: |
1da177e4 | 275 | { |
d2953315 AS |
276 | struct mpc_config_lintsrc *m = |
277 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 278 | MP_lintsrc_info(m); |
aecc6361 AK |
279 | mpt += sizeof(*m); |
280 | count += sizeof(*m); | |
1da177e4 LT |
281 | break; |
282 | } | |
283 | } | |
284 | } | |
3c43f039 | 285 | setup_apic_routing(); |
1da177e4 | 286 | if (!num_processors) |
aecc6361 | 287 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
288 | return num_processors; |
289 | } | |
290 | ||
291 | static int __init ELCR_trigger(unsigned int irq) | |
292 | { | |
293 | unsigned int port; | |
294 | ||
295 | port = 0x4d0 + (irq >> 3); | |
296 | return (inb(port) >> (irq & 7)) & 1; | |
297 | } | |
298 | ||
299 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
300 | { | |
301 | struct mpc_config_intsrc intsrc; | |
302 | int i; | |
303 | int ELCR_fallback = 0; | |
304 | ||
305 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 306 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
307 | intsrc.mpc_srcbus = 0; |
308 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
309 | ||
310 | intsrc.mpc_irqtype = mp_INT; | |
311 | ||
312 | /* | |
313 | * If true, we have an ISA/PCI system with no IRQ entries | |
314 | * in the MP table. To prevent the PCI interrupts from being set up | |
315 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
316 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
317 | * never be level sensitive, so we simply see if the ELCR agrees. | |
318 | * If it does, we assume it's valid. | |
319 | */ | |
320 | if (mpc_default_type == 5) { | |
d2953315 AS |
321 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
322 | "falling back to ELCR\n"); | |
1da177e4 | 323 | |
d2953315 AS |
324 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
325 | ELCR_trigger(13)) | |
326 | printk(KERN_ERR "ELCR contains invalid data... " | |
327 | "not using ELCR\n"); | |
1da177e4 | 328 | else { |
d2953315 AS |
329 | printk(KERN_INFO |
330 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
331 | ELCR_fallback = 1; |
332 | } | |
333 | } | |
334 | ||
335 | for (i = 0; i < 16; i++) { | |
336 | switch (mpc_default_type) { | |
337 | case 2: | |
338 | if (i == 0 || i == 13) | |
339 | continue; /* IRQ0 & IRQ13 not connected */ | |
340 | /* fall through */ | |
341 | default: | |
342 | if (i == 2) | |
343 | continue; /* IRQ2 is never connected */ | |
344 | } | |
345 | ||
346 | if (ELCR_fallback) { | |
347 | /* | |
348 | * If the ELCR indicates a level-sensitive interrupt, we | |
349 | * copy that information over to the MP table in the | |
350 | * irqflag field (level sensitive, active high polarity). | |
351 | */ | |
352 | if (ELCR_trigger(i)) | |
353 | intsrc.mpc_irqflag = 13; | |
354 | else | |
355 | intsrc.mpc_irqflag = 0; | |
356 | } | |
357 | ||
358 | intsrc.mpc_srcbusirq = i; | |
d2953315 | 359 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
360 | MP_intsrc_info(&intsrc); |
361 | } | |
362 | ||
363 | intsrc.mpc_irqtype = mp_ExtINT; | |
364 | intsrc.mpc_srcbusirq = 0; | |
d2953315 | 365 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
366 | MP_intsrc_info(&intsrc); |
367 | } | |
368 | ||
369 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
370 | { | |
371 | struct mpc_config_processor processor; | |
372 | struct mpc_config_bus bus; | |
373 | struct mpc_config_ioapic ioapic; | |
374 | struct mpc_config_lintsrc lintsrc; | |
375 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
376 | int i; | |
377 | ||
378 | /* | |
379 | * local APIC has default address | |
380 | */ | |
381 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
382 | ||
383 | /* | |
384 | * 2 CPUs, numbered 0 & 1. | |
385 | */ | |
386 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 387 | processor.mpc_apicver = 0; |
1da177e4 | 388 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
389 | processor.mpc_cpufeature = 0; |
390 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
391 | processor.mpc_reserved[0] = 0; |
392 | processor.mpc_reserved[1] = 0; | |
393 | for (i = 0; i < 2; i++) { | |
394 | processor.mpc_apicid = i; | |
395 | MP_processor_info(&processor); | |
396 | } | |
397 | ||
398 | bus.mpc_type = MP_BUS; | |
399 | bus.mpc_busid = 0; | |
400 | switch (mpc_default_type) { | |
d2953315 AS |
401 | default: |
402 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
403 | mpc_default_type); | |
404 | /* fall through */ | |
405 | case 1: | |
406 | case 5: | |
407 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
408 | break; | |
1da177e4 LT |
409 | } |
410 | MP_bus_info(&bus); | |
411 | if (mpc_default_type > 4) { | |
412 | bus.mpc_busid = 1; | |
413 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
414 | MP_bus_info(&bus); | |
415 | } | |
416 | ||
417 | ioapic.mpc_type = MP_IOAPIC; | |
418 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 419 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
420 | ioapic.mpc_flags = MPC_APIC_USABLE; |
421 | ioapic.mpc_apicaddr = 0xFEC00000; | |
422 | MP_ioapic_info(&ioapic); | |
423 | ||
424 | /* | |
425 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
426 | */ | |
427 | construct_default_ioirq_mptable(mpc_default_type); | |
428 | ||
429 | lintsrc.mpc_type = MP_LINTSRC; | |
d2953315 | 430 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
431 | lintsrc.mpc_srcbusid = 0; |
432 | lintsrc.mpc_srcbusirq = 0; | |
433 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
434 | for (i = 0; i < 2; i++) { | |
435 | lintsrc.mpc_irqtype = linttypes[i]; | |
436 | lintsrc.mpc_destapiclint = i; | |
437 | MP_lintsrc_info(&lintsrc); | |
438 | } | |
439 | } | |
440 | ||
441 | static struct intel_mp_floating *mpf_found; | |
442 | ||
443 | /* | |
444 | * Scan the memory blocks for an SMP configuration block. | |
445 | */ | |
8643f9d0 | 446 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
447 | { |
448 | struct intel_mp_floating *mpf = mpf_found; | |
449 | ||
8643f9d0 YL |
450 | if (acpi_lapic && early) |
451 | return; | |
1da177e4 | 452 | /* |
8643f9d0 YL |
453 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
454 | * processors, where MPS only supports physical. | |
455 | */ | |
456 | if (acpi_lapic && acpi_ioapic) { | |
457 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " | |
d2953315 | 458 | "information\n"); |
8643f9d0 YL |
459 | return; |
460 | } else if (acpi_lapic) | |
461 | printk(KERN_INFO "Using ACPI for processor (LAPIC) " | |
d2953315 | 462 | "configuration information\n"); |
1da177e4 | 463 | |
8643f9d0 | 464 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
d2953315 | 465 | mpf->mpf_specification); |
1da177e4 LT |
466 | |
467 | /* | |
468 | * Now see if we need to read further. | |
469 | */ | |
470 | if (mpf->mpf_feature1 != 0) { | |
8643f9d0 YL |
471 | if (early) { |
472 | /* | |
473 | * local APIC has default address | |
474 | */ | |
475 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
476 | return; | |
477 | } | |
1da177e4 | 478 | |
d2953315 AS |
479 | printk(KERN_INFO "Default MP configuration #%d\n", |
480 | mpf->mpf_feature1); | |
1da177e4 LT |
481 | construct_default_ISA_mptable(mpf->mpf_feature1); |
482 | ||
483 | } else if (mpf->mpf_physptr) { | |
484 | ||
485 | /* | |
486 | * Read the physical hardware table. Anything here will | |
487 | * override the defaults. | |
488 | */ | |
8643f9d0 | 489 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 490 | smp_found_config = 0; |
d2953315 AS |
491 | printk(KERN_ERR |
492 | "BIOS bug, MP table errors detected!...\n"); | |
493 | printk(KERN_ERR "... disabling SMP support. " | |
494 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
495 | return; |
496 | } | |
8643f9d0 YL |
497 | |
498 | if (early) | |
499 | return; | |
1da177e4 LT |
500 | /* |
501 | * If there are no explicit MP IRQ entries, then we are | |
502 | * broken. We set up most of the low 16 IO-APIC pins to | |
503 | * ISA defaults and hope it will work. | |
504 | */ | |
505 | if (!mp_irq_entries) { | |
506 | struct mpc_config_bus bus; | |
507 | ||
d2953315 AS |
508 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " |
509 | "using default mptable. " | |
510 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
511 | |
512 | bus.mpc_type = MP_BUS; | |
513 | bus.mpc_busid = 0; | |
514 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
515 | MP_bus_info(&bus); | |
516 | ||
517 | construct_default_ioirq_mptable(0); | |
518 | } | |
519 | ||
520 | } else | |
521 | BUG(); | |
522 | ||
8643f9d0 YL |
523 | if (!early) |
524 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
525 | /* |
526 | * Only use the first configuration found. | |
527 | */ | |
528 | } | |
529 | ||
8643f9d0 YL |
530 | void __init early_get_smp_config(void) |
531 | { | |
532 | __get_smp_config(1); | |
533 | } | |
534 | ||
535 | void __init get_smp_config(void) | |
536 | { | |
537 | __get_smp_config(0); | |
538 | } | |
539 | ||
540 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
541 | unsigned reserve) | |
1da177e4 | 542 | { |
d2953315 | 543 | extern void __bad_mpf_size(void); |
1da177e4 LT |
544 | unsigned int *bp = phys_to_virt(base); |
545 | struct intel_mp_floating *mpf; | |
546 | ||
d2953315 | 547 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
548 | if (sizeof(*mpf) != 16) |
549 | __bad_mpf_size(); | |
550 | ||
551 | while (length > 0) { | |
552 | mpf = (struct intel_mp_floating *)bp; | |
553 | if ((*bp == SMP_MAGIC_IDENT) && | |
d2953315 AS |
554 | (mpf->mpf_length == 1) && |
555 | !mpf_checksum((unsigned char *)bp, 16) && | |
556 | ((mpf->mpf_specification == 1) | |
557 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
558 | |
559 | smp_found_config = 1; | |
8643f9d0 YL |
560 | mpf_found = mpf; |
561 | ||
562 | if (!reserve) | |
563 | return 1; | |
564 | ||
1da177e4 LT |
565 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); |
566 | if (mpf->mpf_physptr) | |
8643f9d0 YL |
567 | reserve_bootmem_generic(mpf->mpf_physptr, |
568 | PAGE_SIZE); | |
1da177e4 LT |
569 | return 1; |
570 | } | |
571 | bp += 4; | |
572 | length -= 16; | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | ||
8643f9d0 | 577 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
578 | { |
579 | unsigned int address; | |
580 | ||
581 | /* | |
582 | * FIXME: Linux assumes you have 640K of base ram.. | |
583 | * this continues the error... | |
584 | * | |
585 | * 1) Scan the bottom 1K for a signature | |
586 | * 2) Scan the top 1K of base RAM | |
587 | * 3) Scan the 64K of bios | |
588 | */ | |
8643f9d0 | 589 | if (smp_scan_config(0x0, 0x400, reserve) || |
d2953315 AS |
590 | smp_scan_config(639 * 0x400, 0x400, reserve) || |
591 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
592 | return; |
593 | /* | |
e5099134 | 594 | * If it is an SMP machine we should know now. |
1da177e4 LT |
595 | * |
596 | * there is a real-mode segmented pointer pointing to the | |
597 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
598 | * | |
599 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
600 | * area, and as such this kind of SMP config may be less | |
601 | * trustworthy, simply because the SMP table may have been | |
602 | * stomped on during early boot. These loaders are buggy and | |
603 | * should be fixed. | |
85e46035 AS |
604 | * |
605 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
1da177e4 LT |
606 | */ |
607 | ||
ce3fe6b2 AS |
608 | address = get_bios_ebda(); |
609 | if (address) | |
85e46035 | 610 | smp_scan_config(address, 0x400, reserve); |
1da177e4 LT |
611 | } |
612 | ||
8643f9d0 YL |
613 | void __init early_find_smp_config(void) |
614 | { | |
615 | __find_smp_config(0); | |
616 | } | |
617 | ||
618 | void __init find_smp_config(void) | |
619 | { | |
620 | __find_smp_config(1); | |
621 | } | |
622 | ||
1da177e4 LT |
623 | /* -------------------------------------------------------------------------- |
624 | ACPI-based MP Configuration | |
625 | -------------------------------------------------------------------------- */ | |
626 | ||
888ba6c6 | 627 | #ifdef CONFIG_ACPI |
1da177e4 | 628 | |
efec3b9a | 629 | void __init mp_register_lapic_address(u64 address) |
1da177e4 | 630 | { |
d2953315 | 631 | mp_lapic_addr = (unsigned long)address; |
1da177e4 | 632 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
c70dcb74 | 633 | if (boot_cpu_physical_apicid == -1U) |
05f2d12c | 634 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 | 635 | } |
a65d1d64 | 636 | void __cpuinit mp_register_lapic(int id, u8 enabled) |
1da177e4 | 637 | { |
8ccab29c AS |
638 | if (!enabled) { |
639 | ++disabled_cpus; | |
640 | return; | |
641 | } | |
1da177e4 | 642 | |
468e85b9 | 643 | generic_processor_info(id, 0); |
1da177e4 LT |
644 | } |
645 | ||
be8a5685 | 646 | |
1da177e4 LT |
647 | #define MP_ISA_BUS 0 |
648 | #define MP_MAX_IOAPIC_PIN 127 | |
649 | ||
650 | static struct mp_ioapic_routing { | |
d2953315 | 651 | int apic_id; |
555b0764 | 652 | int gsi_base; |
d2953315 AS |
653 | int gsi_end; |
654 | u32 pin_programmed[4]; | |
1da177e4 LT |
655 | } mp_ioapic_routing[MAX_IO_APICS]; |
656 | ||
efec3b9a | 657 | static int mp_find_ioapic(int gsi) |
1da177e4 | 658 | { |
efec3b9a | 659 | int i = 0; |
1da177e4 LT |
660 | |
661 | /* Find the IOAPIC that manages this GSI. */ | |
662 | for (i = 0; i < nr_ioapics; i++) { | |
555b0764 | 663 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
d2953315 | 664 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
665 | return i; |
666 | } | |
667 | ||
668 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
669 | return -1; |
670 | } | |
1da177e4 | 671 | |
78b599ae AK |
672 | static u8 uniq_ioapic_id(u8 id) |
673 | { | |
674 | int i; | |
675 | DECLARE_BITMAP(used, 256); | |
676 | bitmap_zero(used, 256); | |
677 | for (i = 0; i < nr_ioapics; i++) { | |
678 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
679 | __set_bit(ia->mpc_apicid, used); | |
680 | } | |
681 | if (!test_bit(id, used)) | |
682 | return id; | |
683 | return find_first_zero_bit(used, 256); | |
684 | } | |
685 | ||
a65d1d64 | 686 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 687 | { |
efec3b9a | 688 | int idx = 0; |
1da177e4 | 689 | |
013bf2c5 | 690 | if (bad_ioapic(address)) |
1da177e4 | 691 | return; |
1da177e4 | 692 | |
78b599ae | 693 | idx = nr_ioapics; |
1da177e4 LT |
694 | |
695 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
696 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
697 | mp_ioapics[idx].mpc_apicaddr = address; | |
698 | ||
699 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 700 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 701 | mp_ioapics[idx].mpc_apicver = 0; |
d2953315 | 702 | |
1da177e4 LT |
703 | /* |
704 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
705 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
706 | */ | |
707 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
555b0764 | 708 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
d2953315 AS |
709 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
710 | io_apic_get_redir_entries(idx); | |
1da177e4 | 711 | |
f2c2cca3 | 712 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
d2953315 AS |
713 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
714 | mp_ioapics[idx].mpc_apicaddr, | |
555b0764 | 715 | mp_ioapic_routing[idx].gsi_base, |
d2953315 | 716 | mp_ioapic_routing[idx].gsi_end); |
78b599ae AK |
717 | |
718 | nr_ioapics++; | |
1da177e4 LT |
719 | } |
720 | ||
d2953315 | 721 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
722 | { |
723 | struct mpc_config_intsrc intsrc; | |
d2953315 AS |
724 | int ioapic = -1; |
725 | int pin = -1; | |
1da177e4 LT |
726 | |
727 | /* | |
728 | * Convert 'gsi' to 'ioapic.pin'. | |
729 | */ | |
730 | ioapic = mp_find_ioapic(gsi); | |
731 | if (ioapic < 0) | |
732 | return; | |
555b0764 | 733 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
734 | |
735 | /* | |
736 | * TBD: This check is for faulty timer entries, where the override | |
737 | * erroneously sets the trigger to level, resulting in a HUGE | |
738 | * increase of timer interrupts! | |
739 | */ | |
740 | if ((bus_irq == 0) && (trigger == 3)) | |
741 | trigger = 1; | |
742 | ||
743 | intsrc.mpc_type = MP_INTSRC; | |
744 | intsrc.mpc_irqtype = mp_INT; | |
745 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
746 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
d2953315 AS |
747 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
748 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
749 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 | 750 | |
d2953315 AS |
751 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
752 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
753 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
754 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
755 | ||
756 | mp_irqs[mp_irq_entries] = intsrc; | |
757 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
758 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
759 | } |
760 | ||
efec3b9a | 761 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
762 | { |
763 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
764 | int i = 0; |
765 | int ioapic = -1; | |
1da177e4 LT |
766 | |
767 | /* | |
768 | * Fabricate the legacy ISA bus (bus #31). | |
769 | */ | |
55f05ffa | 770 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
771 | |
772 | /* | |
773 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
774 | */ | |
775 | ioapic = mp_find_ioapic(0); | |
776 | if (ioapic < 0) | |
777 | return; | |
778 | ||
779 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 780 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 LT |
781 | intsrc.mpc_srcbus = MP_ISA_BUS; |
782 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
783 | ||
784 | /* | |
785 | * Use the default configuration for the IRQs 0-15. Unless | |
786 | * overridden by (MADT) interrupt source override entries. | |
787 | */ | |
788 | for (i = 0; i < 16; i++) { | |
789 | int idx; | |
790 | ||
791 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
792 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
793 | ||
794 | /* Do we already have a mapping for this ISA IRQ? */ | |
d2953315 AS |
795 | if (irq->mpc_srcbus == MP_ISA_BUS |
796 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
797 | break; |
798 | ||
799 | /* Do we already have a mapping for this IOAPIC pin */ | |
800 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
d2953315 | 801 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
802 | break; |
803 | } | |
804 | ||
805 | if (idx != mp_irq_entries) { | |
806 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
d2953315 | 807 | continue; /* IRQ already used */ |
1da177e4 LT |
808 | } |
809 | ||
810 | intsrc.mpc_irqtype = mp_INT; | |
d2953315 | 811 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
812 | intsrc.mpc_dstirq = i; |
813 | ||
814 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
d2953315 AS |
815 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
816 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
817 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
818 | intsrc.mpc_dstirq); |
819 | ||
820 | mp_irqs[mp_irq_entries] = intsrc; | |
821 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
822 | panic("Max # of irq sources exceeded!\n"); | |
823 | } | |
1da177e4 LT |
824 | } |
825 | ||
50eca3eb | 826 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 827 | { |
efec3b9a AK |
828 | int ioapic = -1; |
829 | int ioapic_pin = 0; | |
830 | int idx, bit = 0; | |
1da177e4 LT |
831 | |
832 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
833 | return gsi; | |
834 | ||
1da177e4 | 835 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 836 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 837 | return gsi; |
1da177e4 LT |
838 | |
839 | ioapic = mp_find_ioapic(gsi); | |
840 | if (ioapic < 0) { | |
841 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
842 | return gsi; | |
843 | } | |
844 | ||
555b0764 | 845 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
846 | |
847 | /* | |
848 | * Avoid pin reprogramming. PRTs typically include entries | |
849 | * with redundant pin->gsi mappings (but unique PCI devices); | |
850 | * we only program the IOAPIC on the first. | |
851 | */ | |
852 | bit = ioapic_pin % 32; | |
853 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
854 | if (idx > 3) { | |
855 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
d2953315 AS |
856 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
857 | ioapic_pin); | |
1da177e4 LT |
858 | return gsi; |
859 | } | |
d2953315 | 860 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
861 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
862 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 863 | return gsi; |
1da177e4 LT |
864 | } |
865 | ||
d2953315 | 866 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 LT |
867 | |
868 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
d2953315 AS |
869 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
870 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
871 | return gsi; |
872 | } | |
d2953315 | 873 | #endif /* CONFIG_ACPI */ |