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Commit | Line | Data |
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2f485ef5 GOC |
1 | #include <asm/paravirt.h> |
2 | ||
3 | DEF_NATIVE(pv_irq_ops, irq_disable, "cli"); | |
4 | DEF_NATIVE(pv_irq_ops, irq_enable, "sti"); | |
5 | DEF_NATIVE(pv_irq_ops, restore_fl, "push %eax; popf"); | |
6 | DEF_NATIVE(pv_irq_ops, save_fl, "pushf; pop %eax"); | |
7 | DEF_NATIVE(pv_cpu_ops, iret, "iret"); | |
2f485ef5 GOC |
8 | DEF_NATIVE(pv_mmu_ops, read_cr2, "mov %cr2, %eax"); |
9 | DEF_NATIVE(pv_mmu_ops, write_cr3, "mov %eax, %cr3"); | |
10 | DEF_NATIVE(pv_mmu_ops, read_cr3, "mov %cr3, %eax"); | |
2f485ef5 | 11 | |
cfd8983f | 12 | #if defined(CONFIG_PARAVIRT_SPINLOCKS) |
f233f7f1 | 13 | DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%eax)"); |
3cded417 | 14 | DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %eax, %eax"); |
f233f7f1 PZI |
15 | #endif |
16 | ||
41edafdb JF |
17 | unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len) |
18 | { | |
19 | /* arg in %eax, return in %eax */ | |
20 | return 0; | |
21 | } | |
22 | ||
23 | unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len) | |
24 | { | |
25 | /* arg in %edx:%eax, return in %edx:%eax */ | |
26 | return 0; | |
27 | } | |
28 | ||
f233f7f1 | 29 | extern bool pv_is_native_spin_unlock(void); |
3cded417 | 30 | extern bool pv_is_native_vcpu_is_preempted(void); |
f233f7f1 | 31 | |
2f485ef5 GOC |
32 | unsigned native_patch(u8 type, u16 clobbers, void *ibuf, |
33 | unsigned long addr, unsigned len) | |
34 | { | |
35 | const unsigned char *start, *end; | |
36 | unsigned ret; | |
37 | ||
38 | #define PATCH_SITE(ops, x) \ | |
39 | case PARAVIRT_PATCH(ops.x): \ | |
40 | start = start_##ops##_##x; \ | |
41 | end = end_##ops##_##x; \ | |
42 | goto patch_site | |
d9336a9b | 43 | switch (type) { |
2f485ef5 GOC |
44 | PATCH_SITE(pv_irq_ops, irq_disable); |
45 | PATCH_SITE(pv_irq_ops, irq_enable); | |
46 | PATCH_SITE(pv_irq_ops, restore_fl); | |
47 | PATCH_SITE(pv_irq_ops, save_fl); | |
48 | PATCH_SITE(pv_cpu_ops, iret); | |
2f485ef5 GOC |
49 | PATCH_SITE(pv_mmu_ops, read_cr2); |
50 | PATCH_SITE(pv_mmu_ops, read_cr3); | |
51 | PATCH_SITE(pv_mmu_ops, write_cr3); | |
cfd8983f | 52 | #if defined(CONFIG_PARAVIRT_SPINLOCKS) |
f233f7f1 PZI |
53 | case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock): |
54 | if (pv_is_native_spin_unlock()) { | |
55 | start = start_pv_lock_ops_queued_spin_unlock; | |
56 | end = end_pv_lock_ops_queued_spin_unlock; | |
57 | goto patch_site; | |
58 | } | |
45dbea5f PZ |
59 | goto patch_default; |
60 | ||
3cded417 PZ |
61 | case PARAVIRT_PATCH(pv_lock_ops.vcpu_is_preempted): |
62 | if (pv_is_native_vcpu_is_preempted()) { | |
63 | start = start_pv_lock_ops_vcpu_is_preempted; | |
64 | end = end_pv_lock_ops_vcpu_is_preempted; | |
65 | goto patch_site; | |
66 | } | |
45dbea5f | 67 | goto patch_default; |
f233f7f1 | 68 | #endif |
2f485ef5 GOC |
69 | |
70 | default: | |
cef4402d | 71 | patch_default: __maybe_unused |
2f485ef5 GOC |
72 | ret = paravirt_patch_default(type, clobbers, ibuf, addr, len); |
73 | break; | |
f233f7f1 PZI |
74 | |
75 | patch_site: | |
76 | ret = paravirt_patch_insns(ibuf, len, start, end); | |
77 | break; | |
2f485ef5 GOC |
78 | } |
79 | #undef PATCH_SITE | |
80 | return ret; | |
81 | } |