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x86/pti: Do not enable PTI on CPUs which are not vulnerable to Meltdown
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / paravirt_patch_64.c
CommitLineData
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GOC
1#include <asm/paravirt.h>
2#include <asm/asm-offsets.h>
8a650ce2 3#include <linux/stringify.h>
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GOC
4
5DEF_NATIVE(pv_irq_ops, irq_disable, "cli");
6DEF_NATIVE(pv_irq_ops, irq_enable, "sti");
7DEF_NATIVE(pv_irq_ops, restore_fl, "pushq %rdi; popfq");
8DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax");
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GOC
9DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax");
10DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax");
11DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3");
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GOC
12DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd");
13
2be29982 14DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
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GOC
15DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
16
41edafdb
JF
17DEF_NATIVE(, mov32, "mov %edi, %eax");
18DEF_NATIVE(, mov64, "mov %rdi, %rax");
19
cfd8983f 20#if defined(CONFIG_PARAVIRT_SPINLOCKS)
f233f7f1 21DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%rdi)");
3cded417 22DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %rax, %rax");
f233f7f1
PZI
23#endif
24
41edafdb
JF
25unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len)
26{
27 return paravirt_patch_insns(insnbuf, len,
28 start__mov32, end__mov32);
29}
30
31unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len)
32{
33 return paravirt_patch_insns(insnbuf, len,
34 start__mov64, end__mov64);
35}
36
f233f7f1 37extern bool pv_is_native_spin_unlock(void);
3cded417 38extern bool pv_is_native_vcpu_is_preempted(void);
f233f7f1 39
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GOC
40unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
41 unsigned long addr, unsigned len)
42{
43 const unsigned char *start, *end;
44 unsigned ret;
45
46#define PATCH_SITE(ops, x) \
47 case PARAVIRT_PATCH(ops.x): \
48 start = start_##ops##_##x; \
49 end = end_##ops##_##x; \
50 goto patch_site
51 switch(type) {
52 PATCH_SITE(pv_irq_ops, restore_fl);
53 PATCH_SITE(pv_irq_ops, save_fl);
54 PATCH_SITE(pv_irq_ops, irq_enable);
55 PATCH_SITE(pv_irq_ops, irq_disable);
2be29982 56 PATCH_SITE(pv_cpu_ops, usergs_sysret64);
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GOC
57 PATCH_SITE(pv_cpu_ops, swapgs);
58 PATCH_SITE(pv_mmu_ops, read_cr2);
59 PATCH_SITE(pv_mmu_ops, read_cr3);
60 PATCH_SITE(pv_mmu_ops, write_cr3);
53fd13cf 61 PATCH_SITE(pv_cpu_ops, wbinvd);
cfd8983f 62#if defined(CONFIG_PARAVIRT_SPINLOCKS)
f233f7f1
PZI
63 case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock):
64 if (pv_is_native_spin_unlock()) {
65 start = start_pv_lock_ops_queued_spin_unlock;
66 end = end_pv_lock_ops_queued_spin_unlock;
67 goto patch_site;
68 }
45dbea5f
PZ
69 goto patch_default;
70
3cded417
PZ
71 case PARAVIRT_PATCH(pv_lock_ops.vcpu_is_preempted):
72 if (pv_is_native_vcpu_is_preempted()) {
73 start = start_pv_lock_ops_vcpu_is_preempted;
74 end = end_pv_lock_ops_vcpu_is_preempted;
75 goto patch_site;
76 }
45dbea5f 77 goto patch_default;
f233f7f1 78#endif
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79
80 default:
cef4402d 81patch_default: __maybe_unused
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82 ret = paravirt_patch_default(type, clobbers, ibuf, addr, len);
83 break;
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PZI
84
85patch_site:
86 ret = paravirt_patch_insns(ibuf, len, start, end);
87 break;
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GOC
88 }
89#undef PATCH_SITE
90 return ret;
91}