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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
c767a54b JP |
25 | #define pr_fmt(fmt) "Calgary: " fmt |
26 | ||
e465058d JM |
27 | #include <linux/kernel.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/string.h> | |
95b68dec | 34 | #include <linux/crash_dump.h> |
e465058d | 35 | #include <linux/dma-mapping.h> |
a66022c4 | 36 | #include <linux/bitmap.h> |
e465058d JM |
37 | #include <linux/pci_ids.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/delay.h> | |
8b87d9f4 | 40 | #include <linux/scatterlist.h> |
1b39b077 | 41 | #include <linux/iommu-helper.h> |
1956a96d | 42 | |
46a7fa27 | 43 | #include <asm/iommu.h> |
e465058d JM |
44 | #include <asm/calgary.h> |
45 | #include <asm/tce.h> | |
46 | #include <asm/pci-direct.h> | |
e465058d | 47 | #include <asm/dma.h> |
b34e90b8 | 48 | #include <asm/rio.h> |
ae5830a6 | 49 | #include <asm/bios_ebda.h> |
d7b9f7be | 50 | #include <asm/x86_init.h> |
d2aa232f | 51 | #include <asm/iommu_table.h> |
e465058d | 52 | |
8bd17c66 CH |
53 | #define CALGARY_MAPPING_ERROR 0 |
54 | ||
bff6547b MBY |
55 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
56 | int use_calgary __read_mostly = 1; | |
57 | #else | |
58 | int use_calgary __read_mostly = 0; | |
59 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
60 | ||
e465058d | 61 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 62 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 63 | |
e465058d | 64 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
65 | #define CALGARY_CONFIG_REG 0x0108 |
66 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
67 | #define PHB_PLSSR_OFFSET 0x0120 |
68 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
69 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
70 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
71 | #define PHB_MEM_1_LOW 0x0190 | |
72 | #define PHB_MEM_1_HIGH 0x01A0 | |
73 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
74 | #define PHB_MEM_1_SIZE 0x01C0 | |
75 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
76 | #define PHB_AER_OFFSET 0x0200 | |
77 | #define PHB_CONFIG_0_HIGH 0x0220 | |
78 | #define PHB_CONFIG_0_LOW 0x0230 | |
79 | #define PHB_CONFIG_0_END 0x0240 | |
80 | #define PHB_MEM_2_LOW 0x02B0 | |
81 | #define PHB_MEM_2_HIGH 0x02C0 | |
82 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
83 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
84 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
85 | ||
c3860108 | 86 | /* CalIOC2 specific */ |
8bcf7705 MBY |
87 | #define PHB_SAVIOR_L2 0x0DB0 |
88 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
89 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 90 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 91 | |
e465058d JM |
92 | /* PHB_CONFIG_RW */ |
93 | #define PHB_TCE_ENABLE 0x20000000 | |
94 | #define PHB_SLOT_DISABLE 0x1C000000 | |
95 | #define PHB_DAC_DISABLE 0x01000000 | |
96 | #define PHB_MEM2_ENABLE 0x00400000 | |
97 | #define PHB_MCSR_ENABLE 0x00100000 | |
98 | /* TAR (Table Address Register) */ | |
99 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
100 | #define TAR_VALID 0x0000000000000008UL | |
101 | /* CSR (Channel/DMA Status Register) */ | |
102 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 103 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 104 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 105 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
106 | #define PMR_SOFTSTOP 0x80000000 |
107 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
108 | #define PMR_HARDSTOP 0x20000000 | |
e465058d | 109 | |
499a00e9 DW |
110 | /* |
111 | * The maximum PHB bus number. | |
112 | * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384 | |
113 | * x3950M2: 4 chassis, 48 PHBs per chassis = 192 | |
114 | * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 | |
115 | * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 | |
116 | */ | |
d596043d | 117 | #define MAX_PHB_BUS_NUM 256 |
499a00e9 DW |
118 | |
119 | #define PHBS_PER_CALGARY 4 | |
e465058d JM |
120 | |
121 | /* register offsets in Calgary's internal register space */ | |
122 | static const unsigned long tar_offsets[] = { | |
123 | 0x0580 /* TAR0 */, | |
124 | 0x0588 /* TAR1 */, | |
125 | 0x0590 /* TAR2 */, | |
126 | 0x0598 /* TAR3 */ | |
127 | }; | |
128 | ||
129 | static const unsigned long split_queue_offsets[] = { | |
130 | 0x4870 /* SPLIT QUEUE 0 */, | |
131 | 0x5870 /* SPLIT QUEUE 1 */, | |
132 | 0x6870 /* SPLIT QUEUE 2 */, | |
133 | 0x7870 /* SPLIT QUEUE 3 */ | |
134 | }; | |
135 | ||
136 | static const unsigned long phb_offsets[] = { | |
137 | 0x8000 /* PHB0 */, | |
138 | 0x9000 /* PHB1 */, | |
139 | 0xA000 /* PHB2 */, | |
140 | 0xB000 /* PHB3 */ | |
141 | }; | |
142 | ||
b34e90b8 LV |
143 | /* PHB debug registers */ |
144 | ||
145 | static const unsigned long phb_debug_offsets[] = { | |
146 | 0x4000 /* PHB 0 DEBUG */, | |
147 | 0x5000 /* PHB 1 DEBUG */, | |
148 | 0x6000 /* PHB 2 DEBUG */, | |
149 | 0x7000 /* PHB 3 DEBUG */ | |
150 | }; | |
151 | ||
152 | /* | |
153 | * STUFF register for each debug PHB, | |
154 | * byte 1 = start bus number, byte 2 = end bus number | |
155 | */ | |
156 | ||
157 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
158 | ||
310adfdd MBY |
159 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
160 | ||
e465058d JM |
161 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
162 | static int translate_empty_slots __read_mostly = 0; | |
163 | static int calgary_detected __read_mostly = 0; | |
164 | ||
b34e90b8 LV |
165 | static struct rio_table_hdr *rio_table_hdr __initdata; |
166 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 167 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 168 | |
f38db651 MBY |
169 | struct calgary_bus_info { |
170 | void *tce_space; | |
0577f148 | 171 | unsigned char translation_disabled; |
f38db651 | 172 | signed char phbid; |
b34e90b8 | 173 | void __iomem *bbar; |
f38db651 MBY |
174 | }; |
175 | ||
ff297b8c MBY |
176 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
177 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 178 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 179 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 180 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 181 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
95b68dec C |
182 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl); |
183 | static void get_tce_space_from_tar(void); | |
ff297b8c | 184 | |
d6b56b0b | 185 | static const struct cal_chipset_ops calgary_chip_ops = { |
ff297b8c | 186 | .handle_quirks = calgary_handle_quirks, |
8cb32dc7 MBY |
187 | .tce_cache_blast = calgary_tce_cache_blast, |
188 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 189 | }; |
e465058d | 190 | |
d6b56b0b | 191 | static const struct cal_chipset_ops calioc2_chip_ops = { |
c3860108 | 192 | .handle_quirks = calioc2_handle_quirks, |
8cb32dc7 MBY |
193 | .tce_cache_blast = calioc2_tce_cache_blast, |
194 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
195 | }; |
196 | ||
ff297b8c | 197 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d | 198 | |
d588ba8c MBY |
199 | static inline int translation_enabled(struct iommu_table *tbl) |
200 | { | |
201 | /* only PHBs with translation enabled have an IOMMU table */ | |
202 | return (tbl != NULL); | |
203 | } | |
204 | ||
e465058d | 205 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 206 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
207 | { |
208 | unsigned long index; | |
209 | unsigned long end; | |
820a1497 | 210 | unsigned long flags; |
e465058d JM |
211 | |
212 | index = start_addr >> PAGE_SHIFT; | |
213 | ||
214 | /* bail out if we're asked to reserve a region we don't cover */ | |
215 | if (index >= tbl->it_size) | |
216 | return; | |
217 | ||
218 | end = index + npages; | |
219 | if (end > tbl->it_size) /* don't go off the table */ | |
220 | end = tbl->it_size; | |
221 | ||
820a1497 MBY |
222 | spin_lock_irqsave(&tbl->it_lock, flags); |
223 | ||
a66022c4 | 224 | bitmap_set(tbl->it_map, index, npages); |
820a1497 MBY |
225 | |
226 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
227 | } |
228 | ||
1b39b077 FT |
229 | static unsigned long iommu_range_alloc(struct device *dev, |
230 | struct iommu_table *tbl, | |
231 | unsigned int npages) | |
e465058d | 232 | { |
820a1497 | 233 | unsigned long flags; |
e465058d | 234 | unsigned long offset; |
1b39b077 FT |
235 | unsigned long boundary_size; |
236 | ||
237 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
238 | PAGE_SIZE) >> PAGE_SHIFT; | |
e465058d JM |
239 | |
240 | BUG_ON(npages == 0); | |
241 | ||
820a1497 MBY |
242 | spin_lock_irqsave(&tbl->it_lock, flags); |
243 | ||
1b39b077 FT |
244 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint, |
245 | npages, 0, boundary_size, 0); | |
e465058d | 246 | if (offset == ~0UL) { |
ff297b8c | 247 | tbl->chip_ops->tce_cache_blast(tbl); |
1b39b077 FT |
248 | |
249 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | |
250 | npages, 0, boundary_size, 0); | |
e465058d | 251 | if (offset == ~0UL) { |
c767a54b | 252 | pr_warn("IOMMU full\n"); |
820a1497 | 253 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
254 | if (panic_on_overflow) |
255 | panic("Calgary: fix the allocator.\n"); | |
256 | else | |
8bd17c66 | 257 | return CALGARY_MAPPING_ERROR; |
e465058d JM |
258 | } |
259 | } | |
260 | ||
e465058d JM |
261 | tbl->it_hint = offset + npages; |
262 | BUG_ON(tbl->it_hint > tbl->it_size); | |
263 | ||
820a1497 MBY |
264 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
265 | ||
e465058d JM |
266 | return offset; |
267 | } | |
268 | ||
1b39b077 FT |
269 | static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, |
270 | void *vaddr, unsigned int npages, int direction) | |
e465058d | 271 | { |
820a1497 | 272 | unsigned long entry; |
1f7564ca | 273 | dma_addr_t ret; |
e465058d | 274 | |
1b39b077 | 275 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d | 276 | |
8bd17c66 | 277 | if (unlikely(entry == CALGARY_MAPPING_ERROR)) { |
c767a54b JP |
278 | pr_warn("failed to allocate %u pages in iommu %p\n", |
279 | npages, tbl); | |
8bd17c66 | 280 | return CALGARY_MAPPING_ERROR; |
1f7564ca | 281 | } |
e465058d JM |
282 | |
283 | /* set the return dma address */ | |
284 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
285 | ||
286 | /* put the TCEs in the HW table */ | |
287 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
288 | direction); | |
e465058d | 289 | return ret; |
e465058d JM |
290 | } |
291 | ||
3cc39bda | 292 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
293 | unsigned int npages) |
294 | { | |
295 | unsigned long entry; | |
310adfdd | 296 | unsigned long badend; |
820a1497 | 297 | unsigned long flags; |
310adfdd MBY |
298 | |
299 | /* were we called with bad_dma_address? */ | |
8bd17c66 | 300 | badend = CALGARY_MAPPING_ERROR + (EMERGENCY_PAGES * PAGE_SIZE); |
68dee8e2 | 301 | if (unlikely(dma_addr < badend)) { |
bde78a79 | 302 | WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA " |
310adfdd | 303 | "address 0x%Lx\n", dma_addr); |
310adfdd MBY |
304 | return; |
305 | } | |
e465058d JM |
306 | |
307 | entry = dma_addr >> PAGE_SHIFT; | |
308 | ||
309 | BUG_ON(entry + npages > tbl->it_size); | |
310 | ||
311 | tce_free(tbl, entry, npages); | |
312 | ||
820a1497 MBY |
313 | spin_lock_irqsave(&tbl->it_lock, flags); |
314 | ||
a66022c4 | 315 | bitmap_clear(tbl->it_map, entry, npages); |
820a1497 MBY |
316 | |
317 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
318 | } |
319 | ||
35b6dfa0 MBY |
320 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
321 | { | |
8a244590 MBY |
322 | struct pci_dev *pdev; |
323 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
324 | struct iommu_table *tbl; |
325 | ||
8a244590 MBY |
326 | pdev = to_pci_dev(dev); |
327 | ||
4528752f | 328 | /* search up the device tree for an iommu */ |
f055a061 | 329 | pbus = pdev->bus; |
4528752f DW |
330 | do { |
331 | tbl = pci_iommu(pbus); | |
332 | if (tbl && tbl->it_busno == pbus->number) | |
333 | break; | |
334 | tbl = NULL; | |
f055a061 | 335 | pbus = pbus->parent; |
4528752f | 336 | } while (pbus); |
7354b075 | 337 | |
f055a061 | 338 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
339 | |
340 | return tbl; | |
341 | } | |
342 | ||
160c1d8e FT |
343 | static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, |
344 | int nelems,enum dma_data_direction dir, | |
00085f1e | 345 | unsigned long attrs) |
e465058d | 346 | { |
3cc39bda | 347 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
348 | struct scatterlist *s; |
349 | int i; | |
3cc39bda | 350 | |
bc3c6058 | 351 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
352 | return; |
353 | ||
8b87d9f4 | 354 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 355 | unsigned int npages; |
8b87d9f4 JA |
356 | dma_addr_t dma = s->dma_address; |
357 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
358 | |
359 | if (dmalen == 0) | |
360 | break; | |
361 | ||
036b4c50 | 362 | npages = iommu_num_pages(dma, dmalen, PAGE_SIZE); |
3cc39bda | 363 | iommu_free(tbl, dma, npages); |
e465058d JM |
364 | } |
365 | } | |
366 | ||
0b11e1c6 | 367 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
160c1d8e | 368 | int nelems, enum dma_data_direction dir, |
00085f1e | 369 | unsigned long attrs) |
e465058d | 370 | { |
35b6dfa0 | 371 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 372 | struct scatterlist *s; |
e465058d JM |
373 | unsigned long vaddr; |
374 | unsigned int npages; | |
375 | unsigned long entry; | |
376 | int i; | |
377 | ||
8b87d9f4 | 378 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 379 | BUG_ON(!sg_page(s)); |
e465058d | 380 | |
58b053e4 | 381 | vaddr = (unsigned long) sg_virt(s); |
036b4c50 | 382 | npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE); |
e465058d | 383 | |
1b39b077 | 384 | entry = iommu_range_alloc(dev, tbl, npages); |
8bd17c66 | 385 | if (entry == CALGARY_MAPPING_ERROR) { |
e465058d JM |
386 | /* makes sure unmap knows to stop */ |
387 | s->dma_length = 0; | |
388 | goto error; | |
389 | } | |
390 | ||
391 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
392 | ||
393 | /* insert into HW table */ | |
160c1d8e | 394 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir); |
e465058d JM |
395 | |
396 | s->dma_length = s->length; | |
397 | } | |
398 | ||
e465058d JM |
399 | return nelems; |
400 | error: | |
00085f1e | 401 | calgary_unmap_sg(dev, sg, nelems, dir, 0); |
8b87d9f4 | 402 | for_each_sg(sg, s, nelems, i) { |
8bd17c66 | 403 | sg->dma_address = CALGARY_MAPPING_ERROR; |
8b87d9f4 | 404 | sg->dma_length = 0; |
e465058d | 405 | } |
e465058d JM |
406 | return 0; |
407 | } | |
408 | ||
3991605c FT |
409 | static dma_addr_t calgary_map_page(struct device *dev, struct page *page, |
410 | unsigned long offset, size_t size, | |
411 | enum dma_data_direction dir, | |
00085f1e | 412 | unsigned long attrs) |
e465058d | 413 | { |
3991605c | 414 | void *vaddr = page_address(page) + offset; |
e465058d JM |
415 | unsigned long uaddr; |
416 | unsigned int npages; | |
35b6dfa0 | 417 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
418 | |
419 | uaddr = (unsigned long)vaddr; | |
036b4c50 | 420 | npages = iommu_num_pages(uaddr, size, PAGE_SIZE); |
e465058d | 421 | |
3991605c | 422 | return iommu_alloc(dev, tbl, vaddr, npages, dir); |
e465058d JM |
423 | } |
424 | ||
3991605c FT |
425 | static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr, |
426 | size_t size, enum dma_data_direction dir, | |
00085f1e | 427 | unsigned long attrs) |
e465058d | 428 | { |
35b6dfa0 | 429 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
430 | unsigned int npages; |
431 | ||
3991605c FT |
432 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
433 | iommu_free(tbl, dma_addr, npages); | |
434 | } | |
435 | ||
0b11e1c6 | 436 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
00085f1e | 437 | dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs) |
e465058d JM |
438 | { |
439 | void *ret = NULL; | |
440 | dma_addr_t mapping; | |
441 | unsigned int npages, order; | |
35b6dfa0 | 442 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
443 | |
444 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
445 | npages = size >> PAGE_SHIFT; | |
446 | order = get_order(size); | |
447 | ||
f10ac8a2 FT |
448 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
449 | ||
e465058d JM |
450 | /* alloc enough pages (and possibly more) */ |
451 | ret = (void *)__get_free_pages(flag, order); | |
452 | if (!ret) | |
453 | goto error; | |
454 | memset(ret, 0, size); | |
455 | ||
1956a96d AB |
456 | /* set up tces to cover the allocated range */ |
457 | mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL); | |
8bd17c66 | 458 | if (mapping == CALGARY_MAPPING_ERROR) |
1956a96d AB |
459 | goto free; |
460 | *dma_handle = mapping; | |
e465058d | 461 | return ret; |
e465058d JM |
462 | free: |
463 | free_pages((unsigned long)ret, get_order(size)); | |
464 | ret = NULL; | |
465 | error: | |
466 | return ret; | |
467 | } | |
468 | ||
e4ad68b6 | 469 | static void calgary_free_coherent(struct device *dev, size_t size, |
baa676fc | 470 | void *vaddr, dma_addr_t dma_handle, |
00085f1e | 471 | unsigned long attrs) |
e4ad68b6 JR |
472 | { |
473 | unsigned int npages; | |
474 | struct iommu_table *tbl = find_iommu_table(dev); | |
475 | ||
476 | size = PAGE_ALIGN(size); | |
477 | npages = size >> PAGE_SHIFT; | |
478 | ||
479 | iommu_free(tbl, dma_handle, npages); | |
480 | free_pages((unsigned long)vaddr, get_order(size)); | |
481 | } | |
482 | ||
8bd17c66 CH |
483 | static int calgary_mapping_error(struct device *dev, dma_addr_t dma_addr) |
484 | { | |
485 | return dma_addr == CALGARY_MAPPING_ERROR; | |
486 | } | |
487 | ||
5299709d | 488 | static const struct dma_map_ops calgary_dma_ops = { |
baa676fc AP |
489 | .alloc = calgary_alloc_coherent, |
490 | .free = calgary_free_coherent, | |
e465058d JM |
491 | .map_sg = calgary_map_sg, |
492 | .unmap_sg = calgary_unmap_sg, | |
3991605c FT |
493 | .map_page = calgary_map_page, |
494 | .unmap_page = calgary_unmap_page, | |
8bd17c66 | 495 | .mapping_error = calgary_mapping_error, |
5860acc1 | 496 | .dma_supported = x86_dma_supported, |
e465058d JM |
497 | }; |
498 | ||
b34e90b8 LV |
499 | static inline void __iomem * busno_to_bbar(unsigned char num) |
500 | { | |
501 | return bus_info[num].bbar; | |
502 | } | |
503 | ||
e465058d JM |
504 | static inline int busno_to_phbid(unsigned char num) |
505 | { | |
f38db651 | 506 | return bus_info[num].phbid; |
e465058d JM |
507 | } |
508 | ||
509 | static inline unsigned long split_queue_offset(unsigned char num) | |
510 | { | |
511 | size_t idx = busno_to_phbid(num); | |
512 | ||
513 | return split_queue_offsets[idx]; | |
514 | } | |
515 | ||
516 | static inline unsigned long tar_offset(unsigned char num) | |
517 | { | |
518 | size_t idx = busno_to_phbid(num); | |
519 | ||
520 | return tar_offsets[idx]; | |
521 | } | |
522 | ||
523 | static inline unsigned long phb_offset(unsigned char num) | |
524 | { | |
525 | size_t idx = busno_to_phbid(num); | |
526 | ||
527 | return phb_offsets[idx]; | |
528 | } | |
529 | ||
530 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
531 | { | |
532 | unsigned long target = ((unsigned long)bar) | offset; | |
533 | return (void __iomem*)target; | |
534 | } | |
535 | ||
8a244590 MBY |
536 | static inline int is_calioc2(unsigned short device) |
537 | { | |
538 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
539 | } | |
540 | ||
541 | static inline int is_calgary(unsigned short device) | |
542 | { | |
543 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
544 | } | |
545 | ||
546 | static inline int is_cal_pci_dev(unsigned short device) | |
547 | { | |
548 | return (is_calgary(device) || is_calioc2(device)); | |
549 | } | |
550 | ||
ff297b8c | 551 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
552 | { |
553 | u64 val; | |
554 | u32 aer; | |
555 | int i = 0; | |
556 | void __iomem *bbar = tbl->bbar; | |
557 | void __iomem *target; | |
558 | ||
559 | /* disable arbitration on the bus */ | |
560 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
561 | aer = readl(target); | |
562 | writel(0, target); | |
563 | ||
564 | /* read plssr to ensure it got there */ | |
565 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
566 | val = readl(target); | |
567 | ||
568 | /* poll split queues until all DMA activity is done */ | |
569 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
570 | do { | |
571 | val = readq(target); | |
572 | i++; | |
573 | } while ((val & 0xff) != 0xff && i < 100); | |
574 | if (i == 100) | |
c767a54b | 575 | pr_warn("PCI bus not quiesced, continuing anyway\n"); |
e465058d JM |
576 | |
577 | /* invalidate TCE cache */ | |
578 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
579 | writeq(tbl->tar_val, target); | |
580 | ||
581 | /* enable arbitration */ | |
582 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
583 | writel(aer, target); | |
584 | (void)readl(target); /* flush */ | |
585 | } | |
586 | ||
00be3fa4 MBY |
587 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
588 | { | |
589 | void __iomem *bbar = tbl->bbar; | |
590 | void __iomem *target; | |
591 | u64 val64; | |
592 | u32 val; | |
593 | int i = 0; | |
594 | int count = 1; | |
595 | unsigned char bus = tbl->it_busno; | |
596 | ||
597 | begin: | |
598 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
599 | "sequence - count %d\n", bus, count); | |
600 | ||
601 | /* 1. using the Page Migration Control reg set SoftStop */ | |
602 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
603 | val = be32_to_cpu(readl(target)); | |
604 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
605 | val |= PMR_SOFTSTOP; | |
606 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
607 | writel(cpu_to_be32(val), target); | |
608 | ||
609 | /* 2. poll split queues until all DMA activity is done */ | |
610 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
611 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
612 | do { | |
613 | val64 = readq(target); | |
614 | i++; | |
615 | } while ((val64 & 0xff) != 0xff && i < 100); | |
616 | if (i == 100) | |
c767a54b | 617 | pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n"); |
00be3fa4 MBY |
618 | |
619 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
620 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
621 | val = be32_to_cpu(readl(target)); | |
622 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
623 | ||
624 | /* 4. if SoftStopFault - goto (1) */ | |
625 | if (val & PMR_SOFTSTOPFAULT) { | |
626 | if (++count < 100) | |
627 | goto begin; | |
628 | else { | |
c767a54b | 629 | pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n"); |
00be3fa4 MBY |
630 | return; /* pray for the best */ |
631 | } | |
632 | } | |
633 | ||
634 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
635 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
636 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
637 | val = be32_to_cpu(readl(target)); | |
638 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
639 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
640 | val = be32_to_cpu(readl(target)); | |
641 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
642 | ||
643 | /* 6. invalidate TCE cache */ | |
644 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
645 | target = calgary_reg(bbar, tar_offset(bus)); | |
646 | writeq(tbl->tar_val, target); | |
647 | ||
648 | /* 7. Re-read PMCR */ | |
649 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
650 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
651 | val = be32_to_cpu(readl(target)); | |
652 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
653 | ||
654 | /* 8. Remove HardStop */ | |
655 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
656 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
657 | val = 0; | |
658 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
659 | writel(cpu_to_be32(val), target); | |
660 | val = be32_to_cpu(readl(target)); | |
661 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
662 | } | |
663 | ||
e465058d JM |
664 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
665 | u64 limit) | |
666 | { | |
667 | unsigned int numpages; | |
668 | ||
669 | limit = limit | 0xfffff; | |
670 | limit++; | |
671 | ||
672 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 673 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
674 | } |
675 | ||
676 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
677 | { | |
678 | void __iomem *target; | |
679 | u64 low, high, sizelow; | |
680 | u64 start, limit; | |
08f1c192 | 681 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
682 | unsigned char busnum = dev->bus->number; |
683 | void __iomem *bbar = tbl->bbar; | |
684 | ||
685 | /* peripheral MEM_1 region */ | |
686 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
687 | low = be32_to_cpu(readl(target)); | |
688 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
689 | high = be32_to_cpu(readl(target)); | |
690 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
691 | sizelow = be32_to_cpu(readl(target)); | |
692 | ||
693 | start = (high << 32) | low; | |
694 | limit = sizelow; | |
695 | ||
696 | calgary_reserve_mem_region(dev, start, limit); | |
697 | } | |
698 | ||
699 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
700 | { | |
701 | void __iomem *target; | |
702 | u32 val32; | |
703 | u64 low, high, sizelow, sizehigh; | |
704 | u64 start, limit; | |
08f1c192 | 705 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
706 | unsigned char busnum = dev->bus->number; |
707 | void __iomem *bbar = tbl->bbar; | |
708 | ||
709 | /* is it enabled? */ | |
710 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
711 | val32 = be32_to_cpu(readl(target)); | |
712 | if (!(val32 & PHB_MEM2_ENABLE)) | |
713 | return; | |
714 | ||
715 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
716 | low = be32_to_cpu(readl(target)); | |
717 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
718 | high = be32_to_cpu(readl(target)); | |
719 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
720 | sizelow = be32_to_cpu(readl(target)); | |
721 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
722 | sizehigh = be32_to_cpu(readl(target)); | |
723 | ||
724 | start = (high << 32) | low; | |
725 | limit = (sizehigh << 32) | sizelow; | |
726 | ||
727 | calgary_reserve_mem_region(dev, start, limit); | |
728 | } | |
729 | ||
730 | /* | |
731 | * some regions of the IO address space do not get translated, so we | |
732 | * must not give devices IO addresses in those regions. The regions | |
733 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
734 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
735 | * later. | |
736 | */ | |
737 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
738 | { | |
739 | unsigned int npages; | |
e465058d | 740 | u64 start; |
08f1c192 | 741 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 742 | |
310adfdd | 743 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
8bd17c66 | 744 | iommu_range_reserve(tbl, CALGARY_MAPPING_ERROR, EMERGENCY_PAGES); |
e465058d JM |
745 | |
746 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 747 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
748 | if (is_calgary(dev->device)) { |
749 | start = (640 * 1024); | |
750 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
751 | } else { /* calioc2 */ | |
752 | start = 0; | |
e8f20414 | 753 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 754 | } |
e465058d JM |
755 | iommu_range_reserve(tbl, start, npages); |
756 | ||
757 | /* reserve the two PCI peripheral memory regions in IO space */ | |
758 | calgary_reserve_peripheral_mem_1(dev); | |
759 | calgary_reserve_peripheral_mem_2(dev); | |
760 | } | |
761 | ||
762 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
763 | { | |
764 | u64 val64; | |
765 | u64 table_phys; | |
766 | void __iomem *target; | |
767 | int ret; | |
768 | struct iommu_table *tbl; | |
769 | ||
770 | /* build TCE tables for each PHB */ | |
771 | ret = build_tce_table(dev, bbar); | |
772 | if (ret) | |
773 | return ret; | |
774 | ||
08f1c192 | 775 | tbl = pci_iommu(dev->bus); |
f38db651 | 776 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
95b68dec C |
777 | |
778 | if (is_kdump_kernel()) | |
779 | calgary_init_bitmap_from_tce_table(tbl); | |
780 | else | |
781 | tce_free(tbl, 0, tbl->it_size); | |
f38db651 | 782 | |
8bcf7705 MBY |
783 | if (is_calgary(dev->device)) |
784 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
785 | else if (is_calioc2(dev->device)) |
786 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
787 | else |
788 | BUG(); | |
ff297b8c | 789 | |
e465058d JM |
790 | calgary_reserve_regions(dev); |
791 | ||
792 | /* set TARs for each PHB */ | |
793 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
794 | val64 = be64_to_cpu(readq(target)); | |
795 | ||
796 | /* zero out all TAR bits under sw control */ | |
797 | val64 &= ~TAR_SW_BITS; | |
e465058d | 798 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 799 | |
e465058d JM |
800 | val64 |= table_phys; |
801 | ||
802 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
803 | val64 |= (u64) specified_table_size; | |
804 | ||
805 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 806 | |
e465058d JM |
807 | writeq(tbl->tar_val, target); |
808 | readq(target); /* flush */ | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
b8f4fe66 | 813 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
814 | { |
815 | u64 val64; | |
08f1c192 | 816 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 817 | void __iomem *target; |
b8f4fe66 | 818 | unsigned int bitmapsz; |
e465058d JM |
819 | |
820 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
821 | val64 = be64_to_cpu(readq(target)); | |
822 | val64 &= ~TAR_SW_BITS; | |
823 | writeq(cpu_to_be64(val64), target); | |
824 | readq(target); /* flush */ | |
825 | ||
b8f4fe66 MBY |
826 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
827 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
828 | tbl->it_map = NULL; | |
829 | ||
e465058d | 830 | kfree(tbl); |
08f1c192 MBY |
831 | |
832 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
833 | |
834 | /* Can't free bootmem allocated memory after system is up :-( */ | |
835 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
836 | } |
837 | ||
8a244590 MBY |
838 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
839 | { | |
840 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 841 | void __iomem *target; |
ddbd41b4 | 842 | u32 csr, plssr; |
8cb32dc7 MBY |
843 | |
844 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
845 | csr = be32_to_cpu(readl(target)); |
846 | ||
847 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
848 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
849 | |
850 | /* If no error, the agent ID in the CSR is not valid */ | |
c767a54b JP |
851 | pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n", |
852 | tbl->it_busno, csr, plssr); | |
8cb32dc7 MBY |
853 | } |
854 | ||
855 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
856 | { | |
857 | void __iomem *bbar = tbl->bbar; | |
858 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
859 | void __iomem *target; |
860 | unsigned long phboff = phb_offset(tbl->it_busno); | |
861 | unsigned long erroff; | |
862 | u32 errregs[7]; | |
863 | int i; | |
864 | ||
865 | /* dump CSR */ | |
866 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
867 | csr = be32_to_cpu(readl(target)); | |
868 | /* dump PLSSR */ | |
869 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
870 | plssr = be32_to_cpu(readl(target)); | |
871 | /* dump CSMR */ | |
872 | target = calgary_reg(bbar, phboff | 0x290); | |
873 | csmr = be32_to_cpu(readl(target)); | |
874 | /* dump mck */ | |
875 | target = calgary_reg(bbar, phboff | 0x800); | |
876 | mck = be32_to_cpu(readl(target)); | |
877 | ||
c767a54b | 878 | pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno); |
8cb32dc7 | 879 | |
c767a54b JP |
880 | pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", |
881 | csr, plssr, csmr, mck); | |
8a244590 MBY |
882 | |
883 | /* dump rest of error regs */ | |
c767a54b | 884 | pr_emerg(""); |
8a244590 | 885 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { |
7354b075 MBY |
886 | /* err regs are at 0x810 - 0x870 */ |
887 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
888 | target = calgary_reg(bbar, phboff | erroff); |
889 | errregs[i] = be32_to_cpu(readl(target)); | |
c767a54b | 890 | pr_cont("0x%08x@0x%lx ", errregs[i], erroff); |
8a244590 | 891 | } |
c767a54b | 892 | pr_cont("\n"); |
8cb32dc7 MBY |
893 | |
894 | /* root complex status */ | |
895 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
896 | rcstat = be32_to_cpu(readl(target)); | |
897 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
898 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
899 | } |
900 | ||
3142692a | 901 | static void calgary_watchdog(struct timer_list *t) |
e465058d | 902 | { |
3142692a | 903 | struct iommu_table *tbl = from_timer(tbl, t, watchdog_timer); |
e465058d JM |
904 | void __iomem *bbar = tbl->bbar; |
905 | u32 val32; | |
906 | void __iomem *target; | |
907 | ||
908 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
909 | val32 = be32_to_cpu(readl(target)); | |
910 | ||
911 | /* If no error, the agent ID in the CSR is not valid */ | |
912 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 913 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
914 | |
915 | /* reset error */ | |
e465058d JM |
916 | writel(0, target); |
917 | ||
918 | /* Disable bus that caused the error */ | |
919 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 920 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
921 | val32 = be32_to_cpu(readl(target)); |
922 | val32 |= PHB_SLOT_DISABLE; | |
923 | writel(cpu_to_be32(val32), target); | |
924 | readl(target); /* flush */ | |
925 | } else { | |
926 | /* Reset the timer */ | |
927 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
928 | } | |
929 | } | |
930 | ||
a2b663f6 MBY |
931 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
932 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
933 | { |
934 | u64 val64; | |
935 | void __iomem *target; | |
58db8548 | 936 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
937 | u64 mask; |
938 | ||
939 | switch (busno_to_phbid(busnum)) { | |
940 | case 0: phb_shift = (63 - 19); | |
941 | break; | |
942 | case 1: phb_shift = (63 - 23); | |
943 | break; | |
944 | case 2: phb_shift = (63 - 27); | |
945 | break; | |
946 | case 3: phb_shift = (63 - 35); | |
947 | break; | |
948 | default: | |
949 | BUG_ON(busno_to_phbid(busnum)); | |
950 | } | |
951 | ||
952 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
953 | val64 = be64_to_cpu(readq(target)); | |
954 | ||
955 | /* zero out this PHB's timer bits */ | |
956 | mask = ~(0xFUL << phb_shift); | |
957 | val64 &= mask; | |
a2b663f6 | 958 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
959 | writeq(cpu_to_be64(val64), target); |
960 | readq(target); /* flush */ | |
961 | } | |
962 | ||
31f3dff6 | 963 | static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
c3860108 MBY |
964 | { |
965 | unsigned char busnum = dev->bus->number; | |
966 | void __iomem *bbar = tbl->bbar; | |
967 | void __iomem *target; | |
968 | u32 val; | |
969 | ||
8bcf7705 MBY |
970 | /* |
971 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
972 | */ | |
973 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
974 | val = cpu_to_be32(readl(target)); | |
975 | val |= 0x00800000; | |
976 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
977 | } |
978 | ||
31f3dff6 | 979 | static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
b8d2ea1b MBY |
980 | { |
981 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
982 | |
983 | /* | |
984 | * Give split completion a longer timeout on bus 1 for aic94xx | |
985 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
986 | */ | |
c3860108 | 987 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
988 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
989 | CCR_2SEC_TIMEOUT); | |
990 | } | |
991 | ||
e465058d JM |
992 | static void __init calgary_enable_translation(struct pci_dev *dev) |
993 | { | |
994 | u32 val32; | |
995 | unsigned char busnum; | |
996 | void __iomem *target; | |
997 | void __iomem *bbar; | |
998 | struct iommu_table *tbl; | |
999 | ||
1000 | busnum = dev->bus->number; | |
08f1c192 | 1001 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1002 | bbar = tbl->bbar; |
1003 | ||
1004 | /* enable TCE in PHB Config Register */ | |
1005 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1006 | val32 = be32_to_cpu(readl(target)); | |
1007 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
1008 | ||
8a244590 MBY |
1009 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
1010 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
1011 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1012 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1013 | "bus.\n"); | |
1014 | ||
1015 | writel(cpu_to_be32(val32), target); | |
1016 | readl(target); /* flush */ | |
1017 | ||
3142692a | 1018 | timer_setup(&tbl->watchdog_timer, calgary_watchdog, 0); |
e465058d JM |
1019 | mod_timer(&tbl->watchdog_timer, jiffies); |
1020 | } | |
1021 | ||
1022 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1023 | { | |
1024 | u32 val32; | |
1025 | unsigned char busnum; | |
1026 | void __iomem *target; | |
1027 | void __iomem *bbar; | |
1028 | struct iommu_table *tbl; | |
1029 | ||
1030 | busnum = dev->bus->number; | |
08f1c192 | 1031 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1032 | bbar = tbl->bbar; |
1033 | ||
1034 | /* disable TCE in PHB Config Register */ | |
1035 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1036 | val32 = be32_to_cpu(readl(target)); | |
1037 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1038 | ||
70d666d6 | 1039 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1040 | writel(cpu_to_be32(val32), target); |
1041 | readl(target); /* flush */ | |
1042 | ||
1043 | del_timer_sync(&tbl->watchdog_timer); | |
1044 | } | |
1045 | ||
a4fc520a | 1046 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1047 | { |
871b1700 | 1048 | pci_dev_get(dev); |
08f1c192 | 1049 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1050 | |
1051 | /* is the device behind a bridge? */ | |
1052 | if (dev->bus->parent) | |
1053 | dev->bus->parent->self = dev; | |
1054 | else | |
1055 | dev->bus->self = dev; | |
e465058d JM |
1056 | } |
1057 | ||
1058 | static int __init calgary_init_one(struct pci_dev *dev) | |
1059 | { | |
e465058d | 1060 | void __iomem *bbar; |
ff297b8c | 1061 | struct iommu_table *tbl; |
e465058d JM |
1062 | int ret; |
1063 | ||
eae93755 | 1064 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1065 | ret = calgary_setup_tar(dev, bbar); |
1066 | if (ret) | |
eae93755 | 1067 | goto done; |
e465058d | 1068 | |
871b1700 | 1069 | pci_dev_get(dev); |
8a244590 MBY |
1070 | |
1071 | if (dev->bus->parent) { | |
1072 | if (dev->bus->parent->self) | |
1073 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1074 | "bus->parent->self!\n", dev); | |
1075 | dev->bus->parent->self = dev; | |
1076 | } else | |
1077 | dev->bus->self = dev; | |
b8d2ea1b | 1078 | |
08f1c192 | 1079 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1080 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1081 | |
e465058d JM |
1082 | calgary_enable_translation(dev); |
1083 | ||
1084 | return 0; | |
1085 | ||
e465058d JM |
1086 | done: |
1087 | return ret; | |
1088 | } | |
1089 | ||
eae93755 | 1090 | static int __init calgary_locate_bbars(void) |
e465058d | 1091 | { |
eae93755 MBY |
1092 | int ret; |
1093 | int rioidx, phb, bus; | |
b34e90b8 LV |
1094 | void __iomem *bbar; |
1095 | void __iomem *target; | |
eae93755 | 1096 | unsigned long offset; |
b34e90b8 LV |
1097 | u8 start_bus, end_bus; |
1098 | u32 val; | |
1099 | ||
eae93755 MBY |
1100 | ret = -ENODATA; |
1101 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1102 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1103 | |
eae93755 | 1104 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1105 | continue; |
1106 | ||
1107 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1108 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1109 | if (!bbar) | |
1110 | goto error; | |
b34e90b8 LV |
1111 | |
1112 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1113 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1114 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1115 | |
b34e90b8 | 1116 | val = be32_to_cpu(readl(target)); |
8a244590 | 1117 | |
b34e90b8 | 1118 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1119 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1120 | |
1121 | if (end_bus) { | |
1122 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1123 | bus_info[bus].bbar = bbar; | |
1124 | bus_info[bus].phbid = phb; | |
1125 | } | |
1126 | } else { | |
1127 | bus_info[start_bus].bbar = bbar; | |
1128 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1129 | } |
1130 | } | |
1131 | } | |
1132 | ||
eae93755 MBY |
1133 | return 0; |
1134 | ||
1135 | error: | |
1136 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1137 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1138 | if (bus_info[bus].bbar) | |
1139 | iounmap(bus_info[bus].bbar); | |
1140 | ||
1141 | return ret; | |
1142 | } | |
1143 | ||
1144 | static int __init calgary_init(void) | |
1145 | { | |
1146 | int ret; | |
1147 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1148 | struct calgary_bus_info *info; |
eae93755 MBY |
1149 | |
1150 | ret = calgary_locate_bbars(); | |
1151 | if (ret) | |
1152 | return ret; | |
e465058d | 1153 | |
95b68dec C |
1154 | /* Purely for kdump kernel case */ |
1155 | if (is_kdump_kernel()) | |
1156 | get_tce_space_from_tar(); | |
1157 | ||
dedc9937 | 1158 | do { |
8a244590 | 1159 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1160 | if (!dev) |
1161 | break; | |
8a244590 MBY |
1162 | if (!is_cal_pci_dev(dev->device)) |
1163 | continue; | |
bc3c6058 MBY |
1164 | |
1165 | info = &bus_info[dev->bus->number]; | |
1166 | if (info->translation_disabled) { | |
e465058d JM |
1167 | calgary_init_one_nontraslated(dev); |
1168 | continue; | |
1169 | } | |
bc3c6058 MBY |
1170 | |
1171 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1172 | continue; |
12de257b | 1173 | |
e465058d JM |
1174 | ret = calgary_init_one(dev); |
1175 | if (ret) | |
1176 | goto error; | |
dedc9937 | 1177 | } while (1); |
e465058d | 1178 | |
1956a96d AB |
1179 | dev = NULL; |
1180 | for_each_pci_dev(dev) { | |
1181 | struct iommu_table *tbl; | |
1182 | ||
1183 | tbl = find_iommu_table(&dev->dev); | |
1184 | ||
1185 | if (translation_enabled(tbl)) | |
5657933d | 1186 | dev->dev.dma_ops = &calgary_dma_ops; |
1956a96d AB |
1187 | } |
1188 | ||
e465058d JM |
1189 | return ret; |
1190 | ||
1191 | error: | |
dedc9937 | 1192 | do { |
a2b5d877 | 1193 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
9f2dc46d MBY |
1194 | if (!dev) |
1195 | break; | |
8a244590 MBY |
1196 | if (!is_cal_pci_dev(dev->device)) |
1197 | continue; | |
bc3c6058 MBY |
1198 | |
1199 | info = &bus_info[dev->bus->number]; | |
1200 | if (info->translation_disabled) { | |
e465058d JM |
1201 | pci_dev_put(dev); |
1202 | continue; | |
1203 | } | |
bc3c6058 | 1204 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1205 | continue; |
871b1700 | 1206 | |
e465058d | 1207 | calgary_disable_translation(dev); |
b8f4fe66 | 1208 | calgary_free_bus(dev); |
871b1700 | 1209 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
5657933d | 1210 | dev->dev.dma_ops = NULL; |
dedc9937 | 1211 | } while (1); |
e465058d JM |
1212 | |
1213 | return ret; | |
1214 | } | |
1215 | ||
0534af01 | 1216 | static inline int __init determine_tce_table_size(void) |
e465058d JM |
1217 | { |
1218 | int ret; | |
1219 | ||
1220 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1221 | return specified_table_size; | |
1222 | ||
0534af01 WC |
1223 | if (is_kdump_kernel() && saved_max_pfn) { |
1224 | /* | |
1225 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1226 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1227 | * larger table size has twice as many entries, so shift the | |
1228 | * max ram address by 13 to divide by 8K and then look at the | |
1229 | * order of the result to choose between 0-7. | |
1230 | */ | |
1231 | ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13); | |
1232 | if (ret > TCE_TABLE_SIZE_8M) | |
1233 | ret = TCE_TABLE_SIZE_8M; | |
1234 | } else { | |
1235 | /* | |
1236 | * Use 8M by default (suggested by Muli) if it's not | |
1237 | * kdump kernel and saved_max_pfn isn't set. | |
1238 | */ | |
e465058d | 1239 | ret = TCE_TABLE_SIZE_8M; |
0534af01 | 1240 | } |
e465058d JM |
1241 | |
1242 | return ret; | |
1243 | } | |
1244 | ||
b34e90b8 LV |
1245 | static int __init build_detail_arrays(void) |
1246 | { | |
1247 | unsigned long ptr; | |
85d57797 DH |
1248 | unsigned numnodes, i; |
1249 | int scal_detail_size, rio_detail_size; | |
b34e90b8 | 1250 | |
85d57797 DH |
1251 | numnodes = rio_table_hdr->num_scal_dev; |
1252 | if (numnodes > MAX_NUMNODES){ | |
b34e90b8 | 1253 | printk(KERN_WARNING |
eae93755 | 1254 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 | 1255 | "but system has %d nodes.\n", |
85d57797 | 1256 | MAX_NUMNODES, numnodes); |
b34e90b8 LV |
1257 | return -ENODEV; |
1258 | } | |
1259 | ||
1260 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1261 | case 2: |
1262 | scal_detail_size = 11; | |
1263 | rio_detail_size = 13; | |
1264 | break; | |
1265 | case 3: | |
1266 | scal_detail_size = 12; | |
1267 | rio_detail_size = 15; | |
1268 | break; | |
eae93755 MBY |
1269 | default: |
1270 | printk(KERN_WARNING | |
1271 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1272 | rio_table_hdr->version); | |
1273 | return -EPROTO; | |
b34e90b8 LV |
1274 | } |
1275 | ||
1276 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
85d57797 | 1277 | for (i = 0; i < numnodes; i++, ptr += scal_detail_size) |
b34e90b8 LV |
1278 | scal_devs[i] = (struct scal_detail *)ptr; |
1279 | ||
1280 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1281 | i++, ptr += rio_detail_size) | |
1282 | rio_devs[i] = (struct rio_detail *)ptr; | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
8a244590 | 1287 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1288 | { |
8a244590 | 1289 | int dev; |
e465058d | 1290 | u32 val; |
8a244590 MBY |
1291 | |
1292 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1293 | /* | |
0d2eb44f | 1294 | * FIXME: properly scan for devices across the |
8a244590 MBY |
1295 | * PCI-to-PCI bridge on every CalIOC2 port. |
1296 | */ | |
1297 | return 1; | |
1298 | } | |
1299 | ||
1300 | for (dev = 1; dev < 8; dev++) { | |
1301 | val = read_pci_config(bus, dev, 0, 0); | |
1302 | if (val != 0xffffffff) | |
1303 | break; | |
1304 | } | |
1305 | return (val != 0xffffffff); | |
1306 | } | |
1307 | ||
95b68dec C |
1308 | /* |
1309 | * calgary_init_bitmap_from_tce_table(): | |
0d2eb44f | 1310 | * Function for kdump case. In the second/kdump kernel initialize |
95b68dec C |
1311 | * the bitmap based on the tce table entries obtained from first kernel |
1312 | */ | |
1313 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl) | |
1314 | { | |
1315 | u64 *tp; | |
1316 | unsigned int index; | |
1317 | tp = ((u64 *)tbl->it_base); | |
1318 | for (index = 0 ; index < tbl->it_size; index++) { | |
1319 | if (*tp != 0x0) | |
1320 | set_bit(index, tbl->it_map); | |
1321 | tp++; | |
1322 | } | |
1323 | } | |
1324 | ||
1325 | /* | |
1326 | * get_tce_space_from_tar(): | |
1327 | * Function for kdump case. Get the tce tables from first kernel | |
3ad2f3fb | 1328 | * by reading the contents of the base address register of calgary iommu |
95b68dec | 1329 | */ |
f7106662 | 1330 | static void __init get_tce_space_from_tar(void) |
95b68dec C |
1331 | { |
1332 | int bus; | |
1333 | void __iomem *target; | |
1334 | unsigned long tce_space; | |
1335 | ||
1336 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { | |
1337 | struct calgary_bus_info *info = &bus_info[bus]; | |
1338 | unsigned short pci_device; | |
1339 | u32 val; | |
1340 | ||
1341 | val = read_pci_config(bus, 0, 0, 0); | |
1342 | pci_device = (val & 0xFFFF0000) >> 16; | |
1343 | ||
1344 | if (!is_cal_pci_dev(pci_device)) | |
1345 | continue; | |
1346 | if (info->translation_disabled) | |
1347 | continue; | |
1348 | ||
1349 | if (calgary_bus_has_devices(bus, pci_device) || | |
1350 | translate_empty_slots) { | |
1351 | target = calgary_reg(bus_info[bus].bbar, | |
1352 | tar_offset(bus)); | |
1353 | tce_space = be64_to_cpu(readq(target)); | |
1354 | tce_space = tce_space & TAR_SW_BITS; | |
1355 | ||
1356 | tce_space = tce_space & (~specified_table_size); | |
1357 | info->tce_space = (u64 *)__va(tce_space); | |
1358 | } | |
1359 | } | |
1360 | return; | |
1361 | } | |
1362 | ||
f4131c62 FT |
1363 | static int __init calgary_iommu_init(void) |
1364 | { | |
1365 | int ret; | |
1366 | ||
1367 | /* ok, we're trying to use Calgary - let's roll */ | |
1368 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1369 | ||
1370 | ret = calgary_init(); | |
1371 | if (ret) { | |
1372 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1373 | "falling back to no_iommu\n", ret); | |
1374 | return ret; | |
1375 | } | |
1376 | ||
f4131c62 FT |
1377 | return 0; |
1378 | } | |
d7b9f7be | 1379 | |
480125ba | 1380 | int __init detect_calgary(void) |
8a244590 | 1381 | { |
d2105b10 | 1382 | int bus; |
e465058d | 1383 | void *tbl; |
d2105b10 | 1384 | int calgary_found = 0; |
b34e90b8 | 1385 | unsigned long ptr; |
136f1e7a | 1386 | unsigned int offset, prev_offset; |
eae93755 | 1387 | int ret; |
e465058d JM |
1388 | |
1389 | /* | |
1390 | * if the user specified iommu=off or iommu=soft or we found | |
1391 | * another HW IOMMU already, bail out. | |
1392 | */ | |
75f1cdf1 | 1393 | if (no_iommu || iommu_detected) |
480125ba | 1394 | return -ENODEV; |
e465058d | 1395 | |
bff6547b | 1396 | if (!use_calgary) |
480125ba | 1397 | return -ENODEV; |
bff6547b | 1398 | |
0637a70a | 1399 | if (!early_pci_allowed()) |
480125ba | 1400 | return -ENODEV; |
0637a70a | 1401 | |
b92cc559 MBY |
1402 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1403 | ||
b34e90b8 LV |
1404 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1405 | ||
1406 | rio_table_hdr = NULL; | |
136f1e7a | 1407 | prev_offset = 0; |
b34e90b8 | 1408 | offset = 0x180; |
136f1e7a IM |
1409 | /* |
1410 | * The next offset is stored in the 1st word. | |
1411 | * Only parse up until the offset increases: | |
1412 | */ | |
1413 | while (offset > prev_offset) { | |
b34e90b8 LV |
1414 | /* The block id is stored in the 2nd word */ |
1415 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1416 | /* set the pointer past the offset & block id */ | |
eae93755 | 1417 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1418 | break; |
1419 | } | |
136f1e7a | 1420 | prev_offset = offset; |
b34e90b8 LV |
1421 | offset = *((unsigned short *)(ptr + offset)); |
1422 | } | |
eae93755 | 1423 | if (!rio_table_hdr) { |
b92cc559 MBY |
1424 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1425 | "in EBDA - bailing!\n"); | |
480125ba | 1426 | return -ENODEV; |
b34e90b8 LV |
1427 | } |
1428 | ||
eae93755 MBY |
1429 | ret = build_detail_arrays(); |
1430 | if (ret) { | |
b92cc559 | 1431 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
480125ba | 1432 | return -ENOMEM; |
eae93755 | 1433 | } |
b34e90b8 | 1434 | |
0534af01 | 1435 | specified_table_size = determine_tce_table_size(); |
e465058d | 1436 | |
d2105b10 | 1437 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1438 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1439 | unsigned short pci_device; |
1440 | u32 val; | |
1441 | ||
1442 | val = read_pci_config(bus, 0, 0, 0); | |
1443 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1444 | |
8a244590 | 1445 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1446 | continue; |
d2105b10 | 1447 | |
f38db651 | 1448 | if (info->translation_disabled) |
e465058d | 1449 | continue; |
f38db651 | 1450 | |
8a244590 MBY |
1451 | if (calgary_bus_has_devices(bus, pci_device) || |
1452 | translate_empty_slots) { | |
95b68dec C |
1453 | /* |
1454 | * If it is kdump kernel, find and use tce tables | |
1455 | * from first kernel, else allocate tce tables here | |
1456 | */ | |
1457 | if (!is_kdump_kernel()) { | |
1458 | tbl = alloc_tce_table(); | |
1459 | if (!tbl) | |
1460 | goto cleanup; | |
1461 | info->tce_space = tbl; | |
1462 | } | |
8a244590 | 1463 | calgary_found = 1; |
d2105b10 | 1464 | } |
e465058d JM |
1465 | } |
1466 | ||
b92cc559 MBY |
1467 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1468 | calgary_found ? "found" : "not found"); | |
1469 | ||
d2105b10 | 1470 | if (calgary_found) { |
e465058d JM |
1471 | iommu_detected = 1; |
1472 | calgary_detected = 1; | |
de684652 | 1473 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
7e05575c FT |
1474 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n", |
1475 | specified_table_size); | |
1956a96d | 1476 | |
d7b9f7be | 1477 | x86_init.iommu.iommu_init = calgary_iommu_init; |
e465058d | 1478 | } |
480125ba | 1479 | return calgary_found; |
e465058d JM |
1480 | |
1481 | cleanup: | |
f38db651 MBY |
1482 | for (--bus; bus >= 0; --bus) { |
1483 | struct calgary_bus_info *info = &bus_info[bus]; | |
1484 | ||
1485 | if (info->tce_space) | |
1486 | free_tce_table(info->tce_space); | |
1487 | } | |
480125ba | 1488 | return -ENOMEM; |
e465058d JM |
1489 | } |
1490 | ||
e465058d JM |
1491 | static int __init calgary_parse_options(char *p) |
1492 | { | |
1493 | unsigned int bridge; | |
74bc4917 | 1494 | unsigned long val; |
e465058d | 1495 | size_t len; |
74bc4917 | 1496 | ssize_t ret; |
e465058d JM |
1497 | |
1498 | while (*p) { | |
1499 | if (!strncmp(p, "64k", 3)) | |
1500 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1501 | else if (!strncmp(p, "128k", 4)) | |
1502 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1503 | else if (!strncmp(p, "256k", 4)) | |
1504 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1505 | else if (!strncmp(p, "512k", 4)) | |
1506 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1507 | else if (!strncmp(p, "1M", 2)) | |
1508 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1509 | else if (!strncmp(p, "2M", 2)) | |
1510 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1511 | else if (!strncmp(p, "4M", 2)) | |
1512 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1513 | else if (!strncmp(p, "8M", 2)) | |
1514 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1515 | ||
1516 | len = strlen("translate_empty_slots"); | |
1517 | if (!strncmp(p, "translate_empty_slots", len)) | |
1518 | translate_empty_slots = 1; | |
1519 | ||
1520 | len = strlen("disable"); | |
1521 | if (!strncmp(p, "disable", len)) { | |
1522 | p += len; | |
1523 | if (*p == '=') | |
1524 | ++p; | |
1525 | if (*p == '\0') | |
1526 | break; | |
74bc4917 SK |
1527 | ret = kstrtoul(p, 0, &val); |
1528 | if (ret) | |
e465058d JM |
1529 | break; |
1530 | ||
74bc4917 | 1531 | bridge = val; |
d2105b10 | 1532 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1533 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1534 | "translation for PHB %#x\n", bridge); |
f38db651 | 1535 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1536 | } |
1537 | } | |
1538 | ||
1539 | p = strpbrk(p, ","); | |
1540 | if (!p) | |
1541 | break; | |
1542 | ||
1543 | p++; /* skip ',' */ | |
1544 | } | |
1545 | return 1; | |
1546 | } | |
1547 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1548 | |
1549 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1550 | { | |
1551 | struct iommu_table *tbl; | |
1552 | unsigned int npages; | |
1553 | int i; | |
1554 | ||
08f1c192 | 1555 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1556 | |
1557 | for (i = 0; i < 4; i++) { | |
1558 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1559 | ||
1560 | /* Don't give out TCEs that map MEM resources */ | |
1561 | if (!(r->flags & IORESOURCE_MEM)) | |
1562 | continue; | |
1563 | ||
1564 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1565 | if (!r->start) | |
1566 | continue; | |
1567 | ||
1568 | /* cover the whole region */ | |
28f65c11 | 1569 | npages = resource_size(r) >> PAGE_SHIFT; |
07877cf6 MBY |
1570 | npages++; |
1571 | ||
07877cf6 MBY |
1572 | iommu_range_reserve(tbl, r->start, npages); |
1573 | } | |
1574 | } | |
1575 | ||
1576 | static int __init calgary_fixup_tce_spaces(void) | |
1577 | { | |
1578 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1579 | struct calgary_bus_info *info; |
07877cf6 MBY |
1580 | |
1581 | if (no_iommu || swiotlb || !calgary_detected) | |
1582 | return -ENODEV; | |
1583 | ||
12de257b | 1584 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1585 | |
1586 | do { | |
1587 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1588 | if (!dev) | |
1589 | break; | |
1590 | if (!is_cal_pci_dev(dev->device)) | |
1591 | continue; | |
bc3c6058 MBY |
1592 | |
1593 | info = &bus_info[dev->bus->number]; | |
1594 | if (info->translation_disabled) | |
07877cf6 MBY |
1595 | continue; |
1596 | ||
bc3c6058 | 1597 | if (!info->tce_space) |
07877cf6 MBY |
1598 | continue; |
1599 | ||
1600 | calgary_fixup_one_tce_space(dev); | |
1601 | ||
1602 | } while (1); | |
1603 | ||
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | /* | |
1608 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1609 | * and before device_initcall. | |
1610 | */ | |
1611 | rootfs_initcall(calgary_fixup_tce_spaces); | |
d2aa232f KRW |
1612 | |
1613 | IOMMU_INIT_POST(detect_calgary); |