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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
e465058d JM |
33 | #include <linux/bitops.h> |
34 | #include <linux/pci_ids.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/delay.h> | |
8b87d9f4 | 37 | #include <linux/scatterlist.h> |
395624fc | 38 | #include <asm/gart.h> |
e465058d JM |
39 | #include <asm/calgary.h> |
40 | #include <asm/tce.h> | |
41 | #include <asm/pci-direct.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/dma.h> | |
b34e90b8 | 44 | #include <asm/rio.h> |
e465058d | 45 | |
bff6547b MBY |
46 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
47 | int use_calgary __read_mostly = 1; | |
48 | #else | |
49 | int use_calgary __read_mostly = 0; | |
50 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
51 | ||
e465058d | 52 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 53 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 54 | |
e465058d | 55 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
56 | #define CALGARY_CONFIG_REG 0x0108 |
57 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
58 | #define PHB_PLSSR_OFFSET 0x0120 |
59 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
60 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
61 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
62 | #define PHB_MEM_1_LOW 0x0190 | |
63 | #define PHB_MEM_1_HIGH 0x01A0 | |
64 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
65 | #define PHB_MEM_1_SIZE 0x01C0 | |
66 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
67 | #define PHB_AER_OFFSET 0x0200 | |
68 | #define PHB_CONFIG_0_HIGH 0x0220 | |
69 | #define PHB_CONFIG_0_LOW 0x0230 | |
70 | #define PHB_CONFIG_0_END 0x0240 | |
71 | #define PHB_MEM_2_LOW 0x02B0 | |
72 | #define PHB_MEM_2_HIGH 0x02C0 | |
73 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
74 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
75 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
76 | ||
c3860108 | 77 | /* CalIOC2 specific */ |
8bcf7705 MBY |
78 | #define PHB_SAVIOR_L2 0x0DB0 |
79 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
80 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 81 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 82 | |
e465058d JM |
83 | /* PHB_CONFIG_RW */ |
84 | #define PHB_TCE_ENABLE 0x20000000 | |
85 | #define PHB_SLOT_DISABLE 0x1C000000 | |
86 | #define PHB_DAC_DISABLE 0x01000000 | |
87 | #define PHB_MEM2_ENABLE 0x00400000 | |
88 | #define PHB_MCSR_ENABLE 0x00100000 | |
89 | /* TAR (Table Address Register) */ | |
90 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
91 | #define TAR_VALID 0x0000000000000008UL | |
92 | /* CSR (Channel/DMA Status Register) */ | |
93 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 94 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 95 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 96 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
97 | #define PMR_SOFTSTOP 0x80000000 |
98 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
99 | #define PMR_HARDSTOP 0x20000000 | |
e465058d JM |
100 | |
101 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 102 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
103 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
104 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
105 | #define PHBS_PER_CALGARY 4 |
106 | ||
107 | /* register offsets in Calgary's internal register space */ | |
108 | static const unsigned long tar_offsets[] = { | |
109 | 0x0580 /* TAR0 */, | |
110 | 0x0588 /* TAR1 */, | |
111 | 0x0590 /* TAR2 */, | |
112 | 0x0598 /* TAR3 */ | |
113 | }; | |
114 | ||
115 | static const unsigned long split_queue_offsets[] = { | |
116 | 0x4870 /* SPLIT QUEUE 0 */, | |
117 | 0x5870 /* SPLIT QUEUE 1 */, | |
118 | 0x6870 /* SPLIT QUEUE 2 */, | |
119 | 0x7870 /* SPLIT QUEUE 3 */ | |
120 | }; | |
121 | ||
122 | static const unsigned long phb_offsets[] = { | |
123 | 0x8000 /* PHB0 */, | |
124 | 0x9000 /* PHB1 */, | |
125 | 0xA000 /* PHB2 */, | |
126 | 0xB000 /* PHB3 */ | |
127 | }; | |
128 | ||
b34e90b8 LV |
129 | /* PHB debug registers */ |
130 | ||
131 | static const unsigned long phb_debug_offsets[] = { | |
132 | 0x4000 /* PHB 0 DEBUG */, | |
133 | 0x5000 /* PHB 1 DEBUG */, | |
134 | 0x6000 /* PHB 2 DEBUG */, | |
135 | 0x7000 /* PHB 3 DEBUG */ | |
136 | }; | |
137 | ||
138 | /* | |
139 | * STUFF register for each debug PHB, | |
140 | * byte 1 = start bus number, byte 2 = end bus number | |
141 | */ | |
142 | ||
143 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
144 | ||
310adfdd MBY |
145 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
146 | ||
e465058d JM |
147 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
148 | static int translate_empty_slots __read_mostly = 0; | |
149 | static int calgary_detected __read_mostly = 0; | |
150 | ||
b34e90b8 LV |
151 | static struct rio_table_hdr *rio_table_hdr __initdata; |
152 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 153 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 154 | |
f38db651 MBY |
155 | struct calgary_bus_info { |
156 | void *tce_space; | |
0577f148 | 157 | unsigned char translation_disabled; |
f38db651 | 158 | signed char phbid; |
b34e90b8 | 159 | void __iomem *bbar; |
f38db651 MBY |
160 | }; |
161 | ||
ff297b8c MBY |
162 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
163 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 164 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 165 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 166 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 167 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
ff297b8c MBY |
168 | |
169 | static struct cal_chipset_ops calgary_chip_ops = { | |
170 | .handle_quirks = calgary_handle_quirks, | |
8cb32dc7 MBY |
171 | .tce_cache_blast = calgary_tce_cache_blast, |
172 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 173 | }; |
e465058d | 174 | |
c3860108 MBY |
175 | static struct cal_chipset_ops calioc2_chip_ops = { |
176 | .handle_quirks = calioc2_handle_quirks, | |
8cb32dc7 MBY |
177 | .tce_cache_blast = calioc2_tce_cache_blast, |
178 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
179 | }; |
180 | ||
ff297b8c | 181 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
182 | |
183 | /* enable this to stress test the chip's TCE cache */ | |
184 | #ifdef CONFIG_IOMMU_DEBUG | |
ed65260b | 185 | static int debugging = 1; |
de684652 | 186 | |
796e4390 MBY |
187 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
188 | int expected, unsigned long start, unsigned long end) | |
189 | { | |
190 | unsigned long idx = start; | |
191 | ||
192 | BUG_ON(start >= end); | |
193 | ||
194 | while (idx < end) { | |
195 | if (!!test_bit(idx, bitmap) != expected) | |
196 | return idx; | |
197 | ++idx; | |
198 | } | |
199 | ||
200 | /* all bits have the expected value */ | |
201 | return ~0UL; | |
202 | } | |
de684652 | 203 | #else /* debugging is disabled */ |
ed65260b | 204 | static int debugging; |
de684652 | 205 | |
796e4390 MBY |
206 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
207 | int expected, unsigned long start, unsigned long end) | |
208 | { | |
209 | return ~0UL; | |
210 | } | |
8a244590 | 211 | |
de684652 | 212 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
213 | |
214 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
215 | { | |
216 | unsigned int npages; | |
217 | ||
218 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
219 | npages >>= PAGE_SHIFT; | |
220 | ||
221 | return npages; | |
222 | } | |
223 | ||
d588ba8c MBY |
224 | static inline int translation_enabled(struct iommu_table *tbl) |
225 | { | |
226 | /* only PHBs with translation enabled have an IOMMU table */ | |
227 | return (tbl != NULL); | |
228 | } | |
229 | ||
e465058d | 230 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 231 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
232 | { |
233 | unsigned long index; | |
234 | unsigned long end; | |
796e4390 | 235 | unsigned long badbit; |
820a1497 | 236 | unsigned long flags; |
e465058d JM |
237 | |
238 | index = start_addr >> PAGE_SHIFT; | |
239 | ||
240 | /* bail out if we're asked to reserve a region we don't cover */ | |
241 | if (index >= tbl->it_size) | |
242 | return; | |
243 | ||
244 | end = index + npages; | |
245 | if (end > tbl->it_size) /* don't go off the table */ | |
246 | end = tbl->it_size; | |
247 | ||
820a1497 MBY |
248 | spin_lock_irqsave(&tbl->it_lock, flags); |
249 | ||
796e4390 MBY |
250 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
251 | if (badbit != ~0UL) { | |
252 | if (printk_ratelimit()) | |
e465058d JM |
253 | printk(KERN_ERR "Calgary: entry already allocated at " |
254 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 255 | badbit, tbl, start_addr, npages); |
e465058d | 256 | } |
796e4390 MBY |
257 | |
258 | set_bit_string(tbl->it_map, index, npages); | |
820a1497 MBY |
259 | |
260 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
261 | } |
262 | ||
263 | static unsigned long iommu_range_alloc(struct iommu_table *tbl, | |
264 | unsigned int npages) | |
265 | { | |
820a1497 | 266 | unsigned long flags; |
e465058d JM |
267 | unsigned long offset; |
268 | ||
269 | BUG_ON(npages == 0); | |
270 | ||
820a1497 MBY |
271 | spin_lock_irqsave(&tbl->it_lock, flags); |
272 | ||
e465058d JM |
273 | offset = find_next_zero_string(tbl->it_map, tbl->it_hint, |
274 | tbl->it_size, npages); | |
275 | if (offset == ~0UL) { | |
ff297b8c | 276 | tbl->chip_ops->tce_cache_blast(tbl); |
e465058d JM |
277 | offset = find_next_zero_string(tbl->it_map, 0, |
278 | tbl->it_size, npages); | |
279 | if (offset == ~0UL) { | |
280 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
820a1497 | 281 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
282 | if (panic_on_overflow) |
283 | panic("Calgary: fix the allocator.\n"); | |
284 | else | |
285 | return bad_dma_address; | |
286 | } | |
287 | } | |
288 | ||
289 | set_bit_string(tbl->it_map, offset, npages); | |
290 | tbl->it_hint = offset + npages; | |
291 | BUG_ON(tbl->it_hint > tbl->it_size); | |
292 | ||
820a1497 MBY |
293 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
294 | ||
e465058d JM |
295 | return offset; |
296 | } | |
297 | ||
298 | static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr, | |
299 | unsigned int npages, int direction) | |
300 | { | |
820a1497 | 301 | unsigned long entry; |
e465058d JM |
302 | dma_addr_t ret = bad_dma_address; |
303 | ||
e465058d JM |
304 | entry = iommu_range_alloc(tbl, npages); |
305 | ||
306 | if (unlikely(entry == bad_dma_address)) | |
307 | goto error; | |
308 | ||
309 | /* set the return dma address */ | |
310 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
311 | ||
312 | /* put the TCEs in the HW table */ | |
313 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
314 | direction); | |
315 | ||
e465058d JM |
316 | return ret; |
317 | ||
318 | error: | |
e465058d JM |
319 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " |
320 | "iommu %p\n", npages, tbl); | |
321 | return bad_dma_address; | |
322 | } | |
323 | ||
3cc39bda | 324 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
325 | unsigned int npages) |
326 | { | |
327 | unsigned long entry; | |
796e4390 | 328 | unsigned long badbit; |
310adfdd | 329 | unsigned long badend; |
820a1497 | 330 | unsigned long flags; |
310adfdd MBY |
331 | |
332 | /* were we called with bad_dma_address? */ | |
333 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
334 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
335 | printk(KERN_ERR "Calgary: driver tried unmapping bad DMA " | |
336 | "address 0x%Lx\n", dma_addr); | |
337 | WARN_ON(1); | |
338 | return; | |
339 | } | |
e465058d JM |
340 | |
341 | entry = dma_addr >> PAGE_SHIFT; | |
342 | ||
343 | BUG_ON(entry + npages > tbl->it_size); | |
344 | ||
345 | tce_free(tbl, entry, npages); | |
346 | ||
820a1497 MBY |
347 | spin_lock_irqsave(&tbl->it_lock, flags); |
348 | ||
796e4390 MBY |
349 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
350 | if (badbit != ~0UL) { | |
351 | if (printk_ratelimit()) | |
e465058d JM |
352 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
353 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 354 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
355 | } |
356 | ||
357 | __clear_bit_string(tbl->it_map, entry, npages); | |
820a1497 MBY |
358 | |
359 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
360 | } |
361 | ||
35b6dfa0 MBY |
362 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
363 | { | |
8a244590 MBY |
364 | struct pci_dev *pdev; |
365 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
366 | struct iommu_table *tbl; |
367 | ||
8a244590 MBY |
368 | pdev = to_pci_dev(dev); |
369 | ||
f055a061 MFB |
370 | pbus = pdev->bus; |
371 | ||
372 | /* is the device behind a bridge? Look for the root bus */ | |
373 | while (pbus->parent) | |
374 | pbus = pbus->parent; | |
8a244590 | 375 | |
08f1c192 | 376 | tbl = pci_iommu(pbus); |
7354b075 | 377 | |
f055a061 | 378 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
379 | |
380 | return tbl; | |
381 | } | |
382 | ||
3cc39bda | 383 | static void calgary_unmap_sg(struct device *dev, |
e465058d JM |
384 | struct scatterlist *sglist, int nelems, int direction) |
385 | { | |
3cc39bda | 386 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
387 | struct scatterlist *s; |
388 | int i; | |
3cc39bda | 389 | |
bc3c6058 | 390 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
391 | return; |
392 | ||
8b87d9f4 | 393 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 394 | unsigned int npages; |
8b87d9f4 JA |
395 | dma_addr_t dma = s->dma_address; |
396 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
397 | |
398 | if (dmalen == 0) | |
399 | break; | |
400 | ||
401 | npages = num_dma_pages(dma, dmalen); | |
3cc39bda | 402 | iommu_free(tbl, dma, npages); |
e465058d JM |
403 | } |
404 | } | |
405 | ||
e465058d JM |
406 | static int calgary_nontranslate_map_sg(struct device* dev, |
407 | struct scatterlist *sg, int nelems, int direction) | |
408 | { | |
8b87d9f4 | 409 | struct scatterlist *s; |
e465058d JM |
410 | int i; |
411 | ||
8b87d9f4 | 412 | for_each_sg(sg, s, nelems, i) { |
58b053e4 JA |
413 | struct page *p = sg_page(s); |
414 | ||
415 | BUG_ON(!p); | |
416 | s->dma_address = virt_to_bus(sg_virt(s)); | |
e465058d JM |
417 | s->dma_length = s->length; |
418 | } | |
419 | return nelems; | |
420 | } | |
421 | ||
0b11e1c6 | 422 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
e465058d JM |
423 | int nelems, int direction) |
424 | { | |
35b6dfa0 | 425 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 426 | struct scatterlist *s; |
e465058d JM |
427 | unsigned long vaddr; |
428 | unsigned int npages; | |
429 | unsigned long entry; | |
430 | int i; | |
431 | ||
d588ba8c | 432 | if (!translation_enabled(tbl)) |
e465058d JM |
433 | return calgary_nontranslate_map_sg(dev, sg, nelems, direction); |
434 | ||
8b87d9f4 | 435 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 436 | BUG_ON(!sg_page(s)); |
e465058d | 437 | |
58b053e4 | 438 | vaddr = (unsigned long) sg_virt(s); |
e465058d JM |
439 | npages = num_dma_pages(vaddr, s->length); |
440 | ||
441 | entry = iommu_range_alloc(tbl, npages); | |
442 | if (entry == bad_dma_address) { | |
443 | /* makes sure unmap knows to stop */ | |
444 | s->dma_length = 0; | |
445 | goto error; | |
446 | } | |
447 | ||
448 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
449 | ||
450 | /* insert into HW table */ | |
451 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
452 | direction); | |
453 | ||
454 | s->dma_length = s->length; | |
455 | } | |
456 | ||
e465058d JM |
457 | return nelems; |
458 | error: | |
3cc39bda | 459 | calgary_unmap_sg(dev, sg, nelems, direction); |
8b87d9f4 JA |
460 | for_each_sg(sg, s, nelems, i) { |
461 | sg->dma_address = bad_dma_address; | |
462 | sg->dma_length = 0; | |
e465058d | 463 | } |
e465058d JM |
464 | return 0; |
465 | } | |
466 | ||
0b11e1c6 | 467 | static dma_addr_t calgary_map_single(struct device *dev, void *vaddr, |
e465058d JM |
468 | size_t size, int direction) |
469 | { | |
470 | dma_addr_t dma_handle = bad_dma_address; | |
471 | unsigned long uaddr; | |
472 | unsigned int npages; | |
35b6dfa0 | 473 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
474 | |
475 | uaddr = (unsigned long)vaddr; | |
476 | npages = num_dma_pages(uaddr, size); | |
477 | ||
d588ba8c | 478 | if (translation_enabled(tbl)) |
e465058d JM |
479 | dma_handle = iommu_alloc(tbl, vaddr, npages, direction); |
480 | else | |
481 | dma_handle = virt_to_bus(vaddr); | |
482 | ||
483 | return dma_handle; | |
484 | } | |
485 | ||
0b11e1c6 | 486 | static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, |
e465058d JM |
487 | size_t size, int direction) |
488 | { | |
35b6dfa0 | 489 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
490 | unsigned int npages; |
491 | ||
d588ba8c | 492 | if (!translation_enabled(tbl)) |
e465058d JM |
493 | return; |
494 | ||
495 | npages = num_dma_pages(dma_handle, size); | |
496 | iommu_free(tbl, dma_handle, npages); | |
497 | } | |
498 | ||
0b11e1c6 | 499 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
e465058d JM |
500 | dma_addr_t *dma_handle, gfp_t flag) |
501 | { | |
502 | void *ret = NULL; | |
503 | dma_addr_t mapping; | |
504 | unsigned int npages, order; | |
35b6dfa0 | 505 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
506 | |
507 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
508 | npages = size >> PAGE_SHIFT; | |
509 | order = get_order(size); | |
510 | ||
511 | /* alloc enough pages (and possibly more) */ | |
512 | ret = (void *)__get_free_pages(flag, order); | |
513 | if (!ret) | |
514 | goto error; | |
515 | memset(ret, 0, size); | |
516 | ||
d588ba8c | 517 | if (translation_enabled(tbl)) { |
e465058d JM |
518 | /* set up tces to cover the allocated range */ |
519 | mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL); | |
520 | if (mapping == bad_dma_address) | |
521 | goto free; | |
522 | ||
523 | *dma_handle = mapping; | |
524 | } else /* non translated slot */ | |
525 | *dma_handle = virt_to_bus(ret); | |
526 | ||
527 | return ret; | |
528 | ||
529 | free: | |
530 | free_pages((unsigned long)ret, get_order(size)); | |
531 | ret = NULL; | |
532 | error: | |
533 | return ret; | |
534 | } | |
535 | ||
e6584504 | 536 | static const struct dma_mapping_ops calgary_dma_ops = { |
e465058d JM |
537 | .alloc_coherent = calgary_alloc_coherent, |
538 | .map_single = calgary_map_single, | |
539 | .unmap_single = calgary_unmap_single, | |
540 | .map_sg = calgary_map_sg, | |
541 | .unmap_sg = calgary_unmap_sg, | |
542 | }; | |
543 | ||
b34e90b8 LV |
544 | static inline void __iomem * busno_to_bbar(unsigned char num) |
545 | { | |
546 | return bus_info[num].bbar; | |
547 | } | |
548 | ||
e465058d JM |
549 | static inline int busno_to_phbid(unsigned char num) |
550 | { | |
f38db651 | 551 | return bus_info[num].phbid; |
e465058d JM |
552 | } |
553 | ||
554 | static inline unsigned long split_queue_offset(unsigned char num) | |
555 | { | |
556 | size_t idx = busno_to_phbid(num); | |
557 | ||
558 | return split_queue_offsets[idx]; | |
559 | } | |
560 | ||
561 | static inline unsigned long tar_offset(unsigned char num) | |
562 | { | |
563 | size_t idx = busno_to_phbid(num); | |
564 | ||
565 | return tar_offsets[idx]; | |
566 | } | |
567 | ||
568 | static inline unsigned long phb_offset(unsigned char num) | |
569 | { | |
570 | size_t idx = busno_to_phbid(num); | |
571 | ||
572 | return phb_offsets[idx]; | |
573 | } | |
574 | ||
575 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
576 | { | |
577 | unsigned long target = ((unsigned long)bar) | offset; | |
578 | return (void __iomem*)target; | |
579 | } | |
580 | ||
8a244590 MBY |
581 | static inline int is_calioc2(unsigned short device) |
582 | { | |
583 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
584 | } | |
585 | ||
586 | static inline int is_calgary(unsigned short device) | |
587 | { | |
588 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
589 | } | |
590 | ||
591 | static inline int is_cal_pci_dev(unsigned short device) | |
592 | { | |
593 | return (is_calgary(device) || is_calioc2(device)); | |
594 | } | |
595 | ||
ff297b8c | 596 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
597 | { |
598 | u64 val; | |
599 | u32 aer; | |
600 | int i = 0; | |
601 | void __iomem *bbar = tbl->bbar; | |
602 | void __iomem *target; | |
603 | ||
604 | /* disable arbitration on the bus */ | |
605 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
606 | aer = readl(target); | |
607 | writel(0, target); | |
608 | ||
609 | /* read plssr to ensure it got there */ | |
610 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
611 | val = readl(target); | |
612 | ||
613 | /* poll split queues until all DMA activity is done */ | |
614 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
615 | do { | |
616 | val = readq(target); | |
617 | i++; | |
618 | } while ((val & 0xff) != 0xff && i < 100); | |
619 | if (i == 100) | |
620 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
621 | "continuing anyway\n"); | |
622 | ||
623 | /* invalidate TCE cache */ | |
624 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
625 | writeq(tbl->tar_val, target); | |
626 | ||
627 | /* enable arbitration */ | |
628 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
629 | writel(aer, target); | |
630 | (void)readl(target); /* flush */ | |
631 | } | |
632 | ||
00be3fa4 MBY |
633 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
634 | { | |
635 | void __iomem *bbar = tbl->bbar; | |
636 | void __iomem *target; | |
637 | u64 val64; | |
638 | u32 val; | |
639 | int i = 0; | |
640 | int count = 1; | |
641 | unsigned char bus = tbl->it_busno; | |
642 | ||
643 | begin: | |
644 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
645 | "sequence - count %d\n", bus, count); | |
646 | ||
647 | /* 1. using the Page Migration Control reg set SoftStop */ | |
648 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
649 | val = be32_to_cpu(readl(target)); | |
650 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
651 | val |= PMR_SOFTSTOP; | |
652 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
653 | writel(cpu_to_be32(val), target); | |
654 | ||
655 | /* 2. poll split queues until all DMA activity is done */ | |
656 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
657 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
658 | do { | |
659 | val64 = readq(target); | |
660 | i++; | |
661 | } while ((val64 & 0xff) != 0xff && i < 100); | |
662 | if (i == 100) | |
663 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | |
664 | "continuing anyway\n"); | |
665 | ||
666 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
667 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
668 | val = be32_to_cpu(readl(target)); | |
669 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
670 | ||
671 | /* 4. if SoftStopFault - goto (1) */ | |
672 | if (val & PMR_SOFTSTOPFAULT) { | |
673 | if (++count < 100) | |
674 | goto begin; | |
675 | else { | |
676 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | |
677 | "aborting TCE cache flush sequence!\n"); | |
678 | return; /* pray for the best */ | |
679 | } | |
680 | } | |
681 | ||
682 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
683 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
684 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
685 | val = be32_to_cpu(readl(target)); | |
686 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
687 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
688 | val = be32_to_cpu(readl(target)); | |
689 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
690 | ||
691 | /* 6. invalidate TCE cache */ | |
692 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
693 | target = calgary_reg(bbar, tar_offset(bus)); | |
694 | writeq(tbl->tar_val, target); | |
695 | ||
696 | /* 7. Re-read PMCR */ | |
697 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
698 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
699 | val = be32_to_cpu(readl(target)); | |
700 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
701 | ||
702 | /* 8. Remove HardStop */ | |
703 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
704 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
705 | val = 0; | |
706 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
707 | writel(cpu_to_be32(val), target); | |
708 | val = be32_to_cpu(readl(target)); | |
709 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
710 | } | |
711 | ||
e465058d JM |
712 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
713 | u64 limit) | |
714 | { | |
715 | unsigned int numpages; | |
716 | ||
717 | limit = limit | 0xfffff; | |
718 | limit++; | |
719 | ||
720 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 721 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
722 | } |
723 | ||
724 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
725 | { | |
726 | void __iomem *target; | |
727 | u64 low, high, sizelow; | |
728 | u64 start, limit; | |
08f1c192 | 729 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
730 | unsigned char busnum = dev->bus->number; |
731 | void __iomem *bbar = tbl->bbar; | |
732 | ||
733 | /* peripheral MEM_1 region */ | |
734 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
735 | low = be32_to_cpu(readl(target)); | |
736 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
737 | high = be32_to_cpu(readl(target)); | |
738 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
739 | sizelow = be32_to_cpu(readl(target)); | |
740 | ||
741 | start = (high << 32) | low; | |
742 | limit = sizelow; | |
743 | ||
744 | calgary_reserve_mem_region(dev, start, limit); | |
745 | } | |
746 | ||
747 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
748 | { | |
749 | void __iomem *target; | |
750 | u32 val32; | |
751 | u64 low, high, sizelow, sizehigh; | |
752 | u64 start, limit; | |
08f1c192 | 753 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
754 | unsigned char busnum = dev->bus->number; |
755 | void __iomem *bbar = tbl->bbar; | |
756 | ||
757 | /* is it enabled? */ | |
758 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
759 | val32 = be32_to_cpu(readl(target)); | |
760 | if (!(val32 & PHB_MEM2_ENABLE)) | |
761 | return; | |
762 | ||
763 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
764 | low = be32_to_cpu(readl(target)); | |
765 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
766 | high = be32_to_cpu(readl(target)); | |
767 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
768 | sizelow = be32_to_cpu(readl(target)); | |
769 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
770 | sizehigh = be32_to_cpu(readl(target)); | |
771 | ||
772 | start = (high << 32) | low; | |
773 | limit = (sizehigh << 32) | sizelow; | |
774 | ||
775 | calgary_reserve_mem_region(dev, start, limit); | |
776 | } | |
777 | ||
778 | /* | |
779 | * some regions of the IO address space do not get translated, so we | |
780 | * must not give devices IO addresses in those regions. The regions | |
781 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
782 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
783 | * later. | |
784 | */ | |
785 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
786 | { | |
787 | unsigned int npages; | |
e465058d | 788 | u64 start; |
08f1c192 | 789 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 790 | |
310adfdd MBY |
791 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
792 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
793 | |
794 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 795 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
796 | if (is_calgary(dev->device)) { |
797 | start = (640 * 1024); | |
798 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
799 | } else { /* calioc2 */ | |
800 | start = 0; | |
e8f20414 | 801 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 802 | } |
e465058d JM |
803 | iommu_range_reserve(tbl, start, npages); |
804 | ||
805 | /* reserve the two PCI peripheral memory regions in IO space */ | |
806 | calgary_reserve_peripheral_mem_1(dev); | |
807 | calgary_reserve_peripheral_mem_2(dev); | |
808 | } | |
809 | ||
810 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
811 | { | |
812 | u64 val64; | |
813 | u64 table_phys; | |
814 | void __iomem *target; | |
815 | int ret; | |
816 | struct iommu_table *tbl; | |
817 | ||
818 | /* build TCE tables for each PHB */ | |
819 | ret = build_tce_table(dev, bbar); | |
820 | if (ret) | |
821 | return ret; | |
822 | ||
08f1c192 | 823 | tbl = pci_iommu(dev->bus); |
f38db651 MBY |
824 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
825 | tce_free(tbl, 0, tbl->it_size); | |
826 | ||
8bcf7705 MBY |
827 | if (is_calgary(dev->device)) |
828 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
829 | else if (is_calioc2(dev->device)) |
830 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
831 | else |
832 | BUG(); | |
ff297b8c | 833 | |
e465058d JM |
834 | calgary_reserve_regions(dev); |
835 | ||
836 | /* set TARs for each PHB */ | |
837 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
838 | val64 = be64_to_cpu(readq(target)); | |
839 | ||
840 | /* zero out all TAR bits under sw control */ | |
841 | val64 &= ~TAR_SW_BITS; | |
e465058d | 842 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 843 | |
e465058d JM |
844 | val64 |= table_phys; |
845 | ||
846 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
847 | val64 |= (u64) specified_table_size; | |
848 | ||
849 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 850 | |
e465058d JM |
851 | writeq(tbl->tar_val, target); |
852 | readq(target); /* flush */ | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
b8f4fe66 | 857 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
858 | { |
859 | u64 val64; | |
08f1c192 | 860 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 861 | void __iomem *target; |
b8f4fe66 | 862 | unsigned int bitmapsz; |
e465058d JM |
863 | |
864 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
865 | val64 = be64_to_cpu(readq(target)); | |
866 | val64 &= ~TAR_SW_BITS; | |
867 | writeq(cpu_to_be64(val64), target); | |
868 | readq(target); /* flush */ | |
869 | ||
b8f4fe66 MBY |
870 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
871 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
872 | tbl->it_map = NULL; | |
873 | ||
e465058d | 874 | kfree(tbl); |
08f1c192 MBY |
875 | |
876 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
877 | |
878 | /* Can't free bootmem allocated memory after system is up :-( */ | |
879 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
880 | } |
881 | ||
8a244590 MBY |
882 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
883 | { | |
884 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 885 | void __iomem *target; |
ddbd41b4 | 886 | u32 csr, plssr; |
8cb32dc7 MBY |
887 | |
888 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
889 | csr = be32_to_cpu(readl(target)); |
890 | ||
891 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
892 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
893 | |
894 | /* If no error, the agent ID in the CSR is not valid */ | |
895 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | |
ddbd41b4 | 896 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); |
8cb32dc7 MBY |
897 | } |
898 | ||
899 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
900 | { | |
901 | void __iomem *bbar = tbl->bbar; | |
902 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
903 | void __iomem *target; |
904 | unsigned long phboff = phb_offset(tbl->it_busno); | |
905 | unsigned long erroff; | |
906 | u32 errregs[7]; | |
907 | int i; | |
908 | ||
909 | /* dump CSR */ | |
910 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
911 | csr = be32_to_cpu(readl(target)); | |
912 | /* dump PLSSR */ | |
913 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
914 | plssr = be32_to_cpu(readl(target)); | |
915 | /* dump CSMR */ | |
916 | target = calgary_reg(bbar, phboff | 0x290); | |
917 | csmr = be32_to_cpu(readl(target)); | |
918 | /* dump mck */ | |
919 | target = calgary_reg(bbar, phboff | 0x800); | |
920 | mck = be32_to_cpu(readl(target)); | |
921 | ||
8cb32dc7 MBY |
922 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", |
923 | tbl->it_busno); | |
924 | ||
925 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | |
926 | csr, plssr, csmr, mck); | |
8a244590 MBY |
927 | |
928 | /* dump rest of error regs */ | |
929 | printk(KERN_EMERG "Calgary: "); | |
930 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
7354b075 MBY |
931 | /* err regs are at 0x810 - 0x870 */ |
932 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
933 | target = calgary_reg(bbar, phboff | erroff); |
934 | errregs[i] = be32_to_cpu(readl(target)); | |
935 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
936 | } | |
937 | printk("\n"); | |
8cb32dc7 MBY |
938 | |
939 | /* root complex status */ | |
940 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
941 | rcstat = be32_to_cpu(readl(target)); | |
942 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
943 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
944 | } |
945 | ||
e465058d JM |
946 | static void calgary_watchdog(unsigned long data) |
947 | { | |
948 | struct pci_dev *dev = (struct pci_dev *)data; | |
08f1c192 | 949 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
950 | void __iomem *bbar = tbl->bbar; |
951 | u32 val32; | |
952 | void __iomem *target; | |
953 | ||
954 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
955 | val32 = be32_to_cpu(readl(target)); | |
956 | ||
957 | /* If no error, the agent ID in the CSR is not valid */ | |
958 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 959 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
960 | |
961 | /* reset error */ | |
e465058d JM |
962 | writel(0, target); |
963 | ||
964 | /* Disable bus that caused the error */ | |
965 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 966 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
967 | val32 = be32_to_cpu(readl(target)); |
968 | val32 |= PHB_SLOT_DISABLE; | |
969 | writel(cpu_to_be32(val32), target); | |
970 | readl(target); /* flush */ | |
971 | } else { | |
972 | /* Reset the timer */ | |
973 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
974 | } | |
975 | } | |
976 | ||
a2b663f6 MBY |
977 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
978 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
979 | { |
980 | u64 val64; | |
981 | void __iomem *target; | |
58db8548 | 982 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
983 | u64 mask; |
984 | ||
985 | switch (busno_to_phbid(busnum)) { | |
986 | case 0: phb_shift = (63 - 19); | |
987 | break; | |
988 | case 1: phb_shift = (63 - 23); | |
989 | break; | |
990 | case 2: phb_shift = (63 - 27); | |
991 | break; | |
992 | case 3: phb_shift = (63 - 35); | |
993 | break; | |
994 | default: | |
995 | BUG_ON(busno_to_phbid(busnum)); | |
996 | } | |
997 | ||
998 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
999 | val64 = be64_to_cpu(readq(target)); | |
1000 | ||
1001 | /* zero out this PHB's timer bits */ | |
1002 | mask = ~(0xFUL << phb_shift); | |
1003 | val64 &= mask; | |
a2b663f6 | 1004 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
1005 | writeq(cpu_to_be64(val64), target); |
1006 | readq(target); /* flush */ | |
1007 | } | |
1008 | ||
c3860108 MBY |
1009 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
1010 | { | |
1011 | unsigned char busnum = dev->bus->number; | |
1012 | void __iomem *bbar = tbl->bbar; | |
1013 | void __iomem *target; | |
1014 | u32 val; | |
1015 | ||
8bcf7705 MBY |
1016 | /* |
1017 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
1018 | */ | |
1019 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
1020 | val = cpu_to_be32(readl(target)); | |
1021 | val |= 0x00800000; | |
1022 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
1023 | } |
1024 | ||
1025 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) | |
b8d2ea1b MBY |
1026 | { |
1027 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
1028 | |
1029 | /* | |
1030 | * Give split completion a longer timeout on bus 1 for aic94xx | |
1031 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
1032 | */ | |
c3860108 | 1033 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
1034 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
1035 | CCR_2SEC_TIMEOUT); | |
1036 | } | |
1037 | ||
e465058d JM |
1038 | static void __init calgary_enable_translation(struct pci_dev *dev) |
1039 | { | |
1040 | u32 val32; | |
1041 | unsigned char busnum; | |
1042 | void __iomem *target; | |
1043 | void __iomem *bbar; | |
1044 | struct iommu_table *tbl; | |
1045 | ||
1046 | busnum = dev->bus->number; | |
08f1c192 | 1047 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1048 | bbar = tbl->bbar; |
1049 | ||
1050 | /* enable TCE in PHB Config Register */ | |
1051 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1052 | val32 = be32_to_cpu(readl(target)); | |
1053 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
1054 | ||
8a244590 MBY |
1055 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
1056 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
1057 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1058 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1059 | "bus.\n"); | |
1060 | ||
1061 | writel(cpu_to_be32(val32), target); | |
1062 | readl(target); /* flush */ | |
1063 | ||
1064 | init_timer(&tbl->watchdog_timer); | |
1065 | tbl->watchdog_timer.function = &calgary_watchdog; | |
1066 | tbl->watchdog_timer.data = (unsigned long)dev; | |
1067 | mod_timer(&tbl->watchdog_timer, jiffies); | |
1068 | } | |
1069 | ||
1070 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1071 | { | |
1072 | u32 val32; | |
1073 | unsigned char busnum; | |
1074 | void __iomem *target; | |
1075 | void __iomem *bbar; | |
1076 | struct iommu_table *tbl; | |
1077 | ||
1078 | busnum = dev->bus->number; | |
08f1c192 | 1079 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1080 | bbar = tbl->bbar; |
1081 | ||
1082 | /* disable TCE in PHB Config Register */ | |
1083 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1084 | val32 = be32_to_cpu(readl(target)); | |
1085 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1086 | ||
70d666d6 | 1087 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1088 | writel(cpu_to_be32(val32), target); |
1089 | readl(target); /* flush */ | |
1090 | ||
1091 | del_timer_sync(&tbl->watchdog_timer); | |
1092 | } | |
1093 | ||
a4fc520a | 1094 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1095 | { |
871b1700 | 1096 | pci_dev_get(dev); |
08f1c192 | 1097 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1098 | |
1099 | /* is the device behind a bridge? */ | |
1100 | if (dev->bus->parent) | |
1101 | dev->bus->parent->self = dev; | |
1102 | else | |
1103 | dev->bus->self = dev; | |
e465058d JM |
1104 | } |
1105 | ||
1106 | static int __init calgary_init_one(struct pci_dev *dev) | |
1107 | { | |
e465058d | 1108 | void __iomem *bbar; |
ff297b8c | 1109 | struct iommu_table *tbl; |
e465058d JM |
1110 | int ret; |
1111 | ||
dedc9937 JM |
1112 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1113 | ||
eae93755 | 1114 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1115 | ret = calgary_setup_tar(dev, bbar); |
1116 | if (ret) | |
eae93755 | 1117 | goto done; |
e465058d | 1118 | |
871b1700 | 1119 | pci_dev_get(dev); |
8a244590 MBY |
1120 | |
1121 | if (dev->bus->parent) { | |
1122 | if (dev->bus->parent->self) | |
1123 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1124 | "bus->parent->self!\n", dev); | |
1125 | dev->bus->parent->self = dev; | |
1126 | } else | |
1127 | dev->bus->self = dev; | |
b8d2ea1b | 1128 | |
08f1c192 | 1129 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1130 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1131 | |
e465058d JM |
1132 | calgary_enable_translation(dev); |
1133 | ||
1134 | return 0; | |
1135 | ||
e465058d JM |
1136 | done: |
1137 | return ret; | |
1138 | } | |
1139 | ||
eae93755 | 1140 | static int __init calgary_locate_bbars(void) |
e465058d | 1141 | { |
eae93755 MBY |
1142 | int ret; |
1143 | int rioidx, phb, bus; | |
b34e90b8 LV |
1144 | void __iomem *bbar; |
1145 | void __iomem *target; | |
eae93755 | 1146 | unsigned long offset; |
b34e90b8 LV |
1147 | u8 start_bus, end_bus; |
1148 | u32 val; | |
1149 | ||
eae93755 MBY |
1150 | ret = -ENODATA; |
1151 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1152 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1153 | |
eae93755 | 1154 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1155 | continue; |
1156 | ||
1157 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1158 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1159 | if (!bbar) | |
1160 | goto error; | |
b34e90b8 LV |
1161 | |
1162 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1163 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1164 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1165 | |
b34e90b8 | 1166 | val = be32_to_cpu(readl(target)); |
8a244590 | 1167 | |
b34e90b8 | 1168 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1169 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1170 | |
1171 | if (end_bus) { | |
1172 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1173 | bus_info[bus].bbar = bbar; | |
1174 | bus_info[bus].phbid = phb; | |
1175 | } | |
1176 | } else { | |
1177 | bus_info[start_bus].bbar = bbar; | |
1178 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1179 | } |
1180 | } | |
1181 | } | |
1182 | ||
eae93755 MBY |
1183 | return 0; |
1184 | ||
1185 | error: | |
1186 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1187 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1188 | if (bus_info[bus].bbar) | |
1189 | iounmap(bus_info[bus].bbar); | |
1190 | ||
1191 | return ret; | |
1192 | } | |
1193 | ||
1194 | static int __init calgary_init(void) | |
1195 | { | |
1196 | int ret; | |
1197 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1198 | struct calgary_bus_info *info; |
eae93755 MBY |
1199 | |
1200 | ret = calgary_locate_bbars(); | |
1201 | if (ret) | |
1202 | return ret; | |
e465058d | 1203 | |
dedc9937 | 1204 | do { |
8a244590 | 1205 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1206 | if (!dev) |
1207 | break; | |
8a244590 MBY |
1208 | if (!is_cal_pci_dev(dev->device)) |
1209 | continue; | |
bc3c6058 MBY |
1210 | |
1211 | info = &bus_info[dev->bus->number]; | |
1212 | if (info->translation_disabled) { | |
e465058d JM |
1213 | calgary_init_one_nontraslated(dev); |
1214 | continue; | |
1215 | } | |
bc3c6058 MBY |
1216 | |
1217 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1218 | continue; |
12de257b | 1219 | |
e465058d JM |
1220 | ret = calgary_init_one(dev); |
1221 | if (ret) | |
1222 | goto error; | |
dedc9937 | 1223 | } while (1); |
e465058d JM |
1224 | |
1225 | return ret; | |
1226 | ||
1227 | error: | |
dedc9937 | 1228 | do { |
7cd8b686 | 1229 | dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM, |
8a244590 | 1230 | PCI_ANY_ID, dev); |
9f2dc46d MBY |
1231 | if (!dev) |
1232 | break; | |
8a244590 MBY |
1233 | if (!is_cal_pci_dev(dev->device)) |
1234 | continue; | |
bc3c6058 MBY |
1235 | |
1236 | info = &bus_info[dev->bus->number]; | |
1237 | if (info->translation_disabled) { | |
e465058d JM |
1238 | pci_dev_put(dev); |
1239 | continue; | |
1240 | } | |
bc3c6058 | 1241 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1242 | continue; |
871b1700 | 1243 | |
e465058d | 1244 | calgary_disable_translation(dev); |
b8f4fe66 | 1245 | calgary_free_bus(dev); |
871b1700 | 1246 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
dedc9937 | 1247 | } while (1); |
e465058d JM |
1248 | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | static inline int __init determine_tce_table_size(u64 ram) | |
1253 | { | |
1254 | int ret; | |
1255 | ||
1256 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1257 | return specified_table_size; | |
1258 | ||
1259 | /* | |
1260 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1261 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1262 | * larger table size has twice as many entries, so shift the | |
1263 | * max ram address by 13 to divide by 8K and then look at the | |
1264 | * order of the result to choose between 0-7. | |
1265 | */ | |
1266 | ret = get_order(ram >> 13); | |
1267 | if (ret > TCE_TABLE_SIZE_8M) | |
1268 | ret = TCE_TABLE_SIZE_8M; | |
1269 | ||
1270 | return ret; | |
1271 | } | |
1272 | ||
b34e90b8 LV |
1273 | static int __init build_detail_arrays(void) |
1274 | { | |
1275 | unsigned long ptr; | |
1276 | int i, scal_detail_size, rio_detail_size; | |
1277 | ||
1278 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){ | |
1279 | printk(KERN_WARNING | |
eae93755 | 1280 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 LV |
1281 | "but system has %d nodes.\n", |
1282 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1283 | return -ENODEV; | |
1284 | } | |
1285 | ||
1286 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1287 | case 2: |
1288 | scal_detail_size = 11; | |
1289 | rio_detail_size = 13; | |
1290 | break; | |
1291 | case 3: | |
1292 | scal_detail_size = 12; | |
1293 | rio_detail_size = 15; | |
1294 | break; | |
eae93755 MBY |
1295 | default: |
1296 | printk(KERN_WARNING | |
1297 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1298 | rio_table_hdr->version); | |
1299 | return -EPROTO; | |
b34e90b8 LV |
1300 | } |
1301 | ||
1302 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
1303 | for (i = 0; i < rio_table_hdr->num_scal_dev; | |
1304 | i++, ptr += scal_detail_size) | |
1305 | scal_devs[i] = (struct scal_detail *)ptr; | |
1306 | ||
1307 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1308 | i++, ptr += rio_detail_size) | |
1309 | rio_devs[i] = (struct rio_detail *)ptr; | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
8a244590 | 1314 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1315 | { |
8a244590 | 1316 | int dev; |
e465058d | 1317 | u32 val; |
8a244590 MBY |
1318 | |
1319 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1320 | /* | |
1321 | * FIXME: properly scan for devices accross the | |
1322 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1323 | */ | |
1324 | return 1; | |
1325 | } | |
1326 | ||
1327 | for (dev = 1; dev < 8; dev++) { | |
1328 | val = read_pci_config(bus, dev, 0, 0); | |
1329 | if (val != 0xffffffff) | |
1330 | break; | |
1331 | } | |
1332 | return (val != 0xffffffff); | |
1333 | } | |
1334 | ||
1335 | void __init detect_calgary(void) | |
1336 | { | |
d2105b10 | 1337 | int bus; |
e465058d | 1338 | void *tbl; |
d2105b10 | 1339 | int calgary_found = 0; |
b34e90b8 | 1340 | unsigned long ptr; |
136f1e7a | 1341 | unsigned int offset, prev_offset; |
eae93755 | 1342 | int ret; |
e465058d JM |
1343 | |
1344 | /* | |
1345 | * if the user specified iommu=off or iommu=soft or we found | |
1346 | * another HW IOMMU already, bail out. | |
1347 | */ | |
1348 | if (swiotlb || no_iommu || iommu_detected) | |
1349 | return; | |
1350 | ||
bff6547b MBY |
1351 | if (!use_calgary) |
1352 | return; | |
1353 | ||
0637a70a AK |
1354 | if (!early_pci_allowed()) |
1355 | return; | |
1356 | ||
b92cc559 MBY |
1357 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1358 | ||
b34e90b8 LV |
1359 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1360 | ||
1361 | rio_table_hdr = NULL; | |
136f1e7a | 1362 | prev_offset = 0; |
b34e90b8 | 1363 | offset = 0x180; |
136f1e7a IM |
1364 | /* |
1365 | * The next offset is stored in the 1st word. | |
1366 | * Only parse up until the offset increases: | |
1367 | */ | |
1368 | while (offset > prev_offset) { | |
b34e90b8 LV |
1369 | /* The block id is stored in the 2nd word */ |
1370 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1371 | /* set the pointer past the offset & block id */ | |
eae93755 | 1372 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1373 | break; |
1374 | } | |
136f1e7a | 1375 | prev_offset = offset; |
b34e90b8 LV |
1376 | offset = *((unsigned short *)(ptr + offset)); |
1377 | } | |
eae93755 | 1378 | if (!rio_table_hdr) { |
b92cc559 MBY |
1379 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1380 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1381 | return; |
1382 | } | |
1383 | ||
eae93755 MBY |
1384 | ret = build_detail_arrays(); |
1385 | if (ret) { | |
b92cc559 | 1386 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1387 | return; |
eae93755 | 1388 | } |
b34e90b8 | 1389 | |
e465058d JM |
1390 | specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE); |
1391 | ||
d2105b10 | 1392 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1393 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1394 | unsigned short pci_device; |
1395 | u32 val; | |
1396 | ||
1397 | val = read_pci_config(bus, 0, 0, 0); | |
1398 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1399 | |
8a244590 | 1400 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1401 | continue; |
d2105b10 | 1402 | |
f38db651 | 1403 | if (info->translation_disabled) |
e465058d | 1404 | continue; |
f38db651 | 1405 | |
8a244590 MBY |
1406 | if (calgary_bus_has_devices(bus, pci_device) || |
1407 | translate_empty_slots) { | |
1408 | tbl = alloc_tce_table(); | |
1409 | if (!tbl) | |
1410 | goto cleanup; | |
1411 | info->tce_space = tbl; | |
1412 | calgary_found = 1; | |
d2105b10 | 1413 | } |
e465058d JM |
1414 | } |
1415 | ||
b92cc559 MBY |
1416 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1417 | calgary_found ? "found" : "not found"); | |
1418 | ||
d2105b10 | 1419 | if (calgary_found) { |
e465058d JM |
1420 | iommu_detected = 1; |
1421 | calgary_detected = 1; | |
de684652 MBY |
1422 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1423 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1424 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1425 | debugging ? "enabled" : "disabled"); | |
e465058d JM |
1426 | } |
1427 | return; | |
1428 | ||
1429 | cleanup: | |
f38db651 MBY |
1430 | for (--bus; bus >= 0; --bus) { |
1431 | struct calgary_bus_info *info = &bus_info[bus]; | |
1432 | ||
1433 | if (info->tce_space) | |
1434 | free_tce_table(info->tce_space); | |
1435 | } | |
e465058d JM |
1436 | } |
1437 | ||
1438 | int __init calgary_iommu_init(void) | |
1439 | { | |
1440 | int ret; | |
1441 | ||
1442 | if (no_iommu || swiotlb) | |
1443 | return -ENODEV; | |
1444 | ||
1445 | if (!calgary_detected) | |
1446 | return -ENODEV; | |
1447 | ||
1448 | /* ok, we're trying to use Calgary - let's roll */ | |
1449 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1450 | ||
1451 | ret = calgary_init(); | |
1452 | if (ret) { | |
1453 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1454 | "falling back to no_iommu\n", ret); | |
1455 | if (end_pfn > MAX_DMA32_PFN) | |
1456 | printk(KERN_ERR "WARNING more than 4GB of memory, " | |
1457 | "32bit PCI may malfunction.\n"); | |
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | force_iommu = 1; | |
310adfdd | 1462 | bad_dma_address = 0x0; |
e465058d JM |
1463 | dma_ops = &calgary_dma_ops; |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | static int __init calgary_parse_options(char *p) | |
1469 | { | |
1470 | unsigned int bridge; | |
1471 | size_t len; | |
1472 | char* endp; | |
1473 | ||
1474 | while (*p) { | |
1475 | if (!strncmp(p, "64k", 3)) | |
1476 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1477 | else if (!strncmp(p, "128k", 4)) | |
1478 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1479 | else if (!strncmp(p, "256k", 4)) | |
1480 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1481 | else if (!strncmp(p, "512k", 4)) | |
1482 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1483 | else if (!strncmp(p, "1M", 2)) | |
1484 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1485 | else if (!strncmp(p, "2M", 2)) | |
1486 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1487 | else if (!strncmp(p, "4M", 2)) | |
1488 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1489 | else if (!strncmp(p, "8M", 2)) | |
1490 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1491 | ||
1492 | len = strlen("translate_empty_slots"); | |
1493 | if (!strncmp(p, "translate_empty_slots", len)) | |
1494 | translate_empty_slots = 1; | |
1495 | ||
1496 | len = strlen("disable"); | |
1497 | if (!strncmp(p, "disable", len)) { | |
1498 | p += len; | |
1499 | if (*p == '=') | |
1500 | ++p; | |
1501 | if (*p == '\0') | |
1502 | break; | |
1503 | bridge = simple_strtol(p, &endp, 0); | |
1504 | if (p == endp) | |
1505 | break; | |
1506 | ||
d2105b10 | 1507 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1508 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1509 | "translation for PHB %#x\n", bridge); |
f38db651 | 1510 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1511 | } |
1512 | } | |
1513 | ||
1514 | p = strpbrk(p, ","); | |
1515 | if (!p) | |
1516 | break; | |
1517 | ||
1518 | p++; /* skip ',' */ | |
1519 | } | |
1520 | return 1; | |
1521 | } | |
1522 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1523 | |
1524 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1525 | { | |
1526 | struct iommu_table *tbl; | |
1527 | unsigned int npages; | |
1528 | int i; | |
1529 | ||
08f1c192 | 1530 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1531 | |
1532 | for (i = 0; i < 4; i++) { | |
1533 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1534 | ||
1535 | /* Don't give out TCEs that map MEM resources */ | |
1536 | if (!(r->flags & IORESOURCE_MEM)) | |
1537 | continue; | |
1538 | ||
1539 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1540 | if (!r->start) | |
1541 | continue; | |
1542 | ||
1543 | /* cover the whole region */ | |
1544 | npages = (r->end - r->start) >> PAGE_SHIFT; | |
1545 | npages++; | |
1546 | ||
07877cf6 MBY |
1547 | iommu_range_reserve(tbl, r->start, npages); |
1548 | } | |
1549 | } | |
1550 | ||
1551 | static int __init calgary_fixup_tce_spaces(void) | |
1552 | { | |
1553 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1554 | struct calgary_bus_info *info; |
07877cf6 MBY |
1555 | |
1556 | if (no_iommu || swiotlb || !calgary_detected) | |
1557 | return -ENODEV; | |
1558 | ||
12de257b | 1559 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1560 | |
1561 | do { | |
1562 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1563 | if (!dev) | |
1564 | break; | |
1565 | if (!is_cal_pci_dev(dev->device)) | |
1566 | continue; | |
bc3c6058 MBY |
1567 | |
1568 | info = &bus_info[dev->bus->number]; | |
1569 | if (info->translation_disabled) | |
07877cf6 MBY |
1570 | continue; |
1571 | ||
bc3c6058 | 1572 | if (!info->tce_space) |
07877cf6 MBY |
1573 | continue; |
1574 | ||
1575 | calgary_fixup_one_tce_space(dev); | |
1576 | ||
1577 | } while (1); | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
1582 | /* | |
1583 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1584 | * and before device_initcall. | |
1585 | */ | |
1586 | rootfs_initcall(calgary_fixup_tce_spaces); |