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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
95b68dec | 32 | #include <linux/crash_dump.h> |
e465058d | 33 | #include <linux/dma-mapping.h> |
e465058d JM |
34 | #include <linux/bitops.h> |
35 | #include <linux/pci_ids.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
8b87d9f4 | 38 | #include <linux/scatterlist.h> |
1b39b077 | 39 | #include <linux/iommu-helper.h> |
1956a96d | 40 | |
46a7fa27 | 41 | #include <asm/iommu.h> |
e465058d JM |
42 | #include <asm/calgary.h> |
43 | #include <asm/tce.h> | |
44 | #include <asm/pci-direct.h> | |
45 | #include <asm/system.h> | |
46 | #include <asm/dma.h> | |
b34e90b8 | 47 | #include <asm/rio.h> |
ae5830a6 | 48 | #include <asm/bios_ebda.h> |
e465058d | 49 | |
bff6547b MBY |
50 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
51 | int use_calgary __read_mostly = 1; | |
52 | #else | |
53 | int use_calgary __read_mostly = 0; | |
54 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
55 | ||
e465058d | 56 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 57 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 58 | |
e465058d | 59 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
60 | #define CALGARY_CONFIG_REG 0x0108 |
61 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
62 | #define PHB_PLSSR_OFFSET 0x0120 |
63 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
64 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
65 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
66 | #define PHB_MEM_1_LOW 0x0190 | |
67 | #define PHB_MEM_1_HIGH 0x01A0 | |
68 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
69 | #define PHB_MEM_1_SIZE 0x01C0 | |
70 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
71 | #define PHB_AER_OFFSET 0x0200 | |
72 | #define PHB_CONFIG_0_HIGH 0x0220 | |
73 | #define PHB_CONFIG_0_LOW 0x0230 | |
74 | #define PHB_CONFIG_0_END 0x0240 | |
75 | #define PHB_MEM_2_LOW 0x02B0 | |
76 | #define PHB_MEM_2_HIGH 0x02C0 | |
77 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
78 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
79 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
80 | ||
c3860108 | 81 | /* CalIOC2 specific */ |
8bcf7705 MBY |
82 | #define PHB_SAVIOR_L2 0x0DB0 |
83 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
84 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 85 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 86 | |
e465058d JM |
87 | /* PHB_CONFIG_RW */ |
88 | #define PHB_TCE_ENABLE 0x20000000 | |
89 | #define PHB_SLOT_DISABLE 0x1C000000 | |
90 | #define PHB_DAC_DISABLE 0x01000000 | |
91 | #define PHB_MEM2_ENABLE 0x00400000 | |
92 | #define PHB_MCSR_ENABLE 0x00100000 | |
93 | /* TAR (Table Address Register) */ | |
94 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
95 | #define TAR_VALID 0x0000000000000008UL | |
96 | /* CSR (Channel/DMA Status Register) */ | |
97 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 98 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 99 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 100 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
101 | #define PMR_SOFTSTOP 0x80000000 |
102 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
103 | #define PMR_HARDSTOP 0x20000000 | |
e465058d JM |
104 | |
105 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 106 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
107 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
108 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
109 | #define PHBS_PER_CALGARY 4 |
110 | ||
111 | /* register offsets in Calgary's internal register space */ | |
112 | static const unsigned long tar_offsets[] = { | |
113 | 0x0580 /* TAR0 */, | |
114 | 0x0588 /* TAR1 */, | |
115 | 0x0590 /* TAR2 */, | |
116 | 0x0598 /* TAR3 */ | |
117 | }; | |
118 | ||
119 | static const unsigned long split_queue_offsets[] = { | |
120 | 0x4870 /* SPLIT QUEUE 0 */, | |
121 | 0x5870 /* SPLIT QUEUE 1 */, | |
122 | 0x6870 /* SPLIT QUEUE 2 */, | |
123 | 0x7870 /* SPLIT QUEUE 3 */ | |
124 | }; | |
125 | ||
126 | static const unsigned long phb_offsets[] = { | |
127 | 0x8000 /* PHB0 */, | |
128 | 0x9000 /* PHB1 */, | |
129 | 0xA000 /* PHB2 */, | |
130 | 0xB000 /* PHB3 */ | |
131 | }; | |
132 | ||
b34e90b8 LV |
133 | /* PHB debug registers */ |
134 | ||
135 | static const unsigned long phb_debug_offsets[] = { | |
136 | 0x4000 /* PHB 0 DEBUG */, | |
137 | 0x5000 /* PHB 1 DEBUG */, | |
138 | 0x6000 /* PHB 2 DEBUG */, | |
139 | 0x7000 /* PHB 3 DEBUG */ | |
140 | }; | |
141 | ||
142 | /* | |
143 | * STUFF register for each debug PHB, | |
144 | * byte 1 = start bus number, byte 2 = end bus number | |
145 | */ | |
146 | ||
147 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
148 | ||
310adfdd MBY |
149 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
150 | ||
e465058d JM |
151 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
152 | static int translate_empty_slots __read_mostly = 0; | |
153 | static int calgary_detected __read_mostly = 0; | |
154 | ||
b34e90b8 LV |
155 | static struct rio_table_hdr *rio_table_hdr __initdata; |
156 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 157 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 158 | |
f38db651 MBY |
159 | struct calgary_bus_info { |
160 | void *tce_space; | |
0577f148 | 161 | unsigned char translation_disabled; |
f38db651 | 162 | signed char phbid; |
b34e90b8 | 163 | void __iomem *bbar; |
f38db651 MBY |
164 | }; |
165 | ||
ff297b8c MBY |
166 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
167 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 168 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 169 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 170 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 171 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
95b68dec C |
172 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl); |
173 | static void get_tce_space_from_tar(void); | |
ff297b8c MBY |
174 | |
175 | static struct cal_chipset_ops calgary_chip_ops = { | |
176 | .handle_quirks = calgary_handle_quirks, | |
8cb32dc7 MBY |
177 | .tce_cache_blast = calgary_tce_cache_blast, |
178 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 179 | }; |
e465058d | 180 | |
c3860108 MBY |
181 | static struct cal_chipset_ops calioc2_chip_ops = { |
182 | .handle_quirks = calioc2_handle_quirks, | |
8cb32dc7 MBY |
183 | .tce_cache_blast = calioc2_tce_cache_blast, |
184 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
185 | }; |
186 | ||
ff297b8c | 187 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
188 | |
189 | /* enable this to stress test the chip's TCE cache */ | |
190 | #ifdef CONFIG_IOMMU_DEBUG | |
ed65260b | 191 | static int debugging = 1; |
de684652 | 192 | |
796e4390 MBY |
193 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
194 | int expected, unsigned long start, unsigned long end) | |
195 | { | |
196 | unsigned long idx = start; | |
197 | ||
198 | BUG_ON(start >= end); | |
199 | ||
200 | while (idx < end) { | |
201 | if (!!test_bit(idx, bitmap) != expected) | |
202 | return idx; | |
203 | ++idx; | |
204 | } | |
205 | ||
206 | /* all bits have the expected value */ | |
207 | return ~0UL; | |
208 | } | |
de684652 | 209 | #else /* debugging is disabled */ |
ed65260b | 210 | static int debugging; |
de684652 | 211 | |
796e4390 MBY |
212 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
213 | int expected, unsigned long start, unsigned long end) | |
214 | { | |
215 | return ~0UL; | |
216 | } | |
8a244590 | 217 | |
de684652 | 218 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d | 219 | |
d588ba8c MBY |
220 | static inline int translation_enabled(struct iommu_table *tbl) |
221 | { | |
222 | /* only PHBs with translation enabled have an IOMMU table */ | |
223 | return (tbl != NULL); | |
224 | } | |
225 | ||
e465058d | 226 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 227 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
228 | { |
229 | unsigned long index; | |
230 | unsigned long end; | |
796e4390 | 231 | unsigned long badbit; |
820a1497 | 232 | unsigned long flags; |
e465058d JM |
233 | |
234 | index = start_addr >> PAGE_SHIFT; | |
235 | ||
236 | /* bail out if we're asked to reserve a region we don't cover */ | |
237 | if (index >= tbl->it_size) | |
238 | return; | |
239 | ||
240 | end = index + npages; | |
241 | if (end > tbl->it_size) /* don't go off the table */ | |
242 | end = tbl->it_size; | |
243 | ||
820a1497 MBY |
244 | spin_lock_irqsave(&tbl->it_lock, flags); |
245 | ||
796e4390 MBY |
246 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
247 | if (badbit != ~0UL) { | |
248 | if (printk_ratelimit()) | |
e465058d JM |
249 | printk(KERN_ERR "Calgary: entry already allocated at " |
250 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 251 | badbit, tbl, start_addr, npages); |
e465058d | 252 | } |
796e4390 | 253 | |
d26dbc5c | 254 | iommu_area_reserve(tbl->it_map, index, npages); |
820a1497 MBY |
255 | |
256 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
257 | } |
258 | ||
1b39b077 FT |
259 | static unsigned long iommu_range_alloc(struct device *dev, |
260 | struct iommu_table *tbl, | |
261 | unsigned int npages) | |
e465058d | 262 | { |
820a1497 | 263 | unsigned long flags; |
e465058d | 264 | unsigned long offset; |
1b39b077 FT |
265 | unsigned long boundary_size; |
266 | ||
267 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
268 | PAGE_SIZE) >> PAGE_SHIFT; | |
e465058d JM |
269 | |
270 | BUG_ON(npages == 0); | |
271 | ||
820a1497 MBY |
272 | spin_lock_irqsave(&tbl->it_lock, flags); |
273 | ||
1b39b077 FT |
274 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint, |
275 | npages, 0, boundary_size, 0); | |
e465058d | 276 | if (offset == ~0UL) { |
ff297b8c | 277 | tbl->chip_ops->tce_cache_blast(tbl); |
1b39b077 FT |
278 | |
279 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | |
280 | npages, 0, boundary_size, 0); | |
e465058d JM |
281 | if (offset == ~0UL) { |
282 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
820a1497 | 283 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
284 | if (panic_on_overflow) |
285 | panic("Calgary: fix the allocator.\n"); | |
286 | else | |
287 | return bad_dma_address; | |
288 | } | |
289 | } | |
290 | ||
e465058d JM |
291 | tbl->it_hint = offset + npages; |
292 | BUG_ON(tbl->it_hint > tbl->it_size); | |
293 | ||
820a1497 MBY |
294 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
295 | ||
e465058d JM |
296 | return offset; |
297 | } | |
298 | ||
1b39b077 FT |
299 | static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, |
300 | void *vaddr, unsigned int npages, int direction) | |
e465058d | 301 | { |
820a1497 | 302 | unsigned long entry; |
e465058d JM |
303 | dma_addr_t ret = bad_dma_address; |
304 | ||
1b39b077 | 305 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d JM |
306 | |
307 | if (unlikely(entry == bad_dma_address)) | |
308 | goto error; | |
309 | ||
310 | /* set the return dma address */ | |
311 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
312 | ||
313 | /* put the TCEs in the HW table */ | |
314 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
315 | direction); | |
316 | ||
e465058d JM |
317 | return ret; |
318 | ||
319 | error: | |
e465058d JM |
320 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " |
321 | "iommu %p\n", npages, tbl); | |
322 | return bad_dma_address; | |
323 | } | |
324 | ||
3cc39bda | 325 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
326 | unsigned int npages) |
327 | { | |
328 | unsigned long entry; | |
796e4390 | 329 | unsigned long badbit; |
310adfdd | 330 | unsigned long badend; |
820a1497 | 331 | unsigned long flags; |
310adfdd MBY |
332 | |
333 | /* were we called with bad_dma_address? */ | |
334 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
335 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
bde78a79 | 336 | WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA " |
310adfdd | 337 | "address 0x%Lx\n", dma_addr); |
310adfdd MBY |
338 | return; |
339 | } | |
e465058d JM |
340 | |
341 | entry = dma_addr >> PAGE_SHIFT; | |
342 | ||
343 | BUG_ON(entry + npages > tbl->it_size); | |
344 | ||
345 | tce_free(tbl, entry, npages); | |
346 | ||
820a1497 MBY |
347 | spin_lock_irqsave(&tbl->it_lock, flags); |
348 | ||
796e4390 MBY |
349 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
350 | if (badbit != ~0UL) { | |
351 | if (printk_ratelimit()) | |
e465058d JM |
352 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
353 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 354 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
355 | } |
356 | ||
1b39b077 | 357 | iommu_area_free(tbl->it_map, entry, npages); |
820a1497 MBY |
358 | |
359 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
360 | } |
361 | ||
35b6dfa0 MBY |
362 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
363 | { | |
8a244590 MBY |
364 | struct pci_dev *pdev; |
365 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
366 | struct iommu_table *tbl; |
367 | ||
8a244590 MBY |
368 | pdev = to_pci_dev(dev); |
369 | ||
f055a061 MFB |
370 | pbus = pdev->bus; |
371 | ||
372 | /* is the device behind a bridge? Look for the root bus */ | |
373 | while (pbus->parent) | |
374 | pbus = pbus->parent; | |
8a244590 | 375 | |
08f1c192 | 376 | tbl = pci_iommu(pbus); |
7354b075 | 377 | |
f055a061 | 378 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
379 | |
380 | return tbl; | |
381 | } | |
382 | ||
3cc39bda | 383 | static void calgary_unmap_sg(struct device *dev, |
e465058d JM |
384 | struct scatterlist *sglist, int nelems, int direction) |
385 | { | |
3cc39bda | 386 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
387 | struct scatterlist *s; |
388 | int i; | |
3cc39bda | 389 | |
bc3c6058 | 390 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
391 | return; |
392 | ||
8b87d9f4 | 393 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 394 | unsigned int npages; |
8b87d9f4 JA |
395 | dma_addr_t dma = s->dma_address; |
396 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
397 | |
398 | if (dmalen == 0) | |
399 | break; | |
400 | ||
036b4c50 | 401 | npages = iommu_num_pages(dma, dmalen, PAGE_SIZE); |
3cc39bda | 402 | iommu_free(tbl, dma, npages); |
e465058d JM |
403 | } |
404 | } | |
405 | ||
0b11e1c6 | 406 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
e465058d JM |
407 | int nelems, int direction) |
408 | { | |
35b6dfa0 | 409 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 410 | struct scatterlist *s; |
e465058d JM |
411 | unsigned long vaddr; |
412 | unsigned int npages; | |
413 | unsigned long entry; | |
414 | int i; | |
415 | ||
8b87d9f4 | 416 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 417 | BUG_ON(!sg_page(s)); |
e465058d | 418 | |
58b053e4 | 419 | vaddr = (unsigned long) sg_virt(s); |
036b4c50 | 420 | npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE); |
e465058d | 421 | |
1b39b077 | 422 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d JM |
423 | if (entry == bad_dma_address) { |
424 | /* makes sure unmap knows to stop */ | |
425 | s->dma_length = 0; | |
426 | goto error; | |
427 | } | |
428 | ||
429 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
430 | ||
431 | /* insert into HW table */ | |
432 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
433 | direction); | |
434 | ||
435 | s->dma_length = s->length; | |
436 | } | |
437 | ||
e465058d JM |
438 | return nelems; |
439 | error: | |
3cc39bda | 440 | calgary_unmap_sg(dev, sg, nelems, direction); |
8b87d9f4 JA |
441 | for_each_sg(sg, s, nelems, i) { |
442 | sg->dma_address = bad_dma_address; | |
443 | sg->dma_length = 0; | |
e465058d | 444 | } |
e465058d JM |
445 | return 0; |
446 | } | |
447 | ||
2be62149 | 448 | static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr, |
e465058d JM |
449 | size_t size, int direction) |
450 | { | |
2be62149 | 451 | void *vaddr = phys_to_virt(paddr); |
e465058d JM |
452 | unsigned long uaddr; |
453 | unsigned int npages; | |
35b6dfa0 | 454 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
455 | |
456 | uaddr = (unsigned long)vaddr; | |
036b4c50 | 457 | npages = iommu_num_pages(uaddr, size, PAGE_SIZE); |
e465058d | 458 | |
1956a96d | 459 | return iommu_alloc(dev, tbl, vaddr, npages, direction); |
e465058d JM |
460 | } |
461 | ||
0b11e1c6 | 462 | static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, |
e465058d JM |
463 | size_t size, int direction) |
464 | { | |
35b6dfa0 | 465 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
466 | unsigned int npages; |
467 | ||
036b4c50 | 468 | npages = iommu_num_pages(dma_handle, size, PAGE_SIZE); |
e465058d JM |
469 | iommu_free(tbl, dma_handle, npages); |
470 | } | |
471 | ||
0b11e1c6 | 472 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
e465058d JM |
473 | dma_addr_t *dma_handle, gfp_t flag) |
474 | { | |
475 | void *ret = NULL; | |
476 | dma_addr_t mapping; | |
477 | unsigned int npages, order; | |
35b6dfa0 | 478 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
479 | |
480 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
481 | npages = size >> PAGE_SHIFT; | |
482 | order = get_order(size); | |
483 | ||
f10ac8a2 FT |
484 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
485 | ||
e465058d JM |
486 | /* alloc enough pages (and possibly more) */ |
487 | ret = (void *)__get_free_pages(flag, order); | |
488 | if (!ret) | |
489 | goto error; | |
490 | memset(ret, 0, size); | |
491 | ||
1956a96d AB |
492 | /* set up tces to cover the allocated range */ |
493 | mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL); | |
494 | if (mapping == bad_dma_address) | |
495 | goto free; | |
496 | *dma_handle = mapping; | |
e465058d | 497 | return ret; |
e465058d JM |
498 | free: |
499 | free_pages((unsigned long)ret, get_order(size)); | |
500 | ret = NULL; | |
501 | error: | |
502 | return ret; | |
503 | } | |
504 | ||
e4ad68b6 JR |
505 | static void calgary_free_coherent(struct device *dev, size_t size, |
506 | void *vaddr, dma_addr_t dma_handle) | |
507 | { | |
508 | unsigned int npages; | |
509 | struct iommu_table *tbl = find_iommu_table(dev); | |
510 | ||
511 | size = PAGE_ALIGN(size); | |
512 | npages = size >> PAGE_SHIFT; | |
513 | ||
514 | iommu_free(tbl, dma_handle, npages); | |
515 | free_pages((unsigned long)vaddr, get_order(size)); | |
516 | } | |
517 | ||
8d8bb39b | 518 | static struct dma_mapping_ops calgary_dma_ops = { |
e465058d | 519 | .alloc_coherent = calgary_alloc_coherent, |
e4ad68b6 | 520 | .free_coherent = calgary_free_coherent, |
e465058d JM |
521 | .map_single = calgary_map_single, |
522 | .unmap_single = calgary_unmap_single, | |
523 | .map_sg = calgary_map_sg, | |
524 | .unmap_sg = calgary_unmap_sg, | |
525 | }; | |
526 | ||
b34e90b8 LV |
527 | static inline void __iomem * busno_to_bbar(unsigned char num) |
528 | { | |
529 | return bus_info[num].bbar; | |
530 | } | |
531 | ||
e465058d JM |
532 | static inline int busno_to_phbid(unsigned char num) |
533 | { | |
f38db651 | 534 | return bus_info[num].phbid; |
e465058d JM |
535 | } |
536 | ||
537 | static inline unsigned long split_queue_offset(unsigned char num) | |
538 | { | |
539 | size_t idx = busno_to_phbid(num); | |
540 | ||
541 | return split_queue_offsets[idx]; | |
542 | } | |
543 | ||
544 | static inline unsigned long tar_offset(unsigned char num) | |
545 | { | |
546 | size_t idx = busno_to_phbid(num); | |
547 | ||
548 | return tar_offsets[idx]; | |
549 | } | |
550 | ||
551 | static inline unsigned long phb_offset(unsigned char num) | |
552 | { | |
553 | size_t idx = busno_to_phbid(num); | |
554 | ||
555 | return phb_offsets[idx]; | |
556 | } | |
557 | ||
558 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
559 | { | |
560 | unsigned long target = ((unsigned long)bar) | offset; | |
561 | return (void __iomem*)target; | |
562 | } | |
563 | ||
8a244590 MBY |
564 | static inline int is_calioc2(unsigned short device) |
565 | { | |
566 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
567 | } | |
568 | ||
569 | static inline int is_calgary(unsigned short device) | |
570 | { | |
571 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
572 | } | |
573 | ||
574 | static inline int is_cal_pci_dev(unsigned short device) | |
575 | { | |
576 | return (is_calgary(device) || is_calioc2(device)); | |
577 | } | |
578 | ||
ff297b8c | 579 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
580 | { |
581 | u64 val; | |
582 | u32 aer; | |
583 | int i = 0; | |
584 | void __iomem *bbar = tbl->bbar; | |
585 | void __iomem *target; | |
586 | ||
587 | /* disable arbitration on the bus */ | |
588 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
589 | aer = readl(target); | |
590 | writel(0, target); | |
591 | ||
592 | /* read plssr to ensure it got there */ | |
593 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
594 | val = readl(target); | |
595 | ||
596 | /* poll split queues until all DMA activity is done */ | |
597 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
598 | do { | |
599 | val = readq(target); | |
600 | i++; | |
601 | } while ((val & 0xff) != 0xff && i < 100); | |
602 | if (i == 100) | |
603 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
604 | "continuing anyway\n"); | |
605 | ||
606 | /* invalidate TCE cache */ | |
607 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
608 | writeq(tbl->tar_val, target); | |
609 | ||
610 | /* enable arbitration */ | |
611 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
612 | writel(aer, target); | |
613 | (void)readl(target); /* flush */ | |
614 | } | |
615 | ||
00be3fa4 MBY |
616 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
617 | { | |
618 | void __iomem *bbar = tbl->bbar; | |
619 | void __iomem *target; | |
620 | u64 val64; | |
621 | u32 val; | |
622 | int i = 0; | |
623 | int count = 1; | |
624 | unsigned char bus = tbl->it_busno; | |
625 | ||
626 | begin: | |
627 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
628 | "sequence - count %d\n", bus, count); | |
629 | ||
630 | /* 1. using the Page Migration Control reg set SoftStop */ | |
631 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
632 | val = be32_to_cpu(readl(target)); | |
633 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
634 | val |= PMR_SOFTSTOP; | |
635 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
636 | writel(cpu_to_be32(val), target); | |
637 | ||
638 | /* 2. poll split queues until all DMA activity is done */ | |
639 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
640 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
641 | do { | |
642 | val64 = readq(target); | |
643 | i++; | |
644 | } while ((val64 & 0xff) != 0xff && i < 100); | |
645 | if (i == 100) | |
646 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | |
647 | "continuing anyway\n"); | |
648 | ||
649 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
650 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
651 | val = be32_to_cpu(readl(target)); | |
652 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
653 | ||
654 | /* 4. if SoftStopFault - goto (1) */ | |
655 | if (val & PMR_SOFTSTOPFAULT) { | |
656 | if (++count < 100) | |
657 | goto begin; | |
658 | else { | |
659 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | |
660 | "aborting TCE cache flush sequence!\n"); | |
661 | return; /* pray for the best */ | |
662 | } | |
663 | } | |
664 | ||
665 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
666 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
667 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
668 | val = be32_to_cpu(readl(target)); | |
669 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
670 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
671 | val = be32_to_cpu(readl(target)); | |
672 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
673 | ||
674 | /* 6. invalidate TCE cache */ | |
675 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
676 | target = calgary_reg(bbar, tar_offset(bus)); | |
677 | writeq(tbl->tar_val, target); | |
678 | ||
679 | /* 7. Re-read PMCR */ | |
680 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
681 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
682 | val = be32_to_cpu(readl(target)); | |
683 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
684 | ||
685 | /* 8. Remove HardStop */ | |
686 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
687 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
688 | val = 0; | |
689 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
690 | writel(cpu_to_be32(val), target); | |
691 | val = be32_to_cpu(readl(target)); | |
692 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
693 | } | |
694 | ||
e465058d JM |
695 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
696 | u64 limit) | |
697 | { | |
698 | unsigned int numpages; | |
699 | ||
700 | limit = limit | 0xfffff; | |
701 | limit++; | |
702 | ||
703 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 704 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
705 | } |
706 | ||
707 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
708 | { | |
709 | void __iomem *target; | |
710 | u64 low, high, sizelow; | |
711 | u64 start, limit; | |
08f1c192 | 712 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
713 | unsigned char busnum = dev->bus->number; |
714 | void __iomem *bbar = tbl->bbar; | |
715 | ||
716 | /* peripheral MEM_1 region */ | |
717 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
718 | low = be32_to_cpu(readl(target)); | |
719 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
720 | high = be32_to_cpu(readl(target)); | |
721 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
722 | sizelow = be32_to_cpu(readl(target)); | |
723 | ||
724 | start = (high << 32) | low; | |
725 | limit = sizelow; | |
726 | ||
727 | calgary_reserve_mem_region(dev, start, limit); | |
728 | } | |
729 | ||
730 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
731 | { | |
732 | void __iomem *target; | |
733 | u32 val32; | |
734 | u64 low, high, sizelow, sizehigh; | |
735 | u64 start, limit; | |
08f1c192 | 736 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
737 | unsigned char busnum = dev->bus->number; |
738 | void __iomem *bbar = tbl->bbar; | |
739 | ||
740 | /* is it enabled? */ | |
741 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
742 | val32 = be32_to_cpu(readl(target)); | |
743 | if (!(val32 & PHB_MEM2_ENABLE)) | |
744 | return; | |
745 | ||
746 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
747 | low = be32_to_cpu(readl(target)); | |
748 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
749 | high = be32_to_cpu(readl(target)); | |
750 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
751 | sizelow = be32_to_cpu(readl(target)); | |
752 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
753 | sizehigh = be32_to_cpu(readl(target)); | |
754 | ||
755 | start = (high << 32) | low; | |
756 | limit = (sizehigh << 32) | sizelow; | |
757 | ||
758 | calgary_reserve_mem_region(dev, start, limit); | |
759 | } | |
760 | ||
761 | /* | |
762 | * some regions of the IO address space do not get translated, so we | |
763 | * must not give devices IO addresses in those regions. The regions | |
764 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
765 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
766 | * later. | |
767 | */ | |
768 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
769 | { | |
770 | unsigned int npages; | |
e465058d | 771 | u64 start; |
08f1c192 | 772 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 773 | |
310adfdd MBY |
774 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
775 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
776 | |
777 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 778 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
779 | if (is_calgary(dev->device)) { |
780 | start = (640 * 1024); | |
781 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
782 | } else { /* calioc2 */ | |
783 | start = 0; | |
e8f20414 | 784 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 785 | } |
e465058d JM |
786 | iommu_range_reserve(tbl, start, npages); |
787 | ||
788 | /* reserve the two PCI peripheral memory regions in IO space */ | |
789 | calgary_reserve_peripheral_mem_1(dev); | |
790 | calgary_reserve_peripheral_mem_2(dev); | |
791 | } | |
792 | ||
793 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
794 | { | |
795 | u64 val64; | |
796 | u64 table_phys; | |
797 | void __iomem *target; | |
798 | int ret; | |
799 | struct iommu_table *tbl; | |
800 | ||
801 | /* build TCE tables for each PHB */ | |
802 | ret = build_tce_table(dev, bbar); | |
803 | if (ret) | |
804 | return ret; | |
805 | ||
08f1c192 | 806 | tbl = pci_iommu(dev->bus); |
f38db651 | 807 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
95b68dec C |
808 | |
809 | if (is_kdump_kernel()) | |
810 | calgary_init_bitmap_from_tce_table(tbl); | |
811 | else | |
812 | tce_free(tbl, 0, tbl->it_size); | |
f38db651 | 813 | |
8bcf7705 MBY |
814 | if (is_calgary(dev->device)) |
815 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
816 | else if (is_calioc2(dev->device)) |
817 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
818 | else |
819 | BUG(); | |
ff297b8c | 820 | |
e465058d JM |
821 | calgary_reserve_regions(dev); |
822 | ||
823 | /* set TARs for each PHB */ | |
824 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
825 | val64 = be64_to_cpu(readq(target)); | |
826 | ||
827 | /* zero out all TAR bits under sw control */ | |
828 | val64 &= ~TAR_SW_BITS; | |
e465058d | 829 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 830 | |
e465058d JM |
831 | val64 |= table_phys; |
832 | ||
833 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
834 | val64 |= (u64) specified_table_size; | |
835 | ||
836 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 837 | |
e465058d JM |
838 | writeq(tbl->tar_val, target); |
839 | readq(target); /* flush */ | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
b8f4fe66 | 844 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
845 | { |
846 | u64 val64; | |
08f1c192 | 847 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 848 | void __iomem *target; |
b8f4fe66 | 849 | unsigned int bitmapsz; |
e465058d JM |
850 | |
851 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
852 | val64 = be64_to_cpu(readq(target)); | |
853 | val64 &= ~TAR_SW_BITS; | |
854 | writeq(cpu_to_be64(val64), target); | |
855 | readq(target); /* flush */ | |
856 | ||
b8f4fe66 MBY |
857 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
858 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
859 | tbl->it_map = NULL; | |
860 | ||
e465058d | 861 | kfree(tbl); |
08f1c192 MBY |
862 | |
863 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
864 | |
865 | /* Can't free bootmem allocated memory after system is up :-( */ | |
866 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
867 | } |
868 | ||
8a244590 MBY |
869 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
870 | { | |
871 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 872 | void __iomem *target; |
ddbd41b4 | 873 | u32 csr, plssr; |
8cb32dc7 MBY |
874 | |
875 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
876 | csr = be32_to_cpu(readl(target)); |
877 | ||
878 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
879 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
880 | |
881 | /* If no error, the agent ID in the CSR is not valid */ | |
882 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | |
ddbd41b4 | 883 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); |
8cb32dc7 MBY |
884 | } |
885 | ||
886 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
887 | { | |
888 | void __iomem *bbar = tbl->bbar; | |
889 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
890 | void __iomem *target; |
891 | unsigned long phboff = phb_offset(tbl->it_busno); | |
892 | unsigned long erroff; | |
893 | u32 errregs[7]; | |
894 | int i; | |
895 | ||
896 | /* dump CSR */ | |
897 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
898 | csr = be32_to_cpu(readl(target)); | |
899 | /* dump PLSSR */ | |
900 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
901 | plssr = be32_to_cpu(readl(target)); | |
902 | /* dump CSMR */ | |
903 | target = calgary_reg(bbar, phboff | 0x290); | |
904 | csmr = be32_to_cpu(readl(target)); | |
905 | /* dump mck */ | |
906 | target = calgary_reg(bbar, phboff | 0x800); | |
907 | mck = be32_to_cpu(readl(target)); | |
908 | ||
8cb32dc7 MBY |
909 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", |
910 | tbl->it_busno); | |
911 | ||
912 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | |
913 | csr, plssr, csmr, mck); | |
8a244590 MBY |
914 | |
915 | /* dump rest of error regs */ | |
916 | printk(KERN_EMERG "Calgary: "); | |
917 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
7354b075 MBY |
918 | /* err regs are at 0x810 - 0x870 */ |
919 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
920 | target = calgary_reg(bbar, phboff | erroff); |
921 | errregs[i] = be32_to_cpu(readl(target)); | |
922 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
923 | } | |
924 | printk("\n"); | |
8cb32dc7 MBY |
925 | |
926 | /* root complex status */ | |
927 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
928 | rcstat = be32_to_cpu(readl(target)); | |
929 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
930 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
931 | } |
932 | ||
e465058d JM |
933 | static void calgary_watchdog(unsigned long data) |
934 | { | |
935 | struct pci_dev *dev = (struct pci_dev *)data; | |
08f1c192 | 936 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
937 | void __iomem *bbar = tbl->bbar; |
938 | u32 val32; | |
939 | void __iomem *target; | |
940 | ||
941 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
942 | val32 = be32_to_cpu(readl(target)); | |
943 | ||
944 | /* If no error, the agent ID in the CSR is not valid */ | |
945 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 946 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
947 | |
948 | /* reset error */ | |
e465058d JM |
949 | writel(0, target); |
950 | ||
951 | /* Disable bus that caused the error */ | |
952 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 953 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
954 | val32 = be32_to_cpu(readl(target)); |
955 | val32 |= PHB_SLOT_DISABLE; | |
956 | writel(cpu_to_be32(val32), target); | |
957 | readl(target); /* flush */ | |
958 | } else { | |
959 | /* Reset the timer */ | |
960 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
961 | } | |
962 | } | |
963 | ||
a2b663f6 MBY |
964 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
965 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
966 | { |
967 | u64 val64; | |
968 | void __iomem *target; | |
58db8548 | 969 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
970 | u64 mask; |
971 | ||
972 | switch (busno_to_phbid(busnum)) { | |
973 | case 0: phb_shift = (63 - 19); | |
974 | break; | |
975 | case 1: phb_shift = (63 - 23); | |
976 | break; | |
977 | case 2: phb_shift = (63 - 27); | |
978 | break; | |
979 | case 3: phb_shift = (63 - 35); | |
980 | break; | |
981 | default: | |
982 | BUG_ON(busno_to_phbid(busnum)); | |
983 | } | |
984 | ||
985 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
986 | val64 = be64_to_cpu(readq(target)); | |
987 | ||
988 | /* zero out this PHB's timer bits */ | |
989 | mask = ~(0xFUL << phb_shift); | |
990 | val64 &= mask; | |
a2b663f6 | 991 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
992 | writeq(cpu_to_be64(val64), target); |
993 | readq(target); /* flush */ | |
994 | } | |
995 | ||
31f3dff6 | 996 | static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
c3860108 MBY |
997 | { |
998 | unsigned char busnum = dev->bus->number; | |
999 | void __iomem *bbar = tbl->bbar; | |
1000 | void __iomem *target; | |
1001 | u32 val; | |
1002 | ||
8bcf7705 MBY |
1003 | /* |
1004 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
1005 | */ | |
1006 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
1007 | val = cpu_to_be32(readl(target)); | |
1008 | val |= 0x00800000; | |
1009 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
1010 | } |
1011 | ||
31f3dff6 | 1012 | static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
b8d2ea1b MBY |
1013 | { |
1014 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
1015 | |
1016 | /* | |
1017 | * Give split completion a longer timeout on bus 1 for aic94xx | |
1018 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
1019 | */ | |
c3860108 | 1020 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
1021 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
1022 | CCR_2SEC_TIMEOUT); | |
1023 | } | |
1024 | ||
e465058d JM |
1025 | static void __init calgary_enable_translation(struct pci_dev *dev) |
1026 | { | |
1027 | u32 val32; | |
1028 | unsigned char busnum; | |
1029 | void __iomem *target; | |
1030 | void __iomem *bbar; | |
1031 | struct iommu_table *tbl; | |
1032 | ||
1033 | busnum = dev->bus->number; | |
08f1c192 | 1034 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1035 | bbar = tbl->bbar; |
1036 | ||
1037 | /* enable TCE in PHB Config Register */ | |
1038 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1039 | val32 = be32_to_cpu(readl(target)); | |
1040 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
1041 | ||
8a244590 MBY |
1042 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
1043 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
1044 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1045 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1046 | "bus.\n"); | |
1047 | ||
1048 | writel(cpu_to_be32(val32), target); | |
1049 | readl(target); /* flush */ | |
1050 | ||
1051 | init_timer(&tbl->watchdog_timer); | |
1052 | tbl->watchdog_timer.function = &calgary_watchdog; | |
1053 | tbl->watchdog_timer.data = (unsigned long)dev; | |
1054 | mod_timer(&tbl->watchdog_timer, jiffies); | |
1055 | } | |
1056 | ||
1057 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1058 | { | |
1059 | u32 val32; | |
1060 | unsigned char busnum; | |
1061 | void __iomem *target; | |
1062 | void __iomem *bbar; | |
1063 | struct iommu_table *tbl; | |
1064 | ||
1065 | busnum = dev->bus->number; | |
08f1c192 | 1066 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1067 | bbar = tbl->bbar; |
1068 | ||
1069 | /* disable TCE in PHB Config Register */ | |
1070 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1071 | val32 = be32_to_cpu(readl(target)); | |
1072 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1073 | ||
70d666d6 | 1074 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1075 | writel(cpu_to_be32(val32), target); |
1076 | readl(target); /* flush */ | |
1077 | ||
1078 | del_timer_sync(&tbl->watchdog_timer); | |
1079 | } | |
1080 | ||
a4fc520a | 1081 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1082 | { |
871b1700 | 1083 | pci_dev_get(dev); |
08f1c192 | 1084 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1085 | |
1086 | /* is the device behind a bridge? */ | |
1087 | if (dev->bus->parent) | |
1088 | dev->bus->parent->self = dev; | |
1089 | else | |
1090 | dev->bus->self = dev; | |
e465058d JM |
1091 | } |
1092 | ||
1093 | static int __init calgary_init_one(struct pci_dev *dev) | |
1094 | { | |
e465058d | 1095 | void __iomem *bbar; |
ff297b8c | 1096 | struct iommu_table *tbl; |
e465058d JM |
1097 | int ret; |
1098 | ||
dedc9937 JM |
1099 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1100 | ||
eae93755 | 1101 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1102 | ret = calgary_setup_tar(dev, bbar); |
1103 | if (ret) | |
eae93755 | 1104 | goto done; |
e465058d | 1105 | |
871b1700 | 1106 | pci_dev_get(dev); |
8a244590 MBY |
1107 | |
1108 | if (dev->bus->parent) { | |
1109 | if (dev->bus->parent->self) | |
1110 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1111 | "bus->parent->self!\n", dev); | |
1112 | dev->bus->parent->self = dev; | |
1113 | } else | |
1114 | dev->bus->self = dev; | |
b8d2ea1b | 1115 | |
08f1c192 | 1116 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1117 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1118 | |
e465058d JM |
1119 | calgary_enable_translation(dev); |
1120 | ||
1121 | return 0; | |
1122 | ||
e465058d JM |
1123 | done: |
1124 | return ret; | |
1125 | } | |
1126 | ||
eae93755 | 1127 | static int __init calgary_locate_bbars(void) |
e465058d | 1128 | { |
eae93755 MBY |
1129 | int ret; |
1130 | int rioidx, phb, bus; | |
b34e90b8 LV |
1131 | void __iomem *bbar; |
1132 | void __iomem *target; | |
eae93755 | 1133 | unsigned long offset; |
b34e90b8 LV |
1134 | u8 start_bus, end_bus; |
1135 | u32 val; | |
1136 | ||
eae93755 MBY |
1137 | ret = -ENODATA; |
1138 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1139 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1140 | |
eae93755 | 1141 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1142 | continue; |
1143 | ||
1144 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1145 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1146 | if (!bbar) | |
1147 | goto error; | |
b34e90b8 LV |
1148 | |
1149 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1150 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1151 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1152 | |
b34e90b8 | 1153 | val = be32_to_cpu(readl(target)); |
8a244590 | 1154 | |
b34e90b8 | 1155 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1156 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1157 | |
1158 | if (end_bus) { | |
1159 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1160 | bus_info[bus].bbar = bbar; | |
1161 | bus_info[bus].phbid = phb; | |
1162 | } | |
1163 | } else { | |
1164 | bus_info[start_bus].bbar = bbar; | |
1165 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1166 | } |
1167 | } | |
1168 | } | |
1169 | ||
eae93755 MBY |
1170 | return 0; |
1171 | ||
1172 | error: | |
1173 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1174 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1175 | if (bus_info[bus].bbar) | |
1176 | iounmap(bus_info[bus].bbar); | |
1177 | ||
1178 | return ret; | |
1179 | } | |
1180 | ||
1181 | static int __init calgary_init(void) | |
1182 | { | |
1183 | int ret; | |
1184 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1185 | struct calgary_bus_info *info; |
eae93755 MBY |
1186 | |
1187 | ret = calgary_locate_bbars(); | |
1188 | if (ret) | |
1189 | return ret; | |
e465058d | 1190 | |
95b68dec C |
1191 | /* Purely for kdump kernel case */ |
1192 | if (is_kdump_kernel()) | |
1193 | get_tce_space_from_tar(); | |
1194 | ||
dedc9937 | 1195 | do { |
8a244590 | 1196 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1197 | if (!dev) |
1198 | break; | |
8a244590 MBY |
1199 | if (!is_cal_pci_dev(dev->device)) |
1200 | continue; | |
bc3c6058 MBY |
1201 | |
1202 | info = &bus_info[dev->bus->number]; | |
1203 | if (info->translation_disabled) { | |
e465058d JM |
1204 | calgary_init_one_nontraslated(dev); |
1205 | continue; | |
1206 | } | |
bc3c6058 MBY |
1207 | |
1208 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1209 | continue; |
12de257b | 1210 | |
e465058d JM |
1211 | ret = calgary_init_one(dev); |
1212 | if (ret) | |
1213 | goto error; | |
dedc9937 | 1214 | } while (1); |
e465058d | 1215 | |
1956a96d AB |
1216 | dev = NULL; |
1217 | for_each_pci_dev(dev) { | |
1218 | struct iommu_table *tbl; | |
1219 | ||
1220 | tbl = find_iommu_table(&dev->dev); | |
1221 | ||
1222 | if (translation_enabled(tbl)) | |
1223 | dev->dev.archdata.dma_ops = &calgary_dma_ops; | |
1224 | } | |
1225 | ||
e465058d JM |
1226 | return ret; |
1227 | ||
1228 | error: | |
dedc9937 | 1229 | do { |
a2b5d877 | 1230 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
9f2dc46d MBY |
1231 | if (!dev) |
1232 | break; | |
8a244590 MBY |
1233 | if (!is_cal_pci_dev(dev->device)) |
1234 | continue; | |
bc3c6058 MBY |
1235 | |
1236 | info = &bus_info[dev->bus->number]; | |
1237 | if (info->translation_disabled) { | |
e465058d JM |
1238 | pci_dev_put(dev); |
1239 | continue; | |
1240 | } | |
bc3c6058 | 1241 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1242 | continue; |
871b1700 | 1243 | |
e465058d | 1244 | calgary_disable_translation(dev); |
b8f4fe66 | 1245 | calgary_free_bus(dev); |
871b1700 | 1246 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
1956a96d | 1247 | dev->dev.archdata.dma_ops = NULL; |
dedc9937 | 1248 | } while (1); |
e465058d JM |
1249 | |
1250 | return ret; | |
1251 | } | |
1252 | ||
1253 | static inline int __init determine_tce_table_size(u64 ram) | |
1254 | { | |
1255 | int ret; | |
1256 | ||
1257 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1258 | return specified_table_size; | |
1259 | ||
1260 | /* | |
1261 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1262 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1263 | * larger table size has twice as many entries, so shift the | |
1264 | * max ram address by 13 to divide by 8K and then look at the | |
1265 | * order of the result to choose between 0-7. | |
1266 | */ | |
1267 | ret = get_order(ram >> 13); | |
1268 | if (ret > TCE_TABLE_SIZE_8M) | |
1269 | ret = TCE_TABLE_SIZE_8M; | |
1270 | ||
1271 | return ret; | |
1272 | } | |
1273 | ||
b34e90b8 LV |
1274 | static int __init build_detail_arrays(void) |
1275 | { | |
1276 | unsigned long ptr; | |
85d57797 DH |
1277 | unsigned numnodes, i; |
1278 | int scal_detail_size, rio_detail_size; | |
b34e90b8 | 1279 | |
85d57797 DH |
1280 | numnodes = rio_table_hdr->num_scal_dev; |
1281 | if (numnodes > MAX_NUMNODES){ | |
b34e90b8 | 1282 | printk(KERN_WARNING |
eae93755 | 1283 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 | 1284 | "but system has %d nodes.\n", |
85d57797 | 1285 | MAX_NUMNODES, numnodes); |
b34e90b8 LV |
1286 | return -ENODEV; |
1287 | } | |
1288 | ||
1289 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1290 | case 2: |
1291 | scal_detail_size = 11; | |
1292 | rio_detail_size = 13; | |
1293 | break; | |
1294 | case 3: | |
1295 | scal_detail_size = 12; | |
1296 | rio_detail_size = 15; | |
1297 | break; | |
eae93755 MBY |
1298 | default: |
1299 | printk(KERN_WARNING | |
1300 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1301 | rio_table_hdr->version); | |
1302 | return -EPROTO; | |
b34e90b8 LV |
1303 | } |
1304 | ||
1305 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
85d57797 | 1306 | for (i = 0; i < numnodes; i++, ptr += scal_detail_size) |
b34e90b8 LV |
1307 | scal_devs[i] = (struct scal_detail *)ptr; |
1308 | ||
1309 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1310 | i++, ptr += rio_detail_size) | |
1311 | rio_devs[i] = (struct rio_detail *)ptr; | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
8a244590 | 1316 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1317 | { |
8a244590 | 1318 | int dev; |
e465058d | 1319 | u32 val; |
8a244590 MBY |
1320 | |
1321 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1322 | /* | |
1323 | * FIXME: properly scan for devices accross the | |
1324 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1325 | */ | |
1326 | return 1; | |
1327 | } | |
1328 | ||
1329 | for (dev = 1; dev < 8; dev++) { | |
1330 | val = read_pci_config(bus, dev, 0, 0); | |
1331 | if (val != 0xffffffff) | |
1332 | break; | |
1333 | } | |
1334 | return (val != 0xffffffff); | |
1335 | } | |
1336 | ||
95b68dec C |
1337 | /* |
1338 | * calgary_init_bitmap_from_tce_table(): | |
1339 | * Funtion for kdump case. In the second/kdump kernel initialize | |
1340 | * the bitmap based on the tce table entries obtained from first kernel | |
1341 | */ | |
1342 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl) | |
1343 | { | |
1344 | u64 *tp; | |
1345 | unsigned int index; | |
1346 | tp = ((u64 *)tbl->it_base); | |
1347 | for (index = 0 ; index < tbl->it_size; index++) { | |
1348 | if (*tp != 0x0) | |
1349 | set_bit(index, tbl->it_map); | |
1350 | tp++; | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | /* | |
1355 | * get_tce_space_from_tar(): | |
1356 | * Function for kdump case. Get the tce tables from first kernel | |
1357 | * by reading the contents of the base adress register of calgary iommu | |
1358 | */ | |
f7106662 | 1359 | static void __init get_tce_space_from_tar(void) |
95b68dec C |
1360 | { |
1361 | int bus; | |
1362 | void __iomem *target; | |
1363 | unsigned long tce_space; | |
1364 | ||
1365 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { | |
1366 | struct calgary_bus_info *info = &bus_info[bus]; | |
1367 | unsigned short pci_device; | |
1368 | u32 val; | |
1369 | ||
1370 | val = read_pci_config(bus, 0, 0, 0); | |
1371 | pci_device = (val & 0xFFFF0000) >> 16; | |
1372 | ||
1373 | if (!is_cal_pci_dev(pci_device)) | |
1374 | continue; | |
1375 | if (info->translation_disabled) | |
1376 | continue; | |
1377 | ||
1378 | if (calgary_bus_has_devices(bus, pci_device) || | |
1379 | translate_empty_slots) { | |
1380 | target = calgary_reg(bus_info[bus].bbar, | |
1381 | tar_offset(bus)); | |
1382 | tce_space = be64_to_cpu(readq(target)); | |
1383 | tce_space = tce_space & TAR_SW_BITS; | |
1384 | ||
1385 | tce_space = tce_space & (~specified_table_size); | |
1386 | info->tce_space = (u64 *)__va(tce_space); | |
1387 | } | |
1388 | } | |
1389 | return; | |
1390 | } | |
1391 | ||
8a244590 MBY |
1392 | void __init detect_calgary(void) |
1393 | { | |
d2105b10 | 1394 | int bus; |
e465058d | 1395 | void *tbl; |
d2105b10 | 1396 | int calgary_found = 0; |
b34e90b8 | 1397 | unsigned long ptr; |
136f1e7a | 1398 | unsigned int offset, prev_offset; |
eae93755 | 1399 | int ret; |
e465058d JM |
1400 | |
1401 | /* | |
1402 | * if the user specified iommu=off or iommu=soft or we found | |
1403 | * another HW IOMMU already, bail out. | |
1404 | */ | |
1405 | if (swiotlb || no_iommu || iommu_detected) | |
1406 | return; | |
1407 | ||
bff6547b MBY |
1408 | if (!use_calgary) |
1409 | return; | |
1410 | ||
0637a70a AK |
1411 | if (!early_pci_allowed()) |
1412 | return; | |
1413 | ||
b92cc559 MBY |
1414 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1415 | ||
b34e90b8 LV |
1416 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1417 | ||
1418 | rio_table_hdr = NULL; | |
136f1e7a | 1419 | prev_offset = 0; |
b34e90b8 | 1420 | offset = 0x180; |
136f1e7a IM |
1421 | /* |
1422 | * The next offset is stored in the 1st word. | |
1423 | * Only parse up until the offset increases: | |
1424 | */ | |
1425 | while (offset > prev_offset) { | |
b34e90b8 LV |
1426 | /* The block id is stored in the 2nd word */ |
1427 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1428 | /* set the pointer past the offset & block id */ | |
eae93755 | 1429 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1430 | break; |
1431 | } | |
136f1e7a | 1432 | prev_offset = offset; |
b34e90b8 LV |
1433 | offset = *((unsigned short *)(ptr + offset)); |
1434 | } | |
eae93755 | 1435 | if (!rio_table_hdr) { |
b92cc559 MBY |
1436 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1437 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1438 | return; |
1439 | } | |
1440 | ||
eae93755 MBY |
1441 | ret = build_detail_arrays(); |
1442 | if (ret) { | |
b92cc559 | 1443 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1444 | return; |
eae93755 | 1445 | } |
b34e90b8 | 1446 | |
95b68dec C |
1447 | specified_table_size = determine_tce_table_size((is_kdump_kernel() ? |
1448 | saved_max_pfn : max_pfn) * PAGE_SIZE); | |
e465058d | 1449 | |
d2105b10 | 1450 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1451 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1452 | unsigned short pci_device; |
1453 | u32 val; | |
1454 | ||
1455 | val = read_pci_config(bus, 0, 0, 0); | |
1456 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1457 | |
8a244590 | 1458 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1459 | continue; |
d2105b10 | 1460 | |
f38db651 | 1461 | if (info->translation_disabled) |
e465058d | 1462 | continue; |
f38db651 | 1463 | |
8a244590 MBY |
1464 | if (calgary_bus_has_devices(bus, pci_device) || |
1465 | translate_empty_slots) { | |
95b68dec C |
1466 | /* |
1467 | * If it is kdump kernel, find and use tce tables | |
1468 | * from first kernel, else allocate tce tables here | |
1469 | */ | |
1470 | if (!is_kdump_kernel()) { | |
1471 | tbl = alloc_tce_table(); | |
1472 | if (!tbl) | |
1473 | goto cleanup; | |
1474 | info->tce_space = tbl; | |
1475 | } | |
8a244590 | 1476 | calgary_found = 1; |
d2105b10 | 1477 | } |
e465058d JM |
1478 | } |
1479 | ||
b92cc559 MBY |
1480 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1481 | calgary_found ? "found" : "not found"); | |
1482 | ||
d2105b10 | 1483 | if (calgary_found) { |
e465058d JM |
1484 | iommu_detected = 1; |
1485 | calgary_detected = 1; | |
de684652 MBY |
1486 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1487 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1488 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1489 | debugging ? "enabled" : "disabled"); | |
1956a96d AB |
1490 | |
1491 | /* swiotlb for devices that aren't behind the Calgary. */ | |
1492 | if (max_pfn > MAX_DMA32_PFN) | |
1493 | swiotlb = 1; | |
e465058d JM |
1494 | } |
1495 | return; | |
1496 | ||
1497 | cleanup: | |
f38db651 MBY |
1498 | for (--bus; bus >= 0; --bus) { |
1499 | struct calgary_bus_info *info = &bus_info[bus]; | |
1500 | ||
1501 | if (info->tce_space) | |
1502 | free_tce_table(info->tce_space); | |
1503 | } | |
e465058d JM |
1504 | } |
1505 | ||
1506 | int __init calgary_iommu_init(void) | |
1507 | { | |
1508 | int ret; | |
1509 | ||
1956a96d | 1510 | if (no_iommu || (swiotlb && !calgary_detected)) |
e465058d JM |
1511 | return -ENODEV; |
1512 | ||
1513 | if (!calgary_detected) | |
1514 | return -ENODEV; | |
1515 | ||
1516 | /* ok, we're trying to use Calgary - let's roll */ | |
1517 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1518 | ||
1519 | ret = calgary_init(); | |
1520 | if (ret) { | |
1521 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1522 | "falling back to no_iommu\n", ret); | |
e465058d JM |
1523 | return ret; |
1524 | } | |
1525 | ||
1526 | force_iommu = 1; | |
310adfdd | 1527 | bad_dma_address = 0x0; |
1956a96d AB |
1528 | /* dma_ops is set to swiotlb or nommu */ |
1529 | if (!dma_ops) | |
1530 | dma_ops = &nommu_dma_ops; | |
e465058d JM |
1531 | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | static int __init calgary_parse_options(char *p) | |
1536 | { | |
1537 | unsigned int bridge; | |
1538 | size_t len; | |
1539 | char* endp; | |
1540 | ||
1541 | while (*p) { | |
1542 | if (!strncmp(p, "64k", 3)) | |
1543 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1544 | else if (!strncmp(p, "128k", 4)) | |
1545 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1546 | else if (!strncmp(p, "256k", 4)) | |
1547 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1548 | else if (!strncmp(p, "512k", 4)) | |
1549 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1550 | else if (!strncmp(p, "1M", 2)) | |
1551 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1552 | else if (!strncmp(p, "2M", 2)) | |
1553 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1554 | else if (!strncmp(p, "4M", 2)) | |
1555 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1556 | else if (!strncmp(p, "8M", 2)) | |
1557 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1558 | ||
1559 | len = strlen("translate_empty_slots"); | |
1560 | if (!strncmp(p, "translate_empty_slots", len)) | |
1561 | translate_empty_slots = 1; | |
1562 | ||
1563 | len = strlen("disable"); | |
1564 | if (!strncmp(p, "disable", len)) { | |
1565 | p += len; | |
1566 | if (*p == '=') | |
1567 | ++p; | |
1568 | if (*p == '\0') | |
1569 | break; | |
eff79aee | 1570 | bridge = simple_strtoul(p, &endp, 0); |
e465058d JM |
1571 | if (p == endp) |
1572 | break; | |
1573 | ||
d2105b10 | 1574 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1575 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1576 | "translation for PHB %#x\n", bridge); |
f38db651 | 1577 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1578 | } |
1579 | } | |
1580 | ||
1581 | p = strpbrk(p, ","); | |
1582 | if (!p) | |
1583 | break; | |
1584 | ||
1585 | p++; /* skip ',' */ | |
1586 | } | |
1587 | return 1; | |
1588 | } | |
1589 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1590 | |
1591 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1592 | { | |
1593 | struct iommu_table *tbl; | |
1594 | unsigned int npages; | |
1595 | int i; | |
1596 | ||
08f1c192 | 1597 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1598 | |
1599 | for (i = 0; i < 4; i++) { | |
1600 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1601 | ||
1602 | /* Don't give out TCEs that map MEM resources */ | |
1603 | if (!(r->flags & IORESOURCE_MEM)) | |
1604 | continue; | |
1605 | ||
1606 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1607 | if (!r->start) | |
1608 | continue; | |
1609 | ||
1610 | /* cover the whole region */ | |
1611 | npages = (r->end - r->start) >> PAGE_SHIFT; | |
1612 | npages++; | |
1613 | ||
07877cf6 MBY |
1614 | iommu_range_reserve(tbl, r->start, npages); |
1615 | } | |
1616 | } | |
1617 | ||
1618 | static int __init calgary_fixup_tce_spaces(void) | |
1619 | { | |
1620 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1621 | struct calgary_bus_info *info; |
07877cf6 MBY |
1622 | |
1623 | if (no_iommu || swiotlb || !calgary_detected) | |
1624 | return -ENODEV; | |
1625 | ||
12de257b | 1626 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1627 | |
1628 | do { | |
1629 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1630 | if (!dev) | |
1631 | break; | |
1632 | if (!is_cal_pci_dev(dev->device)) | |
1633 | continue; | |
bc3c6058 MBY |
1634 | |
1635 | info = &bus_info[dev->bus->number]; | |
1636 | if (info->translation_disabled) | |
07877cf6 MBY |
1637 | continue; |
1638 | ||
bc3c6058 | 1639 | if (!info->tce_space) |
07877cf6 MBY |
1640 | continue; |
1641 | ||
1642 | calgary_fixup_one_tce_space(dev); | |
1643 | ||
1644 | } while (1); | |
1645 | ||
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | /* | |
1650 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1651 | * and before device_initcall. | |
1652 | */ | |
1653 | rootfs_initcall(calgary_fixup_tce_spaces); |