]>
Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e465058d JM |
2 | /* |
3 | * Derived from arch/powerpc/kernel/iommu.c | |
4 | * | |
9882234b | 5 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 6 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 7 | * |
d8d2bedf | 8 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
9 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
10 | ||
e465058d JM |
11 | */ |
12 | ||
c767a54b JP |
13 | #define pr_fmt(fmt) "Calgary: " fmt |
14 | ||
e465058d JM |
15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/string.h> | |
95b68dec | 22 | #include <linux/crash_dump.h> |
e465058d | 23 | #include <linux/dma-mapping.h> |
fec777c3 | 24 | #include <linux/dma-direct.h> |
a66022c4 | 25 | #include <linux/bitmap.h> |
e465058d JM |
26 | #include <linux/pci_ids.h> |
27 | #include <linux/pci.h> | |
28 | #include <linux/delay.h> | |
8b87d9f4 | 29 | #include <linux/scatterlist.h> |
1b39b077 | 30 | #include <linux/iommu-helper.h> |
1956a96d | 31 | |
46a7fa27 | 32 | #include <asm/iommu.h> |
e465058d JM |
33 | #include <asm/calgary.h> |
34 | #include <asm/tce.h> | |
35 | #include <asm/pci-direct.h> | |
e465058d | 36 | #include <asm/dma.h> |
b34e90b8 | 37 | #include <asm/rio.h> |
ae5830a6 | 38 | #include <asm/bios_ebda.h> |
d7b9f7be | 39 | #include <asm/x86_init.h> |
d2aa232f | 40 | #include <asm/iommu_table.h> |
e465058d | 41 | |
bff6547b MBY |
42 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
43 | int use_calgary __read_mostly = 1; | |
44 | #else | |
45 | int use_calgary __read_mostly = 0; | |
46 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
47 | ||
e465058d | 48 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 49 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 50 | |
e465058d | 51 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
52 | #define CALGARY_CONFIG_REG 0x0108 |
53 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
54 | #define PHB_PLSSR_OFFSET 0x0120 |
55 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
56 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
57 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
58 | #define PHB_MEM_1_LOW 0x0190 | |
59 | #define PHB_MEM_1_HIGH 0x01A0 | |
60 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
61 | #define PHB_MEM_1_SIZE 0x01C0 | |
62 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
63 | #define PHB_AER_OFFSET 0x0200 | |
64 | #define PHB_CONFIG_0_HIGH 0x0220 | |
65 | #define PHB_CONFIG_0_LOW 0x0230 | |
66 | #define PHB_CONFIG_0_END 0x0240 | |
67 | #define PHB_MEM_2_LOW 0x02B0 | |
68 | #define PHB_MEM_2_HIGH 0x02C0 | |
69 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
70 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
71 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
72 | ||
c3860108 | 73 | /* CalIOC2 specific */ |
8bcf7705 MBY |
74 | #define PHB_SAVIOR_L2 0x0DB0 |
75 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
76 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 77 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 78 | |
e465058d JM |
79 | /* PHB_CONFIG_RW */ |
80 | #define PHB_TCE_ENABLE 0x20000000 | |
81 | #define PHB_SLOT_DISABLE 0x1C000000 | |
82 | #define PHB_DAC_DISABLE 0x01000000 | |
83 | #define PHB_MEM2_ENABLE 0x00400000 | |
84 | #define PHB_MCSR_ENABLE 0x00100000 | |
85 | /* TAR (Table Address Register) */ | |
86 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
87 | #define TAR_VALID 0x0000000000000008UL | |
88 | /* CSR (Channel/DMA Status Register) */ | |
89 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 90 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 91 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 92 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
93 | #define PMR_SOFTSTOP 0x80000000 |
94 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
95 | #define PMR_HARDSTOP 0x20000000 | |
e465058d | 96 | |
499a00e9 DW |
97 | /* |
98 | * The maximum PHB bus number. | |
99 | * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384 | |
100 | * x3950M2: 4 chassis, 48 PHBs per chassis = 192 | |
101 | * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 | |
102 | * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 | |
103 | */ | |
d596043d | 104 | #define MAX_PHB_BUS_NUM 256 |
499a00e9 DW |
105 | |
106 | #define PHBS_PER_CALGARY 4 | |
e465058d JM |
107 | |
108 | /* register offsets in Calgary's internal register space */ | |
109 | static const unsigned long tar_offsets[] = { | |
110 | 0x0580 /* TAR0 */, | |
111 | 0x0588 /* TAR1 */, | |
112 | 0x0590 /* TAR2 */, | |
113 | 0x0598 /* TAR3 */ | |
114 | }; | |
115 | ||
116 | static const unsigned long split_queue_offsets[] = { | |
117 | 0x4870 /* SPLIT QUEUE 0 */, | |
118 | 0x5870 /* SPLIT QUEUE 1 */, | |
119 | 0x6870 /* SPLIT QUEUE 2 */, | |
120 | 0x7870 /* SPLIT QUEUE 3 */ | |
121 | }; | |
122 | ||
123 | static const unsigned long phb_offsets[] = { | |
124 | 0x8000 /* PHB0 */, | |
125 | 0x9000 /* PHB1 */, | |
126 | 0xA000 /* PHB2 */, | |
127 | 0xB000 /* PHB3 */ | |
128 | }; | |
129 | ||
b34e90b8 LV |
130 | /* PHB debug registers */ |
131 | ||
132 | static const unsigned long phb_debug_offsets[] = { | |
133 | 0x4000 /* PHB 0 DEBUG */, | |
134 | 0x5000 /* PHB 1 DEBUG */, | |
135 | 0x6000 /* PHB 2 DEBUG */, | |
136 | 0x7000 /* PHB 3 DEBUG */ | |
137 | }; | |
138 | ||
139 | /* | |
140 | * STUFF register for each debug PHB, | |
141 | * byte 1 = start bus number, byte 2 = end bus number | |
142 | */ | |
143 | ||
144 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
145 | ||
e465058d JM |
146 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
147 | static int translate_empty_slots __read_mostly = 0; | |
148 | static int calgary_detected __read_mostly = 0; | |
149 | ||
b34e90b8 LV |
150 | static struct rio_table_hdr *rio_table_hdr __initdata; |
151 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 152 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 153 | |
f38db651 MBY |
154 | struct calgary_bus_info { |
155 | void *tce_space; | |
0577f148 | 156 | unsigned char translation_disabled; |
f38db651 | 157 | signed char phbid; |
b34e90b8 | 158 | void __iomem *bbar; |
f38db651 MBY |
159 | }; |
160 | ||
ff297b8c MBY |
161 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
162 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 163 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 164 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 165 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 166 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
95b68dec C |
167 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl); |
168 | static void get_tce_space_from_tar(void); | |
ff297b8c | 169 | |
d6b56b0b | 170 | static const struct cal_chipset_ops calgary_chip_ops = { |
ff297b8c | 171 | .handle_quirks = calgary_handle_quirks, |
8cb32dc7 MBY |
172 | .tce_cache_blast = calgary_tce_cache_blast, |
173 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 174 | }; |
e465058d | 175 | |
d6b56b0b | 176 | static const struct cal_chipset_ops calioc2_chip_ops = { |
c3860108 | 177 | .handle_quirks = calioc2_handle_quirks, |
8cb32dc7 MBY |
178 | .tce_cache_blast = calioc2_tce_cache_blast, |
179 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
180 | }; |
181 | ||
ff297b8c | 182 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d | 183 | |
d588ba8c MBY |
184 | static inline int translation_enabled(struct iommu_table *tbl) |
185 | { | |
186 | /* only PHBs with translation enabled have an IOMMU table */ | |
187 | return (tbl != NULL); | |
188 | } | |
189 | ||
e465058d | 190 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 191 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
192 | { |
193 | unsigned long index; | |
194 | unsigned long end; | |
820a1497 | 195 | unsigned long flags; |
e465058d JM |
196 | |
197 | index = start_addr >> PAGE_SHIFT; | |
198 | ||
199 | /* bail out if we're asked to reserve a region we don't cover */ | |
200 | if (index >= tbl->it_size) | |
201 | return; | |
202 | ||
203 | end = index + npages; | |
204 | if (end > tbl->it_size) /* don't go off the table */ | |
205 | end = tbl->it_size; | |
206 | ||
820a1497 MBY |
207 | spin_lock_irqsave(&tbl->it_lock, flags); |
208 | ||
a66022c4 | 209 | bitmap_set(tbl->it_map, index, npages); |
820a1497 MBY |
210 | |
211 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
212 | } |
213 | ||
1b39b077 FT |
214 | static unsigned long iommu_range_alloc(struct device *dev, |
215 | struct iommu_table *tbl, | |
216 | unsigned int npages) | |
e465058d | 217 | { |
820a1497 | 218 | unsigned long flags; |
e465058d | 219 | unsigned long offset; |
1b39b077 FT |
220 | unsigned long boundary_size; |
221 | ||
222 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
223 | PAGE_SIZE) >> PAGE_SHIFT; | |
e465058d JM |
224 | |
225 | BUG_ON(npages == 0); | |
226 | ||
820a1497 MBY |
227 | spin_lock_irqsave(&tbl->it_lock, flags); |
228 | ||
1b39b077 FT |
229 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint, |
230 | npages, 0, boundary_size, 0); | |
e465058d | 231 | if (offset == ~0UL) { |
ff297b8c | 232 | tbl->chip_ops->tce_cache_blast(tbl); |
1b39b077 FT |
233 | |
234 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | |
235 | npages, 0, boundary_size, 0); | |
e465058d | 236 | if (offset == ~0UL) { |
c767a54b | 237 | pr_warn("IOMMU full\n"); |
820a1497 | 238 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
239 | if (panic_on_overflow) |
240 | panic("Calgary: fix the allocator.\n"); | |
241 | else | |
887712a0 | 242 | return DMA_MAPPING_ERROR; |
e465058d JM |
243 | } |
244 | } | |
245 | ||
e465058d JM |
246 | tbl->it_hint = offset + npages; |
247 | BUG_ON(tbl->it_hint > tbl->it_size); | |
248 | ||
820a1497 MBY |
249 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
250 | ||
e465058d JM |
251 | return offset; |
252 | } | |
253 | ||
1b39b077 FT |
254 | static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, |
255 | void *vaddr, unsigned int npages, int direction) | |
e465058d | 256 | { |
820a1497 | 257 | unsigned long entry; |
1f7564ca | 258 | dma_addr_t ret; |
e465058d | 259 | |
1b39b077 | 260 | entry = iommu_range_alloc(dev, tbl, npages); |
887712a0 | 261 | if (unlikely(entry == DMA_MAPPING_ERROR)) { |
c767a54b JP |
262 | pr_warn("failed to allocate %u pages in iommu %p\n", |
263 | npages, tbl); | |
887712a0 | 264 | return DMA_MAPPING_ERROR; |
1f7564ca | 265 | } |
e465058d JM |
266 | |
267 | /* set the return dma address */ | |
268 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
269 | ||
270 | /* put the TCEs in the HW table */ | |
271 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
272 | direction); | |
e465058d | 273 | return ret; |
e465058d JM |
274 | } |
275 | ||
3cc39bda | 276 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
277 | unsigned int npages) |
278 | { | |
279 | unsigned long entry; | |
820a1497 | 280 | unsigned long flags; |
310adfdd MBY |
281 | |
282 | /* were we called with bad_dma_address? */ | |
887712a0 | 283 | if (unlikely(dma_addr == DMA_MAPPING_ERROR)) { |
bde78a79 | 284 | WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA " |
310adfdd | 285 | "address 0x%Lx\n", dma_addr); |
310adfdd MBY |
286 | return; |
287 | } | |
e465058d JM |
288 | |
289 | entry = dma_addr >> PAGE_SHIFT; | |
290 | ||
291 | BUG_ON(entry + npages > tbl->it_size); | |
292 | ||
293 | tce_free(tbl, entry, npages); | |
294 | ||
820a1497 MBY |
295 | spin_lock_irqsave(&tbl->it_lock, flags); |
296 | ||
a66022c4 | 297 | bitmap_clear(tbl->it_map, entry, npages); |
820a1497 MBY |
298 | |
299 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
300 | } |
301 | ||
35b6dfa0 MBY |
302 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
303 | { | |
8a244590 MBY |
304 | struct pci_dev *pdev; |
305 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
306 | struct iommu_table *tbl; |
307 | ||
8a244590 MBY |
308 | pdev = to_pci_dev(dev); |
309 | ||
4528752f | 310 | /* search up the device tree for an iommu */ |
f055a061 | 311 | pbus = pdev->bus; |
4528752f DW |
312 | do { |
313 | tbl = pci_iommu(pbus); | |
314 | if (tbl && tbl->it_busno == pbus->number) | |
315 | break; | |
316 | tbl = NULL; | |
f055a061 | 317 | pbus = pbus->parent; |
4528752f | 318 | } while (pbus); |
7354b075 | 319 | |
f055a061 | 320 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
321 | |
322 | return tbl; | |
323 | } | |
324 | ||
160c1d8e FT |
325 | static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, |
326 | int nelems,enum dma_data_direction dir, | |
00085f1e | 327 | unsigned long attrs) |
e465058d | 328 | { |
3cc39bda | 329 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
330 | struct scatterlist *s; |
331 | int i; | |
3cc39bda | 332 | |
bc3c6058 | 333 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
334 | return; |
335 | ||
8b87d9f4 | 336 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 337 | unsigned int npages; |
8b87d9f4 JA |
338 | dma_addr_t dma = s->dma_address; |
339 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
340 | |
341 | if (dmalen == 0) | |
342 | break; | |
343 | ||
036b4c50 | 344 | npages = iommu_num_pages(dma, dmalen, PAGE_SIZE); |
3cc39bda | 345 | iommu_free(tbl, dma, npages); |
e465058d JM |
346 | } |
347 | } | |
348 | ||
0b11e1c6 | 349 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
160c1d8e | 350 | int nelems, enum dma_data_direction dir, |
00085f1e | 351 | unsigned long attrs) |
e465058d | 352 | { |
35b6dfa0 | 353 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 354 | struct scatterlist *s; |
e465058d JM |
355 | unsigned long vaddr; |
356 | unsigned int npages; | |
357 | unsigned long entry; | |
358 | int i; | |
359 | ||
8b87d9f4 | 360 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 361 | BUG_ON(!sg_page(s)); |
e465058d | 362 | |
58b053e4 | 363 | vaddr = (unsigned long) sg_virt(s); |
036b4c50 | 364 | npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE); |
e465058d | 365 | |
1b39b077 | 366 | entry = iommu_range_alloc(dev, tbl, npages); |
887712a0 | 367 | if (entry == DMA_MAPPING_ERROR) { |
e465058d JM |
368 | /* makes sure unmap knows to stop */ |
369 | s->dma_length = 0; | |
370 | goto error; | |
371 | } | |
372 | ||
373 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
374 | ||
375 | /* insert into HW table */ | |
160c1d8e | 376 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir); |
e465058d JM |
377 | |
378 | s->dma_length = s->length; | |
379 | } | |
380 | ||
e465058d JM |
381 | return nelems; |
382 | error: | |
00085f1e | 383 | calgary_unmap_sg(dev, sg, nelems, dir, 0); |
8b87d9f4 | 384 | for_each_sg(sg, s, nelems, i) { |
887712a0 | 385 | sg->dma_address = DMA_MAPPING_ERROR; |
8b87d9f4 | 386 | sg->dma_length = 0; |
e465058d | 387 | } |
e465058d JM |
388 | return 0; |
389 | } | |
390 | ||
3991605c FT |
391 | static dma_addr_t calgary_map_page(struct device *dev, struct page *page, |
392 | unsigned long offset, size_t size, | |
393 | enum dma_data_direction dir, | |
00085f1e | 394 | unsigned long attrs) |
e465058d | 395 | { |
3991605c | 396 | void *vaddr = page_address(page) + offset; |
e465058d JM |
397 | unsigned long uaddr; |
398 | unsigned int npages; | |
35b6dfa0 | 399 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
400 | |
401 | uaddr = (unsigned long)vaddr; | |
036b4c50 | 402 | npages = iommu_num_pages(uaddr, size, PAGE_SIZE); |
e465058d | 403 | |
3991605c | 404 | return iommu_alloc(dev, tbl, vaddr, npages, dir); |
e465058d JM |
405 | } |
406 | ||
3991605c FT |
407 | static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr, |
408 | size_t size, enum dma_data_direction dir, | |
00085f1e | 409 | unsigned long attrs) |
e465058d | 410 | { |
35b6dfa0 | 411 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
412 | unsigned int npages; |
413 | ||
3991605c FT |
414 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
415 | iommu_free(tbl, dma_addr, npages); | |
416 | } | |
417 | ||
0b11e1c6 | 418 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
00085f1e | 419 | dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs) |
e465058d JM |
420 | { |
421 | void *ret = NULL; | |
422 | dma_addr_t mapping; | |
423 | unsigned int npages, order; | |
35b6dfa0 | 424 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
425 | |
426 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
427 | npages = size >> PAGE_SHIFT; | |
428 | order = get_order(size); | |
429 | ||
430 | /* alloc enough pages (and possibly more) */ | |
431 | ret = (void *)__get_free_pages(flag, order); | |
432 | if (!ret) | |
433 | goto error; | |
434 | memset(ret, 0, size); | |
435 | ||
1956a96d AB |
436 | /* set up tces to cover the allocated range */ |
437 | mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL); | |
887712a0 | 438 | if (mapping == DMA_MAPPING_ERROR) |
1956a96d AB |
439 | goto free; |
440 | *dma_handle = mapping; | |
e465058d | 441 | return ret; |
e465058d JM |
442 | free: |
443 | free_pages((unsigned long)ret, get_order(size)); | |
444 | ret = NULL; | |
445 | error: | |
446 | return ret; | |
447 | } | |
448 | ||
e4ad68b6 | 449 | static void calgary_free_coherent(struct device *dev, size_t size, |
baa676fc | 450 | void *vaddr, dma_addr_t dma_handle, |
00085f1e | 451 | unsigned long attrs) |
e4ad68b6 JR |
452 | { |
453 | unsigned int npages; | |
454 | struct iommu_table *tbl = find_iommu_table(dev); | |
455 | ||
456 | size = PAGE_ALIGN(size); | |
457 | npages = size >> PAGE_SHIFT; | |
458 | ||
459 | iommu_free(tbl, dma_handle, npages); | |
460 | free_pages((unsigned long)vaddr, get_order(size)); | |
461 | } | |
462 | ||
5299709d | 463 | static const struct dma_map_ops calgary_dma_ops = { |
baa676fc AP |
464 | .alloc = calgary_alloc_coherent, |
465 | .free = calgary_free_coherent, | |
e465058d JM |
466 | .map_sg = calgary_map_sg, |
467 | .unmap_sg = calgary_unmap_sg, | |
3991605c FT |
468 | .map_page = calgary_map_page, |
469 | .unmap_page = calgary_unmap_page, | |
fec777c3 | 470 | .dma_supported = dma_direct_supported, |
e465058d JM |
471 | }; |
472 | ||
b34e90b8 LV |
473 | static inline void __iomem * busno_to_bbar(unsigned char num) |
474 | { | |
475 | return bus_info[num].bbar; | |
476 | } | |
477 | ||
e465058d JM |
478 | static inline int busno_to_phbid(unsigned char num) |
479 | { | |
f38db651 | 480 | return bus_info[num].phbid; |
e465058d JM |
481 | } |
482 | ||
483 | static inline unsigned long split_queue_offset(unsigned char num) | |
484 | { | |
485 | size_t idx = busno_to_phbid(num); | |
486 | ||
487 | return split_queue_offsets[idx]; | |
488 | } | |
489 | ||
490 | static inline unsigned long tar_offset(unsigned char num) | |
491 | { | |
492 | size_t idx = busno_to_phbid(num); | |
493 | ||
494 | return tar_offsets[idx]; | |
495 | } | |
496 | ||
497 | static inline unsigned long phb_offset(unsigned char num) | |
498 | { | |
499 | size_t idx = busno_to_phbid(num); | |
500 | ||
501 | return phb_offsets[idx]; | |
502 | } | |
503 | ||
504 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
505 | { | |
506 | unsigned long target = ((unsigned long)bar) | offset; | |
507 | return (void __iomem*)target; | |
508 | } | |
509 | ||
8a244590 MBY |
510 | static inline int is_calioc2(unsigned short device) |
511 | { | |
512 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
513 | } | |
514 | ||
515 | static inline int is_calgary(unsigned short device) | |
516 | { | |
517 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
518 | } | |
519 | ||
520 | static inline int is_cal_pci_dev(unsigned short device) | |
521 | { | |
522 | return (is_calgary(device) || is_calioc2(device)); | |
523 | } | |
524 | ||
ff297b8c | 525 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
526 | { |
527 | u64 val; | |
528 | u32 aer; | |
529 | int i = 0; | |
530 | void __iomem *bbar = tbl->bbar; | |
531 | void __iomem *target; | |
532 | ||
533 | /* disable arbitration on the bus */ | |
534 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
535 | aer = readl(target); | |
536 | writel(0, target); | |
537 | ||
538 | /* read plssr to ensure it got there */ | |
539 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
540 | val = readl(target); | |
541 | ||
542 | /* poll split queues until all DMA activity is done */ | |
543 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
544 | do { | |
545 | val = readq(target); | |
546 | i++; | |
547 | } while ((val & 0xff) != 0xff && i < 100); | |
548 | if (i == 100) | |
c767a54b | 549 | pr_warn("PCI bus not quiesced, continuing anyway\n"); |
e465058d JM |
550 | |
551 | /* invalidate TCE cache */ | |
552 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
553 | writeq(tbl->tar_val, target); | |
554 | ||
555 | /* enable arbitration */ | |
556 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
557 | writel(aer, target); | |
558 | (void)readl(target); /* flush */ | |
559 | } | |
560 | ||
00be3fa4 MBY |
561 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
562 | { | |
563 | void __iomem *bbar = tbl->bbar; | |
564 | void __iomem *target; | |
565 | u64 val64; | |
566 | u32 val; | |
567 | int i = 0; | |
568 | int count = 1; | |
569 | unsigned char bus = tbl->it_busno; | |
570 | ||
571 | begin: | |
572 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
573 | "sequence - count %d\n", bus, count); | |
574 | ||
575 | /* 1. using the Page Migration Control reg set SoftStop */ | |
576 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
577 | val = be32_to_cpu(readl(target)); | |
578 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
579 | val |= PMR_SOFTSTOP; | |
580 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
581 | writel(cpu_to_be32(val), target); | |
582 | ||
583 | /* 2. poll split queues until all DMA activity is done */ | |
584 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
585 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
586 | do { | |
587 | val64 = readq(target); | |
588 | i++; | |
589 | } while ((val64 & 0xff) != 0xff && i < 100); | |
590 | if (i == 100) | |
c767a54b | 591 | pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n"); |
00be3fa4 MBY |
592 | |
593 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
594 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
595 | val = be32_to_cpu(readl(target)); | |
596 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
597 | ||
598 | /* 4. if SoftStopFault - goto (1) */ | |
599 | if (val & PMR_SOFTSTOPFAULT) { | |
600 | if (++count < 100) | |
601 | goto begin; | |
602 | else { | |
c767a54b | 603 | pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n"); |
00be3fa4 MBY |
604 | return; /* pray for the best */ |
605 | } | |
606 | } | |
607 | ||
608 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
609 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
610 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
611 | val = be32_to_cpu(readl(target)); | |
612 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
613 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
614 | val = be32_to_cpu(readl(target)); | |
615 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
616 | ||
617 | /* 6. invalidate TCE cache */ | |
618 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
619 | target = calgary_reg(bbar, tar_offset(bus)); | |
620 | writeq(tbl->tar_val, target); | |
621 | ||
622 | /* 7. Re-read PMCR */ | |
623 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
624 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
625 | val = be32_to_cpu(readl(target)); | |
626 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
627 | ||
628 | /* 8. Remove HardStop */ | |
629 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
630 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
631 | val = 0; | |
632 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
633 | writel(cpu_to_be32(val), target); | |
634 | val = be32_to_cpu(readl(target)); | |
635 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
636 | } | |
637 | ||
e465058d JM |
638 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
639 | u64 limit) | |
640 | { | |
641 | unsigned int numpages; | |
642 | ||
643 | limit = limit | 0xfffff; | |
644 | limit++; | |
645 | ||
646 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 647 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
648 | } |
649 | ||
650 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
651 | { | |
652 | void __iomem *target; | |
653 | u64 low, high, sizelow; | |
654 | u64 start, limit; | |
08f1c192 | 655 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
656 | unsigned char busnum = dev->bus->number; |
657 | void __iomem *bbar = tbl->bbar; | |
658 | ||
659 | /* peripheral MEM_1 region */ | |
660 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
661 | low = be32_to_cpu(readl(target)); | |
662 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
663 | high = be32_to_cpu(readl(target)); | |
664 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
665 | sizelow = be32_to_cpu(readl(target)); | |
666 | ||
667 | start = (high << 32) | low; | |
668 | limit = sizelow; | |
669 | ||
670 | calgary_reserve_mem_region(dev, start, limit); | |
671 | } | |
672 | ||
673 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
674 | { | |
675 | void __iomem *target; | |
676 | u32 val32; | |
677 | u64 low, high, sizelow, sizehigh; | |
678 | u64 start, limit; | |
08f1c192 | 679 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
680 | unsigned char busnum = dev->bus->number; |
681 | void __iomem *bbar = tbl->bbar; | |
682 | ||
683 | /* is it enabled? */ | |
684 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
685 | val32 = be32_to_cpu(readl(target)); | |
686 | if (!(val32 & PHB_MEM2_ENABLE)) | |
687 | return; | |
688 | ||
689 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
690 | low = be32_to_cpu(readl(target)); | |
691 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
692 | high = be32_to_cpu(readl(target)); | |
693 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
694 | sizelow = be32_to_cpu(readl(target)); | |
695 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
696 | sizehigh = be32_to_cpu(readl(target)); | |
697 | ||
698 | start = (high << 32) | low; | |
699 | limit = (sizehigh << 32) | sizelow; | |
700 | ||
701 | calgary_reserve_mem_region(dev, start, limit); | |
702 | } | |
703 | ||
704 | /* | |
705 | * some regions of the IO address space do not get translated, so we | |
706 | * must not give devices IO addresses in those regions. The regions | |
707 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
708 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
709 | * later. | |
710 | */ | |
711 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
712 | { | |
713 | unsigned int npages; | |
e465058d | 714 | u64 start; |
08f1c192 | 715 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 716 | |
e465058d | 717 | /* avoid the BIOS/VGA first 640KB-1MB region */ |
e8f20414 | 718 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
719 | if (is_calgary(dev->device)) { |
720 | start = (640 * 1024); | |
721 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
722 | } else { /* calioc2 */ | |
723 | start = 0; | |
e8f20414 | 724 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 725 | } |
e465058d JM |
726 | iommu_range_reserve(tbl, start, npages); |
727 | ||
728 | /* reserve the two PCI peripheral memory regions in IO space */ | |
729 | calgary_reserve_peripheral_mem_1(dev); | |
730 | calgary_reserve_peripheral_mem_2(dev); | |
731 | } | |
732 | ||
733 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
734 | { | |
735 | u64 val64; | |
736 | u64 table_phys; | |
737 | void __iomem *target; | |
738 | int ret; | |
739 | struct iommu_table *tbl; | |
740 | ||
741 | /* build TCE tables for each PHB */ | |
742 | ret = build_tce_table(dev, bbar); | |
743 | if (ret) | |
744 | return ret; | |
745 | ||
08f1c192 | 746 | tbl = pci_iommu(dev->bus); |
f38db651 | 747 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
95b68dec C |
748 | |
749 | if (is_kdump_kernel()) | |
750 | calgary_init_bitmap_from_tce_table(tbl); | |
751 | else | |
752 | tce_free(tbl, 0, tbl->it_size); | |
f38db651 | 753 | |
8bcf7705 MBY |
754 | if (is_calgary(dev->device)) |
755 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
756 | else if (is_calioc2(dev->device)) |
757 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
758 | else |
759 | BUG(); | |
ff297b8c | 760 | |
e465058d JM |
761 | calgary_reserve_regions(dev); |
762 | ||
763 | /* set TARs for each PHB */ | |
764 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
765 | val64 = be64_to_cpu(readq(target)); | |
766 | ||
767 | /* zero out all TAR bits under sw control */ | |
768 | val64 &= ~TAR_SW_BITS; | |
e465058d | 769 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 770 | |
e465058d JM |
771 | val64 |= table_phys; |
772 | ||
773 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
774 | val64 |= (u64) specified_table_size; | |
775 | ||
776 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 777 | |
e465058d JM |
778 | writeq(tbl->tar_val, target); |
779 | readq(target); /* flush */ | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
b8f4fe66 | 784 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
785 | { |
786 | u64 val64; | |
08f1c192 | 787 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 788 | void __iomem *target; |
b8f4fe66 | 789 | unsigned int bitmapsz; |
e465058d JM |
790 | |
791 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
792 | val64 = be64_to_cpu(readq(target)); | |
793 | val64 &= ~TAR_SW_BITS; | |
794 | writeq(cpu_to_be64(val64), target); | |
795 | readq(target); /* flush */ | |
796 | ||
b8f4fe66 MBY |
797 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
798 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
799 | tbl->it_map = NULL; | |
800 | ||
e465058d | 801 | kfree(tbl); |
08f1c192 MBY |
802 | |
803 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
804 | |
805 | /* Can't free bootmem allocated memory after system is up :-( */ | |
806 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
807 | } |
808 | ||
8a244590 MBY |
809 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
810 | { | |
811 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 812 | void __iomem *target; |
ddbd41b4 | 813 | u32 csr, plssr; |
8cb32dc7 MBY |
814 | |
815 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
816 | csr = be32_to_cpu(readl(target)); |
817 | ||
818 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
819 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
820 | |
821 | /* If no error, the agent ID in the CSR is not valid */ | |
c767a54b JP |
822 | pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n", |
823 | tbl->it_busno, csr, plssr); | |
8cb32dc7 MBY |
824 | } |
825 | ||
826 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
827 | { | |
828 | void __iomem *bbar = tbl->bbar; | |
829 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
830 | void __iomem *target; |
831 | unsigned long phboff = phb_offset(tbl->it_busno); | |
832 | unsigned long erroff; | |
833 | u32 errregs[7]; | |
834 | int i; | |
835 | ||
836 | /* dump CSR */ | |
837 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
838 | csr = be32_to_cpu(readl(target)); | |
839 | /* dump PLSSR */ | |
840 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
841 | plssr = be32_to_cpu(readl(target)); | |
842 | /* dump CSMR */ | |
843 | target = calgary_reg(bbar, phboff | 0x290); | |
844 | csmr = be32_to_cpu(readl(target)); | |
845 | /* dump mck */ | |
846 | target = calgary_reg(bbar, phboff | 0x800); | |
847 | mck = be32_to_cpu(readl(target)); | |
848 | ||
c767a54b | 849 | pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno); |
8cb32dc7 | 850 | |
c767a54b JP |
851 | pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", |
852 | csr, plssr, csmr, mck); | |
8a244590 MBY |
853 | |
854 | /* dump rest of error regs */ | |
c767a54b | 855 | pr_emerg(""); |
8a244590 | 856 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { |
7354b075 MBY |
857 | /* err regs are at 0x810 - 0x870 */ |
858 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
859 | target = calgary_reg(bbar, phboff | erroff); |
860 | errregs[i] = be32_to_cpu(readl(target)); | |
c767a54b | 861 | pr_cont("0x%08x@0x%lx ", errregs[i], erroff); |
8a244590 | 862 | } |
c767a54b | 863 | pr_cont("\n"); |
8cb32dc7 MBY |
864 | |
865 | /* root complex status */ | |
866 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
867 | rcstat = be32_to_cpu(readl(target)); | |
868 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
869 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
870 | } |
871 | ||
3142692a | 872 | static void calgary_watchdog(struct timer_list *t) |
e465058d | 873 | { |
3142692a | 874 | struct iommu_table *tbl = from_timer(tbl, t, watchdog_timer); |
e465058d JM |
875 | void __iomem *bbar = tbl->bbar; |
876 | u32 val32; | |
877 | void __iomem *target; | |
878 | ||
879 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
880 | val32 = be32_to_cpu(readl(target)); | |
881 | ||
882 | /* If no error, the agent ID in the CSR is not valid */ | |
883 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 884 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
885 | |
886 | /* reset error */ | |
e465058d JM |
887 | writel(0, target); |
888 | ||
889 | /* Disable bus that caused the error */ | |
890 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 891 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
892 | val32 = be32_to_cpu(readl(target)); |
893 | val32 |= PHB_SLOT_DISABLE; | |
894 | writel(cpu_to_be32(val32), target); | |
895 | readl(target); /* flush */ | |
896 | } else { | |
897 | /* Reset the timer */ | |
898 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
899 | } | |
900 | } | |
901 | ||
a2b663f6 MBY |
902 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
903 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
904 | { |
905 | u64 val64; | |
906 | void __iomem *target; | |
58db8548 | 907 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
908 | u64 mask; |
909 | ||
910 | switch (busno_to_phbid(busnum)) { | |
911 | case 0: phb_shift = (63 - 19); | |
912 | break; | |
913 | case 1: phb_shift = (63 - 23); | |
914 | break; | |
915 | case 2: phb_shift = (63 - 27); | |
916 | break; | |
917 | case 3: phb_shift = (63 - 35); | |
918 | break; | |
919 | default: | |
920 | BUG_ON(busno_to_phbid(busnum)); | |
921 | } | |
922 | ||
923 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
924 | val64 = be64_to_cpu(readq(target)); | |
925 | ||
926 | /* zero out this PHB's timer bits */ | |
927 | mask = ~(0xFUL << phb_shift); | |
928 | val64 &= mask; | |
a2b663f6 | 929 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
930 | writeq(cpu_to_be64(val64), target); |
931 | readq(target); /* flush */ | |
932 | } | |
933 | ||
31f3dff6 | 934 | static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
c3860108 MBY |
935 | { |
936 | unsigned char busnum = dev->bus->number; | |
937 | void __iomem *bbar = tbl->bbar; | |
938 | void __iomem *target; | |
939 | u32 val; | |
940 | ||
8bcf7705 MBY |
941 | /* |
942 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
943 | */ | |
944 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
945 | val = cpu_to_be32(readl(target)); | |
946 | val |= 0x00800000; | |
947 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
948 | } |
949 | ||
31f3dff6 | 950 | static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
b8d2ea1b MBY |
951 | { |
952 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
953 | |
954 | /* | |
955 | * Give split completion a longer timeout on bus 1 for aic94xx | |
956 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
957 | */ | |
c3860108 | 958 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
959 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
960 | CCR_2SEC_TIMEOUT); | |
961 | } | |
962 | ||
e465058d JM |
963 | static void __init calgary_enable_translation(struct pci_dev *dev) |
964 | { | |
965 | u32 val32; | |
966 | unsigned char busnum; | |
967 | void __iomem *target; | |
968 | void __iomem *bbar; | |
969 | struct iommu_table *tbl; | |
970 | ||
971 | busnum = dev->bus->number; | |
08f1c192 | 972 | tbl = pci_iommu(dev->bus); |
e465058d JM |
973 | bbar = tbl->bbar; |
974 | ||
975 | /* enable TCE in PHB Config Register */ | |
976 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
977 | val32 = be32_to_cpu(readl(target)); | |
978 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
979 | ||
8a244590 MBY |
980 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
981 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
982 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
983 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
984 | "bus.\n"); | |
985 | ||
986 | writel(cpu_to_be32(val32), target); | |
987 | readl(target); /* flush */ | |
988 | ||
3142692a | 989 | timer_setup(&tbl->watchdog_timer, calgary_watchdog, 0); |
e465058d JM |
990 | mod_timer(&tbl->watchdog_timer, jiffies); |
991 | } | |
992 | ||
993 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
994 | { | |
995 | u32 val32; | |
996 | unsigned char busnum; | |
997 | void __iomem *target; | |
998 | void __iomem *bbar; | |
999 | struct iommu_table *tbl; | |
1000 | ||
1001 | busnum = dev->bus->number; | |
08f1c192 | 1002 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1003 | bbar = tbl->bbar; |
1004 | ||
1005 | /* disable TCE in PHB Config Register */ | |
1006 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1007 | val32 = be32_to_cpu(readl(target)); | |
1008 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1009 | ||
70d666d6 | 1010 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1011 | writel(cpu_to_be32(val32), target); |
1012 | readl(target); /* flush */ | |
1013 | ||
1014 | del_timer_sync(&tbl->watchdog_timer); | |
1015 | } | |
1016 | ||
a4fc520a | 1017 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1018 | { |
871b1700 | 1019 | pci_dev_get(dev); |
08f1c192 | 1020 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1021 | |
1022 | /* is the device behind a bridge? */ | |
1023 | if (dev->bus->parent) | |
1024 | dev->bus->parent->self = dev; | |
1025 | else | |
1026 | dev->bus->self = dev; | |
e465058d JM |
1027 | } |
1028 | ||
1029 | static int __init calgary_init_one(struct pci_dev *dev) | |
1030 | { | |
e465058d | 1031 | void __iomem *bbar; |
ff297b8c | 1032 | struct iommu_table *tbl; |
e465058d JM |
1033 | int ret; |
1034 | ||
eae93755 | 1035 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1036 | ret = calgary_setup_tar(dev, bbar); |
1037 | if (ret) | |
eae93755 | 1038 | goto done; |
e465058d | 1039 | |
871b1700 | 1040 | pci_dev_get(dev); |
8a244590 MBY |
1041 | |
1042 | if (dev->bus->parent) { | |
1043 | if (dev->bus->parent->self) | |
1044 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1045 | "bus->parent->self!\n", dev); | |
1046 | dev->bus->parent->self = dev; | |
1047 | } else | |
1048 | dev->bus->self = dev; | |
b8d2ea1b | 1049 | |
08f1c192 | 1050 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1051 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1052 | |
e465058d JM |
1053 | calgary_enable_translation(dev); |
1054 | ||
1055 | return 0; | |
1056 | ||
e465058d JM |
1057 | done: |
1058 | return ret; | |
1059 | } | |
1060 | ||
eae93755 | 1061 | static int __init calgary_locate_bbars(void) |
e465058d | 1062 | { |
eae93755 MBY |
1063 | int ret; |
1064 | int rioidx, phb, bus; | |
b34e90b8 LV |
1065 | void __iomem *bbar; |
1066 | void __iomem *target; | |
eae93755 | 1067 | unsigned long offset; |
b34e90b8 LV |
1068 | u8 start_bus, end_bus; |
1069 | u32 val; | |
1070 | ||
eae93755 MBY |
1071 | ret = -ENODATA; |
1072 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1073 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1074 | |
eae93755 | 1075 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1076 | continue; |
1077 | ||
1078 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1079 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1080 | if (!bbar) | |
1081 | goto error; | |
b34e90b8 LV |
1082 | |
1083 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1084 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1085 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1086 | |
b34e90b8 | 1087 | val = be32_to_cpu(readl(target)); |
8a244590 | 1088 | |
b34e90b8 | 1089 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1090 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1091 | |
1092 | if (end_bus) { | |
1093 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1094 | bus_info[bus].bbar = bbar; | |
1095 | bus_info[bus].phbid = phb; | |
1096 | } | |
1097 | } else { | |
1098 | bus_info[start_bus].bbar = bbar; | |
1099 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1100 | } |
1101 | } | |
1102 | } | |
1103 | ||
eae93755 MBY |
1104 | return 0; |
1105 | ||
1106 | error: | |
1107 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1108 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1109 | if (bus_info[bus].bbar) | |
1110 | iounmap(bus_info[bus].bbar); | |
1111 | ||
1112 | return ret; | |
1113 | } | |
1114 | ||
1115 | static int __init calgary_init(void) | |
1116 | { | |
1117 | int ret; | |
1118 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1119 | struct calgary_bus_info *info; |
eae93755 MBY |
1120 | |
1121 | ret = calgary_locate_bbars(); | |
1122 | if (ret) | |
1123 | return ret; | |
e465058d | 1124 | |
95b68dec C |
1125 | /* Purely for kdump kernel case */ |
1126 | if (is_kdump_kernel()) | |
1127 | get_tce_space_from_tar(); | |
1128 | ||
dedc9937 | 1129 | do { |
8a244590 | 1130 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1131 | if (!dev) |
1132 | break; | |
8a244590 MBY |
1133 | if (!is_cal_pci_dev(dev->device)) |
1134 | continue; | |
bc3c6058 MBY |
1135 | |
1136 | info = &bus_info[dev->bus->number]; | |
1137 | if (info->translation_disabled) { | |
e465058d JM |
1138 | calgary_init_one_nontraslated(dev); |
1139 | continue; | |
1140 | } | |
bc3c6058 MBY |
1141 | |
1142 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1143 | continue; |
12de257b | 1144 | |
e465058d JM |
1145 | ret = calgary_init_one(dev); |
1146 | if (ret) | |
1147 | goto error; | |
dedc9937 | 1148 | } while (1); |
e465058d | 1149 | |
1956a96d AB |
1150 | dev = NULL; |
1151 | for_each_pci_dev(dev) { | |
1152 | struct iommu_table *tbl; | |
1153 | ||
1154 | tbl = find_iommu_table(&dev->dev); | |
1155 | ||
1156 | if (translation_enabled(tbl)) | |
5657933d | 1157 | dev->dev.dma_ops = &calgary_dma_ops; |
1956a96d AB |
1158 | } |
1159 | ||
e465058d JM |
1160 | return ret; |
1161 | ||
1162 | error: | |
dedc9937 | 1163 | do { |
a2b5d877 | 1164 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
9f2dc46d MBY |
1165 | if (!dev) |
1166 | break; | |
8a244590 MBY |
1167 | if (!is_cal_pci_dev(dev->device)) |
1168 | continue; | |
bc3c6058 MBY |
1169 | |
1170 | info = &bus_info[dev->bus->number]; | |
1171 | if (info->translation_disabled) { | |
e465058d JM |
1172 | pci_dev_put(dev); |
1173 | continue; | |
1174 | } | |
bc3c6058 | 1175 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1176 | continue; |
871b1700 | 1177 | |
e465058d | 1178 | calgary_disable_translation(dev); |
b8f4fe66 | 1179 | calgary_free_bus(dev); |
871b1700 | 1180 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
5657933d | 1181 | dev->dev.dma_ops = NULL; |
dedc9937 | 1182 | } while (1); |
e465058d JM |
1183 | |
1184 | return ret; | |
1185 | } | |
1186 | ||
0534af01 | 1187 | static inline int __init determine_tce_table_size(void) |
e465058d JM |
1188 | { |
1189 | int ret; | |
1190 | ||
1191 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1192 | return specified_table_size; | |
1193 | ||
0534af01 WC |
1194 | if (is_kdump_kernel() && saved_max_pfn) { |
1195 | /* | |
1196 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1197 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1198 | * larger table size has twice as many entries, so shift the | |
1199 | * max ram address by 13 to divide by 8K and then look at the | |
1200 | * order of the result to choose between 0-7. | |
1201 | */ | |
1202 | ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13); | |
1203 | if (ret > TCE_TABLE_SIZE_8M) | |
1204 | ret = TCE_TABLE_SIZE_8M; | |
1205 | } else { | |
1206 | /* | |
1207 | * Use 8M by default (suggested by Muli) if it's not | |
1208 | * kdump kernel and saved_max_pfn isn't set. | |
1209 | */ | |
e465058d | 1210 | ret = TCE_TABLE_SIZE_8M; |
0534af01 | 1211 | } |
e465058d JM |
1212 | |
1213 | return ret; | |
1214 | } | |
1215 | ||
b34e90b8 LV |
1216 | static int __init build_detail_arrays(void) |
1217 | { | |
1218 | unsigned long ptr; | |
85d57797 DH |
1219 | unsigned numnodes, i; |
1220 | int scal_detail_size, rio_detail_size; | |
b34e90b8 | 1221 | |
85d57797 DH |
1222 | numnodes = rio_table_hdr->num_scal_dev; |
1223 | if (numnodes > MAX_NUMNODES){ | |
b34e90b8 | 1224 | printk(KERN_WARNING |
eae93755 | 1225 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 | 1226 | "but system has %d nodes.\n", |
85d57797 | 1227 | MAX_NUMNODES, numnodes); |
b34e90b8 LV |
1228 | return -ENODEV; |
1229 | } | |
1230 | ||
1231 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1232 | case 2: |
1233 | scal_detail_size = 11; | |
1234 | rio_detail_size = 13; | |
1235 | break; | |
1236 | case 3: | |
1237 | scal_detail_size = 12; | |
1238 | rio_detail_size = 15; | |
1239 | break; | |
eae93755 MBY |
1240 | default: |
1241 | printk(KERN_WARNING | |
1242 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1243 | rio_table_hdr->version); | |
1244 | return -EPROTO; | |
b34e90b8 LV |
1245 | } |
1246 | ||
1247 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
85d57797 | 1248 | for (i = 0; i < numnodes; i++, ptr += scal_detail_size) |
b34e90b8 LV |
1249 | scal_devs[i] = (struct scal_detail *)ptr; |
1250 | ||
1251 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1252 | i++, ptr += rio_detail_size) | |
1253 | rio_devs[i] = (struct rio_detail *)ptr; | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
8a244590 | 1258 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1259 | { |
8a244590 | 1260 | int dev; |
e465058d | 1261 | u32 val; |
8a244590 MBY |
1262 | |
1263 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1264 | /* | |
0d2eb44f | 1265 | * FIXME: properly scan for devices across the |
8a244590 MBY |
1266 | * PCI-to-PCI bridge on every CalIOC2 port. |
1267 | */ | |
1268 | return 1; | |
1269 | } | |
1270 | ||
1271 | for (dev = 1; dev < 8; dev++) { | |
1272 | val = read_pci_config(bus, dev, 0, 0); | |
1273 | if (val != 0xffffffff) | |
1274 | break; | |
1275 | } | |
1276 | return (val != 0xffffffff); | |
1277 | } | |
1278 | ||
95b68dec C |
1279 | /* |
1280 | * calgary_init_bitmap_from_tce_table(): | |
0d2eb44f | 1281 | * Function for kdump case. In the second/kdump kernel initialize |
95b68dec C |
1282 | * the bitmap based on the tce table entries obtained from first kernel |
1283 | */ | |
1284 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl) | |
1285 | { | |
1286 | u64 *tp; | |
1287 | unsigned int index; | |
1288 | tp = ((u64 *)tbl->it_base); | |
1289 | for (index = 0 ; index < tbl->it_size; index++) { | |
1290 | if (*tp != 0x0) | |
1291 | set_bit(index, tbl->it_map); | |
1292 | tp++; | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | /* | |
1297 | * get_tce_space_from_tar(): | |
1298 | * Function for kdump case. Get the tce tables from first kernel | |
3ad2f3fb | 1299 | * by reading the contents of the base address register of calgary iommu |
95b68dec | 1300 | */ |
f7106662 | 1301 | static void __init get_tce_space_from_tar(void) |
95b68dec C |
1302 | { |
1303 | int bus; | |
1304 | void __iomem *target; | |
1305 | unsigned long tce_space; | |
1306 | ||
1307 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { | |
1308 | struct calgary_bus_info *info = &bus_info[bus]; | |
1309 | unsigned short pci_device; | |
1310 | u32 val; | |
1311 | ||
1312 | val = read_pci_config(bus, 0, 0, 0); | |
1313 | pci_device = (val & 0xFFFF0000) >> 16; | |
1314 | ||
1315 | if (!is_cal_pci_dev(pci_device)) | |
1316 | continue; | |
1317 | if (info->translation_disabled) | |
1318 | continue; | |
1319 | ||
1320 | if (calgary_bus_has_devices(bus, pci_device) || | |
1321 | translate_empty_slots) { | |
1322 | target = calgary_reg(bus_info[bus].bbar, | |
1323 | tar_offset(bus)); | |
1324 | tce_space = be64_to_cpu(readq(target)); | |
1325 | tce_space = tce_space & TAR_SW_BITS; | |
1326 | ||
1327 | tce_space = tce_space & (~specified_table_size); | |
1328 | info->tce_space = (u64 *)__va(tce_space); | |
1329 | } | |
1330 | } | |
1331 | return; | |
1332 | } | |
1333 | ||
f4131c62 FT |
1334 | static int __init calgary_iommu_init(void) |
1335 | { | |
1336 | int ret; | |
1337 | ||
1338 | /* ok, we're trying to use Calgary - let's roll */ | |
1339 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1340 | ||
1341 | ret = calgary_init(); | |
1342 | if (ret) { | |
1343 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1344 | "falling back to no_iommu\n", ret); | |
1345 | return ret; | |
1346 | } | |
1347 | ||
f4131c62 FT |
1348 | return 0; |
1349 | } | |
d7b9f7be | 1350 | |
480125ba | 1351 | int __init detect_calgary(void) |
8a244590 | 1352 | { |
d2105b10 | 1353 | int bus; |
e465058d | 1354 | void *tbl; |
d2105b10 | 1355 | int calgary_found = 0; |
b34e90b8 | 1356 | unsigned long ptr; |
136f1e7a | 1357 | unsigned int offset, prev_offset; |
eae93755 | 1358 | int ret; |
e465058d JM |
1359 | |
1360 | /* | |
1361 | * if the user specified iommu=off or iommu=soft or we found | |
1362 | * another HW IOMMU already, bail out. | |
1363 | */ | |
75f1cdf1 | 1364 | if (no_iommu || iommu_detected) |
480125ba | 1365 | return -ENODEV; |
e465058d | 1366 | |
bff6547b | 1367 | if (!use_calgary) |
480125ba | 1368 | return -ENODEV; |
bff6547b | 1369 | |
0637a70a | 1370 | if (!early_pci_allowed()) |
480125ba | 1371 | return -ENODEV; |
0637a70a | 1372 | |
b92cc559 MBY |
1373 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1374 | ||
b34e90b8 LV |
1375 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1376 | ||
1377 | rio_table_hdr = NULL; | |
136f1e7a | 1378 | prev_offset = 0; |
b34e90b8 | 1379 | offset = 0x180; |
136f1e7a IM |
1380 | /* |
1381 | * The next offset is stored in the 1st word. | |
1382 | * Only parse up until the offset increases: | |
1383 | */ | |
1384 | while (offset > prev_offset) { | |
b34e90b8 LV |
1385 | /* The block id is stored in the 2nd word */ |
1386 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1387 | /* set the pointer past the offset & block id */ | |
eae93755 | 1388 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1389 | break; |
1390 | } | |
136f1e7a | 1391 | prev_offset = offset; |
b34e90b8 LV |
1392 | offset = *((unsigned short *)(ptr + offset)); |
1393 | } | |
eae93755 | 1394 | if (!rio_table_hdr) { |
b92cc559 MBY |
1395 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1396 | "in EBDA - bailing!\n"); | |
480125ba | 1397 | return -ENODEV; |
b34e90b8 LV |
1398 | } |
1399 | ||
eae93755 MBY |
1400 | ret = build_detail_arrays(); |
1401 | if (ret) { | |
b92cc559 | 1402 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
480125ba | 1403 | return -ENOMEM; |
eae93755 | 1404 | } |
b34e90b8 | 1405 | |
0534af01 | 1406 | specified_table_size = determine_tce_table_size(); |
e465058d | 1407 | |
d2105b10 | 1408 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1409 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1410 | unsigned short pci_device; |
1411 | u32 val; | |
1412 | ||
1413 | val = read_pci_config(bus, 0, 0, 0); | |
1414 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1415 | |
8a244590 | 1416 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1417 | continue; |
d2105b10 | 1418 | |
f38db651 | 1419 | if (info->translation_disabled) |
e465058d | 1420 | continue; |
f38db651 | 1421 | |
8a244590 MBY |
1422 | if (calgary_bus_has_devices(bus, pci_device) || |
1423 | translate_empty_slots) { | |
95b68dec C |
1424 | /* |
1425 | * If it is kdump kernel, find and use tce tables | |
1426 | * from first kernel, else allocate tce tables here | |
1427 | */ | |
1428 | if (!is_kdump_kernel()) { | |
1429 | tbl = alloc_tce_table(); | |
1430 | if (!tbl) | |
1431 | goto cleanup; | |
1432 | info->tce_space = tbl; | |
1433 | } | |
8a244590 | 1434 | calgary_found = 1; |
d2105b10 | 1435 | } |
e465058d JM |
1436 | } |
1437 | ||
b92cc559 MBY |
1438 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1439 | calgary_found ? "found" : "not found"); | |
1440 | ||
d2105b10 | 1441 | if (calgary_found) { |
e465058d JM |
1442 | iommu_detected = 1; |
1443 | calgary_detected = 1; | |
de684652 | 1444 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
7e05575c FT |
1445 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n", |
1446 | specified_table_size); | |
1956a96d | 1447 | |
d7b9f7be | 1448 | x86_init.iommu.iommu_init = calgary_iommu_init; |
e465058d | 1449 | } |
480125ba | 1450 | return calgary_found; |
e465058d JM |
1451 | |
1452 | cleanup: | |
f38db651 MBY |
1453 | for (--bus; bus >= 0; --bus) { |
1454 | struct calgary_bus_info *info = &bus_info[bus]; | |
1455 | ||
1456 | if (info->tce_space) | |
1457 | free_tce_table(info->tce_space); | |
1458 | } | |
480125ba | 1459 | return -ENOMEM; |
e465058d JM |
1460 | } |
1461 | ||
e465058d JM |
1462 | static int __init calgary_parse_options(char *p) |
1463 | { | |
1464 | unsigned int bridge; | |
74bc4917 | 1465 | unsigned long val; |
e465058d | 1466 | size_t len; |
74bc4917 | 1467 | ssize_t ret; |
e465058d JM |
1468 | |
1469 | while (*p) { | |
1470 | if (!strncmp(p, "64k", 3)) | |
1471 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1472 | else if (!strncmp(p, "128k", 4)) | |
1473 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1474 | else if (!strncmp(p, "256k", 4)) | |
1475 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1476 | else if (!strncmp(p, "512k", 4)) | |
1477 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1478 | else if (!strncmp(p, "1M", 2)) | |
1479 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1480 | else if (!strncmp(p, "2M", 2)) | |
1481 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1482 | else if (!strncmp(p, "4M", 2)) | |
1483 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1484 | else if (!strncmp(p, "8M", 2)) | |
1485 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1486 | ||
1487 | len = strlen("translate_empty_slots"); | |
1488 | if (!strncmp(p, "translate_empty_slots", len)) | |
1489 | translate_empty_slots = 1; | |
1490 | ||
1491 | len = strlen("disable"); | |
1492 | if (!strncmp(p, "disable", len)) { | |
1493 | p += len; | |
1494 | if (*p == '=') | |
1495 | ++p; | |
1496 | if (*p == '\0') | |
1497 | break; | |
74bc4917 SK |
1498 | ret = kstrtoul(p, 0, &val); |
1499 | if (ret) | |
e465058d JM |
1500 | break; |
1501 | ||
74bc4917 | 1502 | bridge = val; |
d2105b10 | 1503 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1504 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1505 | "translation for PHB %#x\n", bridge); |
f38db651 | 1506 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1507 | } |
1508 | } | |
1509 | ||
1510 | p = strpbrk(p, ","); | |
1511 | if (!p) | |
1512 | break; | |
1513 | ||
1514 | p++; /* skip ',' */ | |
1515 | } | |
1516 | return 1; | |
1517 | } | |
1518 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1519 | |
1520 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1521 | { | |
1522 | struct iommu_table *tbl; | |
1523 | unsigned int npages; | |
1524 | int i; | |
1525 | ||
08f1c192 | 1526 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1527 | |
1528 | for (i = 0; i < 4; i++) { | |
1529 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1530 | ||
1531 | /* Don't give out TCEs that map MEM resources */ | |
1532 | if (!(r->flags & IORESOURCE_MEM)) | |
1533 | continue; | |
1534 | ||
1535 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1536 | if (!r->start) | |
1537 | continue; | |
1538 | ||
1539 | /* cover the whole region */ | |
28f65c11 | 1540 | npages = resource_size(r) >> PAGE_SHIFT; |
07877cf6 MBY |
1541 | npages++; |
1542 | ||
07877cf6 MBY |
1543 | iommu_range_reserve(tbl, r->start, npages); |
1544 | } | |
1545 | } | |
1546 | ||
1547 | static int __init calgary_fixup_tce_spaces(void) | |
1548 | { | |
1549 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1550 | struct calgary_bus_info *info; |
07877cf6 MBY |
1551 | |
1552 | if (no_iommu || swiotlb || !calgary_detected) | |
1553 | return -ENODEV; | |
1554 | ||
12de257b | 1555 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1556 | |
1557 | do { | |
1558 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1559 | if (!dev) | |
1560 | break; | |
1561 | if (!is_cal_pci_dev(dev->device)) | |
1562 | continue; | |
bc3c6058 MBY |
1563 | |
1564 | info = &bus_info[dev->bus->number]; | |
1565 | if (info->translation_disabled) | |
07877cf6 MBY |
1566 | continue; |
1567 | ||
bc3c6058 | 1568 | if (!info->tce_space) |
07877cf6 MBY |
1569 | continue; |
1570 | ||
1571 | calgary_fixup_one_tce_space(dev); | |
1572 | ||
1573 | } while (1); | |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | ||
1578 | /* | |
1579 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1580 | * and before device_initcall. | |
1581 | */ | |
1582 | rootfs_initcall(calgary_fixup_tce_spaces); | |
d2aa232f KRW |
1583 | |
1584 | IOMMU_INIT_POST(detect_calgary); |