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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
e465058d JM |
33 | #include <linux/bitops.h> |
34 | #include <linux/pci_ids.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/delay.h> | |
8b87d9f4 | 37 | #include <linux/scatterlist.h> |
1b39b077 | 38 | #include <linux/iommu-helper.h> |
395624fc | 39 | #include <asm/gart.h> |
e465058d JM |
40 | #include <asm/calgary.h> |
41 | #include <asm/tce.h> | |
42 | #include <asm/pci-direct.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/dma.h> | |
b34e90b8 | 45 | #include <asm/rio.h> |
e465058d | 46 | |
bff6547b MBY |
47 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
48 | int use_calgary __read_mostly = 1; | |
49 | #else | |
50 | int use_calgary __read_mostly = 0; | |
51 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
52 | ||
e465058d | 53 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 54 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 55 | |
e465058d | 56 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
57 | #define CALGARY_CONFIG_REG 0x0108 |
58 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
59 | #define PHB_PLSSR_OFFSET 0x0120 |
60 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
61 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
62 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
63 | #define PHB_MEM_1_LOW 0x0190 | |
64 | #define PHB_MEM_1_HIGH 0x01A0 | |
65 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
66 | #define PHB_MEM_1_SIZE 0x01C0 | |
67 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
68 | #define PHB_AER_OFFSET 0x0200 | |
69 | #define PHB_CONFIG_0_HIGH 0x0220 | |
70 | #define PHB_CONFIG_0_LOW 0x0230 | |
71 | #define PHB_CONFIG_0_END 0x0240 | |
72 | #define PHB_MEM_2_LOW 0x02B0 | |
73 | #define PHB_MEM_2_HIGH 0x02C0 | |
74 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
75 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
76 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
77 | ||
c3860108 | 78 | /* CalIOC2 specific */ |
8bcf7705 MBY |
79 | #define PHB_SAVIOR_L2 0x0DB0 |
80 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
81 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 82 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 83 | |
e465058d JM |
84 | /* PHB_CONFIG_RW */ |
85 | #define PHB_TCE_ENABLE 0x20000000 | |
86 | #define PHB_SLOT_DISABLE 0x1C000000 | |
87 | #define PHB_DAC_DISABLE 0x01000000 | |
88 | #define PHB_MEM2_ENABLE 0x00400000 | |
89 | #define PHB_MCSR_ENABLE 0x00100000 | |
90 | /* TAR (Table Address Register) */ | |
91 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
92 | #define TAR_VALID 0x0000000000000008UL | |
93 | /* CSR (Channel/DMA Status Register) */ | |
94 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 95 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 96 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 97 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
98 | #define PMR_SOFTSTOP 0x80000000 |
99 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
100 | #define PMR_HARDSTOP 0x20000000 | |
e465058d JM |
101 | |
102 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 103 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
104 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
105 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
106 | #define PHBS_PER_CALGARY 4 |
107 | ||
108 | /* register offsets in Calgary's internal register space */ | |
109 | static const unsigned long tar_offsets[] = { | |
110 | 0x0580 /* TAR0 */, | |
111 | 0x0588 /* TAR1 */, | |
112 | 0x0590 /* TAR2 */, | |
113 | 0x0598 /* TAR3 */ | |
114 | }; | |
115 | ||
116 | static const unsigned long split_queue_offsets[] = { | |
117 | 0x4870 /* SPLIT QUEUE 0 */, | |
118 | 0x5870 /* SPLIT QUEUE 1 */, | |
119 | 0x6870 /* SPLIT QUEUE 2 */, | |
120 | 0x7870 /* SPLIT QUEUE 3 */ | |
121 | }; | |
122 | ||
123 | static const unsigned long phb_offsets[] = { | |
124 | 0x8000 /* PHB0 */, | |
125 | 0x9000 /* PHB1 */, | |
126 | 0xA000 /* PHB2 */, | |
127 | 0xB000 /* PHB3 */ | |
128 | }; | |
129 | ||
b34e90b8 LV |
130 | /* PHB debug registers */ |
131 | ||
132 | static const unsigned long phb_debug_offsets[] = { | |
133 | 0x4000 /* PHB 0 DEBUG */, | |
134 | 0x5000 /* PHB 1 DEBUG */, | |
135 | 0x6000 /* PHB 2 DEBUG */, | |
136 | 0x7000 /* PHB 3 DEBUG */ | |
137 | }; | |
138 | ||
139 | /* | |
140 | * STUFF register for each debug PHB, | |
141 | * byte 1 = start bus number, byte 2 = end bus number | |
142 | */ | |
143 | ||
144 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
145 | ||
310adfdd MBY |
146 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
147 | ||
e465058d JM |
148 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
149 | static int translate_empty_slots __read_mostly = 0; | |
150 | static int calgary_detected __read_mostly = 0; | |
151 | ||
b34e90b8 LV |
152 | static struct rio_table_hdr *rio_table_hdr __initdata; |
153 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 154 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 155 | |
f38db651 MBY |
156 | struct calgary_bus_info { |
157 | void *tce_space; | |
0577f148 | 158 | unsigned char translation_disabled; |
f38db651 | 159 | signed char phbid; |
b34e90b8 | 160 | void __iomem *bbar; |
f38db651 MBY |
161 | }; |
162 | ||
ff297b8c MBY |
163 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
164 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 165 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 166 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 167 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 168 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
ff297b8c MBY |
169 | |
170 | static struct cal_chipset_ops calgary_chip_ops = { | |
171 | .handle_quirks = calgary_handle_quirks, | |
8cb32dc7 MBY |
172 | .tce_cache_blast = calgary_tce_cache_blast, |
173 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 174 | }; |
e465058d | 175 | |
c3860108 MBY |
176 | static struct cal_chipset_ops calioc2_chip_ops = { |
177 | .handle_quirks = calioc2_handle_quirks, | |
8cb32dc7 MBY |
178 | .tce_cache_blast = calioc2_tce_cache_blast, |
179 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
180 | }; |
181 | ||
ff297b8c | 182 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
183 | |
184 | /* enable this to stress test the chip's TCE cache */ | |
185 | #ifdef CONFIG_IOMMU_DEBUG | |
ed65260b | 186 | static int debugging = 1; |
de684652 | 187 | |
796e4390 MBY |
188 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
189 | int expected, unsigned long start, unsigned long end) | |
190 | { | |
191 | unsigned long idx = start; | |
192 | ||
193 | BUG_ON(start >= end); | |
194 | ||
195 | while (idx < end) { | |
196 | if (!!test_bit(idx, bitmap) != expected) | |
197 | return idx; | |
198 | ++idx; | |
199 | } | |
200 | ||
201 | /* all bits have the expected value */ | |
202 | return ~0UL; | |
203 | } | |
de684652 | 204 | #else /* debugging is disabled */ |
ed65260b | 205 | static int debugging; |
de684652 | 206 | |
796e4390 MBY |
207 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
208 | int expected, unsigned long start, unsigned long end) | |
209 | { | |
210 | return ~0UL; | |
211 | } | |
8a244590 | 212 | |
de684652 | 213 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
214 | |
215 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
216 | { | |
217 | unsigned int npages; | |
218 | ||
219 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
220 | npages >>= PAGE_SHIFT; | |
221 | ||
222 | return npages; | |
223 | } | |
224 | ||
d588ba8c MBY |
225 | static inline int translation_enabled(struct iommu_table *tbl) |
226 | { | |
227 | /* only PHBs with translation enabled have an IOMMU table */ | |
228 | return (tbl != NULL); | |
229 | } | |
230 | ||
e465058d | 231 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 232 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
233 | { |
234 | unsigned long index; | |
235 | unsigned long end; | |
796e4390 | 236 | unsigned long badbit; |
820a1497 | 237 | unsigned long flags; |
e465058d JM |
238 | |
239 | index = start_addr >> PAGE_SHIFT; | |
240 | ||
241 | /* bail out if we're asked to reserve a region we don't cover */ | |
242 | if (index >= tbl->it_size) | |
243 | return; | |
244 | ||
245 | end = index + npages; | |
246 | if (end > tbl->it_size) /* don't go off the table */ | |
247 | end = tbl->it_size; | |
248 | ||
820a1497 MBY |
249 | spin_lock_irqsave(&tbl->it_lock, flags); |
250 | ||
796e4390 MBY |
251 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
252 | if (badbit != ~0UL) { | |
253 | if (printk_ratelimit()) | |
e465058d JM |
254 | printk(KERN_ERR "Calgary: entry already allocated at " |
255 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 256 | badbit, tbl, start_addr, npages); |
e465058d | 257 | } |
796e4390 MBY |
258 | |
259 | set_bit_string(tbl->it_map, index, npages); | |
820a1497 MBY |
260 | |
261 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
262 | } |
263 | ||
1b39b077 FT |
264 | static unsigned long iommu_range_alloc(struct device *dev, |
265 | struct iommu_table *tbl, | |
266 | unsigned int npages) | |
e465058d | 267 | { |
820a1497 | 268 | unsigned long flags; |
e465058d | 269 | unsigned long offset; |
1b39b077 FT |
270 | unsigned long boundary_size; |
271 | ||
272 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
273 | PAGE_SIZE) >> PAGE_SHIFT; | |
e465058d JM |
274 | |
275 | BUG_ON(npages == 0); | |
276 | ||
820a1497 MBY |
277 | spin_lock_irqsave(&tbl->it_lock, flags); |
278 | ||
1b39b077 FT |
279 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint, |
280 | npages, 0, boundary_size, 0); | |
e465058d | 281 | if (offset == ~0UL) { |
ff297b8c | 282 | tbl->chip_ops->tce_cache_blast(tbl); |
1b39b077 FT |
283 | |
284 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | |
285 | npages, 0, boundary_size, 0); | |
e465058d JM |
286 | if (offset == ~0UL) { |
287 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
820a1497 | 288 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
289 | if (panic_on_overflow) |
290 | panic("Calgary: fix the allocator.\n"); | |
291 | else | |
292 | return bad_dma_address; | |
293 | } | |
294 | } | |
295 | ||
e465058d JM |
296 | tbl->it_hint = offset + npages; |
297 | BUG_ON(tbl->it_hint > tbl->it_size); | |
298 | ||
820a1497 MBY |
299 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
300 | ||
e465058d JM |
301 | return offset; |
302 | } | |
303 | ||
1b39b077 FT |
304 | static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, |
305 | void *vaddr, unsigned int npages, int direction) | |
e465058d | 306 | { |
820a1497 | 307 | unsigned long entry; |
e465058d JM |
308 | dma_addr_t ret = bad_dma_address; |
309 | ||
1b39b077 | 310 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d JM |
311 | |
312 | if (unlikely(entry == bad_dma_address)) | |
313 | goto error; | |
314 | ||
315 | /* set the return dma address */ | |
316 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
317 | ||
318 | /* put the TCEs in the HW table */ | |
319 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
320 | direction); | |
321 | ||
e465058d JM |
322 | return ret; |
323 | ||
324 | error: | |
e465058d JM |
325 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " |
326 | "iommu %p\n", npages, tbl); | |
327 | return bad_dma_address; | |
328 | } | |
329 | ||
3cc39bda | 330 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
331 | unsigned int npages) |
332 | { | |
333 | unsigned long entry; | |
796e4390 | 334 | unsigned long badbit; |
310adfdd | 335 | unsigned long badend; |
820a1497 | 336 | unsigned long flags; |
310adfdd MBY |
337 | |
338 | /* were we called with bad_dma_address? */ | |
339 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
340 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
341 | printk(KERN_ERR "Calgary: driver tried unmapping bad DMA " | |
342 | "address 0x%Lx\n", dma_addr); | |
343 | WARN_ON(1); | |
344 | return; | |
345 | } | |
e465058d JM |
346 | |
347 | entry = dma_addr >> PAGE_SHIFT; | |
348 | ||
349 | BUG_ON(entry + npages > tbl->it_size); | |
350 | ||
351 | tce_free(tbl, entry, npages); | |
352 | ||
820a1497 MBY |
353 | spin_lock_irqsave(&tbl->it_lock, flags); |
354 | ||
796e4390 MBY |
355 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
356 | if (badbit != ~0UL) { | |
357 | if (printk_ratelimit()) | |
e465058d JM |
358 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
359 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 360 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
361 | } |
362 | ||
1b39b077 | 363 | iommu_area_free(tbl->it_map, entry, npages); |
820a1497 MBY |
364 | |
365 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
366 | } |
367 | ||
35b6dfa0 MBY |
368 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
369 | { | |
8a244590 MBY |
370 | struct pci_dev *pdev; |
371 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
372 | struct iommu_table *tbl; |
373 | ||
8a244590 MBY |
374 | pdev = to_pci_dev(dev); |
375 | ||
f055a061 MFB |
376 | pbus = pdev->bus; |
377 | ||
378 | /* is the device behind a bridge? Look for the root bus */ | |
379 | while (pbus->parent) | |
380 | pbus = pbus->parent; | |
8a244590 | 381 | |
08f1c192 | 382 | tbl = pci_iommu(pbus); |
7354b075 | 383 | |
f055a061 | 384 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
385 | |
386 | return tbl; | |
387 | } | |
388 | ||
3cc39bda | 389 | static void calgary_unmap_sg(struct device *dev, |
e465058d JM |
390 | struct scatterlist *sglist, int nelems, int direction) |
391 | { | |
3cc39bda | 392 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
393 | struct scatterlist *s; |
394 | int i; | |
3cc39bda | 395 | |
bc3c6058 | 396 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
397 | return; |
398 | ||
8b87d9f4 | 399 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 400 | unsigned int npages; |
8b87d9f4 JA |
401 | dma_addr_t dma = s->dma_address; |
402 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
403 | |
404 | if (dmalen == 0) | |
405 | break; | |
406 | ||
407 | npages = num_dma_pages(dma, dmalen); | |
3cc39bda | 408 | iommu_free(tbl, dma, npages); |
e465058d JM |
409 | } |
410 | } | |
411 | ||
e465058d JM |
412 | static int calgary_nontranslate_map_sg(struct device* dev, |
413 | struct scatterlist *sg, int nelems, int direction) | |
414 | { | |
8b87d9f4 | 415 | struct scatterlist *s; |
e465058d JM |
416 | int i; |
417 | ||
8b87d9f4 | 418 | for_each_sg(sg, s, nelems, i) { |
58b053e4 JA |
419 | struct page *p = sg_page(s); |
420 | ||
421 | BUG_ON(!p); | |
422 | s->dma_address = virt_to_bus(sg_virt(s)); | |
e465058d JM |
423 | s->dma_length = s->length; |
424 | } | |
425 | return nelems; | |
426 | } | |
427 | ||
0b11e1c6 | 428 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
e465058d JM |
429 | int nelems, int direction) |
430 | { | |
35b6dfa0 | 431 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 432 | struct scatterlist *s; |
e465058d JM |
433 | unsigned long vaddr; |
434 | unsigned int npages; | |
435 | unsigned long entry; | |
436 | int i; | |
437 | ||
d588ba8c | 438 | if (!translation_enabled(tbl)) |
e465058d JM |
439 | return calgary_nontranslate_map_sg(dev, sg, nelems, direction); |
440 | ||
8b87d9f4 | 441 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 442 | BUG_ON(!sg_page(s)); |
e465058d | 443 | |
58b053e4 | 444 | vaddr = (unsigned long) sg_virt(s); |
e465058d JM |
445 | npages = num_dma_pages(vaddr, s->length); |
446 | ||
1b39b077 | 447 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d JM |
448 | if (entry == bad_dma_address) { |
449 | /* makes sure unmap knows to stop */ | |
450 | s->dma_length = 0; | |
451 | goto error; | |
452 | } | |
453 | ||
454 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
455 | ||
456 | /* insert into HW table */ | |
457 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
458 | direction); | |
459 | ||
460 | s->dma_length = s->length; | |
461 | } | |
462 | ||
e465058d JM |
463 | return nelems; |
464 | error: | |
3cc39bda | 465 | calgary_unmap_sg(dev, sg, nelems, direction); |
8b87d9f4 JA |
466 | for_each_sg(sg, s, nelems, i) { |
467 | sg->dma_address = bad_dma_address; | |
468 | sg->dma_length = 0; | |
e465058d | 469 | } |
e465058d JM |
470 | return 0; |
471 | } | |
472 | ||
2be62149 | 473 | static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr, |
e465058d JM |
474 | size_t size, int direction) |
475 | { | |
476 | dma_addr_t dma_handle = bad_dma_address; | |
2be62149 | 477 | void *vaddr = phys_to_virt(paddr); |
e465058d JM |
478 | unsigned long uaddr; |
479 | unsigned int npages; | |
35b6dfa0 | 480 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
481 | |
482 | uaddr = (unsigned long)vaddr; | |
483 | npages = num_dma_pages(uaddr, size); | |
484 | ||
d588ba8c | 485 | if (translation_enabled(tbl)) |
1b39b077 | 486 | dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction); |
e465058d JM |
487 | else |
488 | dma_handle = virt_to_bus(vaddr); | |
489 | ||
490 | return dma_handle; | |
491 | } | |
492 | ||
0b11e1c6 | 493 | static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, |
e465058d JM |
494 | size_t size, int direction) |
495 | { | |
35b6dfa0 | 496 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
497 | unsigned int npages; |
498 | ||
d588ba8c | 499 | if (!translation_enabled(tbl)) |
e465058d JM |
500 | return; |
501 | ||
502 | npages = num_dma_pages(dma_handle, size); | |
503 | iommu_free(tbl, dma_handle, npages); | |
504 | } | |
505 | ||
0b11e1c6 | 506 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
e465058d JM |
507 | dma_addr_t *dma_handle, gfp_t flag) |
508 | { | |
509 | void *ret = NULL; | |
510 | dma_addr_t mapping; | |
511 | unsigned int npages, order; | |
35b6dfa0 | 512 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
513 | |
514 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
515 | npages = size >> PAGE_SHIFT; | |
516 | order = get_order(size); | |
517 | ||
518 | /* alloc enough pages (and possibly more) */ | |
519 | ret = (void *)__get_free_pages(flag, order); | |
520 | if (!ret) | |
521 | goto error; | |
522 | memset(ret, 0, size); | |
523 | ||
d588ba8c | 524 | if (translation_enabled(tbl)) { |
e465058d | 525 | /* set up tces to cover the allocated range */ |
1b39b077 | 526 | mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL); |
e465058d JM |
527 | if (mapping == bad_dma_address) |
528 | goto free; | |
529 | ||
530 | *dma_handle = mapping; | |
531 | } else /* non translated slot */ | |
532 | *dma_handle = virt_to_bus(ret); | |
533 | ||
534 | return ret; | |
535 | ||
536 | free: | |
537 | free_pages((unsigned long)ret, get_order(size)); | |
538 | ret = NULL; | |
539 | error: | |
540 | return ret; | |
541 | } | |
542 | ||
e6584504 | 543 | static const struct dma_mapping_ops calgary_dma_ops = { |
e465058d JM |
544 | .alloc_coherent = calgary_alloc_coherent, |
545 | .map_single = calgary_map_single, | |
546 | .unmap_single = calgary_unmap_single, | |
547 | .map_sg = calgary_map_sg, | |
548 | .unmap_sg = calgary_unmap_sg, | |
549 | }; | |
550 | ||
b34e90b8 LV |
551 | static inline void __iomem * busno_to_bbar(unsigned char num) |
552 | { | |
553 | return bus_info[num].bbar; | |
554 | } | |
555 | ||
e465058d JM |
556 | static inline int busno_to_phbid(unsigned char num) |
557 | { | |
f38db651 | 558 | return bus_info[num].phbid; |
e465058d JM |
559 | } |
560 | ||
561 | static inline unsigned long split_queue_offset(unsigned char num) | |
562 | { | |
563 | size_t idx = busno_to_phbid(num); | |
564 | ||
565 | return split_queue_offsets[idx]; | |
566 | } | |
567 | ||
568 | static inline unsigned long tar_offset(unsigned char num) | |
569 | { | |
570 | size_t idx = busno_to_phbid(num); | |
571 | ||
572 | return tar_offsets[idx]; | |
573 | } | |
574 | ||
575 | static inline unsigned long phb_offset(unsigned char num) | |
576 | { | |
577 | size_t idx = busno_to_phbid(num); | |
578 | ||
579 | return phb_offsets[idx]; | |
580 | } | |
581 | ||
582 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
583 | { | |
584 | unsigned long target = ((unsigned long)bar) | offset; | |
585 | return (void __iomem*)target; | |
586 | } | |
587 | ||
8a244590 MBY |
588 | static inline int is_calioc2(unsigned short device) |
589 | { | |
590 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
591 | } | |
592 | ||
593 | static inline int is_calgary(unsigned short device) | |
594 | { | |
595 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
596 | } | |
597 | ||
598 | static inline int is_cal_pci_dev(unsigned short device) | |
599 | { | |
600 | return (is_calgary(device) || is_calioc2(device)); | |
601 | } | |
602 | ||
ff297b8c | 603 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
604 | { |
605 | u64 val; | |
606 | u32 aer; | |
607 | int i = 0; | |
608 | void __iomem *bbar = tbl->bbar; | |
609 | void __iomem *target; | |
610 | ||
611 | /* disable arbitration on the bus */ | |
612 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
613 | aer = readl(target); | |
614 | writel(0, target); | |
615 | ||
616 | /* read plssr to ensure it got there */ | |
617 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
618 | val = readl(target); | |
619 | ||
620 | /* poll split queues until all DMA activity is done */ | |
621 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
622 | do { | |
623 | val = readq(target); | |
624 | i++; | |
625 | } while ((val & 0xff) != 0xff && i < 100); | |
626 | if (i == 100) | |
627 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
628 | "continuing anyway\n"); | |
629 | ||
630 | /* invalidate TCE cache */ | |
631 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
632 | writeq(tbl->tar_val, target); | |
633 | ||
634 | /* enable arbitration */ | |
635 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
636 | writel(aer, target); | |
637 | (void)readl(target); /* flush */ | |
638 | } | |
639 | ||
00be3fa4 MBY |
640 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
641 | { | |
642 | void __iomem *bbar = tbl->bbar; | |
643 | void __iomem *target; | |
644 | u64 val64; | |
645 | u32 val; | |
646 | int i = 0; | |
647 | int count = 1; | |
648 | unsigned char bus = tbl->it_busno; | |
649 | ||
650 | begin: | |
651 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
652 | "sequence - count %d\n", bus, count); | |
653 | ||
654 | /* 1. using the Page Migration Control reg set SoftStop */ | |
655 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
656 | val = be32_to_cpu(readl(target)); | |
657 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
658 | val |= PMR_SOFTSTOP; | |
659 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
660 | writel(cpu_to_be32(val), target); | |
661 | ||
662 | /* 2. poll split queues until all DMA activity is done */ | |
663 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
664 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
665 | do { | |
666 | val64 = readq(target); | |
667 | i++; | |
668 | } while ((val64 & 0xff) != 0xff && i < 100); | |
669 | if (i == 100) | |
670 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | |
671 | "continuing anyway\n"); | |
672 | ||
673 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
674 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
675 | val = be32_to_cpu(readl(target)); | |
676 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
677 | ||
678 | /* 4. if SoftStopFault - goto (1) */ | |
679 | if (val & PMR_SOFTSTOPFAULT) { | |
680 | if (++count < 100) | |
681 | goto begin; | |
682 | else { | |
683 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | |
684 | "aborting TCE cache flush sequence!\n"); | |
685 | return; /* pray for the best */ | |
686 | } | |
687 | } | |
688 | ||
689 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
690 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
691 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
692 | val = be32_to_cpu(readl(target)); | |
693 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
694 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
695 | val = be32_to_cpu(readl(target)); | |
696 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
697 | ||
698 | /* 6. invalidate TCE cache */ | |
699 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
700 | target = calgary_reg(bbar, tar_offset(bus)); | |
701 | writeq(tbl->tar_val, target); | |
702 | ||
703 | /* 7. Re-read PMCR */ | |
704 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
705 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
706 | val = be32_to_cpu(readl(target)); | |
707 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
708 | ||
709 | /* 8. Remove HardStop */ | |
710 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
711 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
712 | val = 0; | |
713 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
714 | writel(cpu_to_be32(val), target); | |
715 | val = be32_to_cpu(readl(target)); | |
716 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
717 | } | |
718 | ||
e465058d JM |
719 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
720 | u64 limit) | |
721 | { | |
722 | unsigned int numpages; | |
723 | ||
724 | limit = limit | 0xfffff; | |
725 | limit++; | |
726 | ||
727 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 728 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
729 | } |
730 | ||
731 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
732 | { | |
733 | void __iomem *target; | |
734 | u64 low, high, sizelow; | |
735 | u64 start, limit; | |
08f1c192 | 736 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
737 | unsigned char busnum = dev->bus->number; |
738 | void __iomem *bbar = tbl->bbar; | |
739 | ||
740 | /* peripheral MEM_1 region */ | |
741 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
742 | low = be32_to_cpu(readl(target)); | |
743 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
744 | high = be32_to_cpu(readl(target)); | |
745 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
746 | sizelow = be32_to_cpu(readl(target)); | |
747 | ||
748 | start = (high << 32) | low; | |
749 | limit = sizelow; | |
750 | ||
751 | calgary_reserve_mem_region(dev, start, limit); | |
752 | } | |
753 | ||
754 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
755 | { | |
756 | void __iomem *target; | |
757 | u32 val32; | |
758 | u64 low, high, sizelow, sizehigh; | |
759 | u64 start, limit; | |
08f1c192 | 760 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
761 | unsigned char busnum = dev->bus->number; |
762 | void __iomem *bbar = tbl->bbar; | |
763 | ||
764 | /* is it enabled? */ | |
765 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
766 | val32 = be32_to_cpu(readl(target)); | |
767 | if (!(val32 & PHB_MEM2_ENABLE)) | |
768 | return; | |
769 | ||
770 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
771 | low = be32_to_cpu(readl(target)); | |
772 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
773 | high = be32_to_cpu(readl(target)); | |
774 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
775 | sizelow = be32_to_cpu(readl(target)); | |
776 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
777 | sizehigh = be32_to_cpu(readl(target)); | |
778 | ||
779 | start = (high << 32) | low; | |
780 | limit = (sizehigh << 32) | sizelow; | |
781 | ||
782 | calgary_reserve_mem_region(dev, start, limit); | |
783 | } | |
784 | ||
785 | /* | |
786 | * some regions of the IO address space do not get translated, so we | |
787 | * must not give devices IO addresses in those regions. The regions | |
788 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
789 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
790 | * later. | |
791 | */ | |
792 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
793 | { | |
794 | unsigned int npages; | |
e465058d | 795 | u64 start; |
08f1c192 | 796 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 797 | |
310adfdd MBY |
798 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
799 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
800 | |
801 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 802 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
803 | if (is_calgary(dev->device)) { |
804 | start = (640 * 1024); | |
805 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
806 | } else { /* calioc2 */ | |
807 | start = 0; | |
e8f20414 | 808 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 809 | } |
e465058d JM |
810 | iommu_range_reserve(tbl, start, npages); |
811 | ||
812 | /* reserve the two PCI peripheral memory regions in IO space */ | |
813 | calgary_reserve_peripheral_mem_1(dev); | |
814 | calgary_reserve_peripheral_mem_2(dev); | |
815 | } | |
816 | ||
817 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
818 | { | |
819 | u64 val64; | |
820 | u64 table_phys; | |
821 | void __iomem *target; | |
822 | int ret; | |
823 | struct iommu_table *tbl; | |
824 | ||
825 | /* build TCE tables for each PHB */ | |
826 | ret = build_tce_table(dev, bbar); | |
827 | if (ret) | |
828 | return ret; | |
829 | ||
08f1c192 | 830 | tbl = pci_iommu(dev->bus); |
f38db651 MBY |
831 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
832 | tce_free(tbl, 0, tbl->it_size); | |
833 | ||
8bcf7705 MBY |
834 | if (is_calgary(dev->device)) |
835 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
836 | else if (is_calioc2(dev->device)) |
837 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
838 | else |
839 | BUG(); | |
ff297b8c | 840 | |
e465058d JM |
841 | calgary_reserve_regions(dev); |
842 | ||
843 | /* set TARs for each PHB */ | |
844 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
845 | val64 = be64_to_cpu(readq(target)); | |
846 | ||
847 | /* zero out all TAR bits under sw control */ | |
848 | val64 &= ~TAR_SW_BITS; | |
e465058d | 849 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 850 | |
e465058d JM |
851 | val64 |= table_phys; |
852 | ||
853 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
854 | val64 |= (u64) specified_table_size; | |
855 | ||
856 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 857 | |
e465058d JM |
858 | writeq(tbl->tar_val, target); |
859 | readq(target); /* flush */ | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
b8f4fe66 | 864 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
865 | { |
866 | u64 val64; | |
08f1c192 | 867 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 868 | void __iomem *target; |
b8f4fe66 | 869 | unsigned int bitmapsz; |
e465058d JM |
870 | |
871 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
872 | val64 = be64_to_cpu(readq(target)); | |
873 | val64 &= ~TAR_SW_BITS; | |
874 | writeq(cpu_to_be64(val64), target); | |
875 | readq(target); /* flush */ | |
876 | ||
b8f4fe66 MBY |
877 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
878 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
879 | tbl->it_map = NULL; | |
880 | ||
e465058d | 881 | kfree(tbl); |
08f1c192 MBY |
882 | |
883 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
884 | |
885 | /* Can't free bootmem allocated memory after system is up :-( */ | |
886 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
887 | } |
888 | ||
8a244590 MBY |
889 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
890 | { | |
891 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 892 | void __iomem *target; |
ddbd41b4 | 893 | u32 csr, plssr; |
8cb32dc7 MBY |
894 | |
895 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
896 | csr = be32_to_cpu(readl(target)); |
897 | ||
898 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
899 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
900 | |
901 | /* If no error, the agent ID in the CSR is not valid */ | |
902 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | |
ddbd41b4 | 903 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); |
8cb32dc7 MBY |
904 | } |
905 | ||
906 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
907 | { | |
908 | void __iomem *bbar = tbl->bbar; | |
909 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
910 | void __iomem *target; |
911 | unsigned long phboff = phb_offset(tbl->it_busno); | |
912 | unsigned long erroff; | |
913 | u32 errregs[7]; | |
914 | int i; | |
915 | ||
916 | /* dump CSR */ | |
917 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
918 | csr = be32_to_cpu(readl(target)); | |
919 | /* dump PLSSR */ | |
920 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
921 | plssr = be32_to_cpu(readl(target)); | |
922 | /* dump CSMR */ | |
923 | target = calgary_reg(bbar, phboff | 0x290); | |
924 | csmr = be32_to_cpu(readl(target)); | |
925 | /* dump mck */ | |
926 | target = calgary_reg(bbar, phboff | 0x800); | |
927 | mck = be32_to_cpu(readl(target)); | |
928 | ||
8cb32dc7 MBY |
929 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", |
930 | tbl->it_busno); | |
931 | ||
932 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | |
933 | csr, plssr, csmr, mck); | |
8a244590 MBY |
934 | |
935 | /* dump rest of error regs */ | |
936 | printk(KERN_EMERG "Calgary: "); | |
937 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
7354b075 MBY |
938 | /* err regs are at 0x810 - 0x870 */ |
939 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
940 | target = calgary_reg(bbar, phboff | erroff); |
941 | errregs[i] = be32_to_cpu(readl(target)); | |
942 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
943 | } | |
944 | printk("\n"); | |
8cb32dc7 MBY |
945 | |
946 | /* root complex status */ | |
947 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
948 | rcstat = be32_to_cpu(readl(target)); | |
949 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
950 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
951 | } |
952 | ||
e465058d JM |
953 | static void calgary_watchdog(unsigned long data) |
954 | { | |
955 | struct pci_dev *dev = (struct pci_dev *)data; | |
08f1c192 | 956 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
957 | void __iomem *bbar = tbl->bbar; |
958 | u32 val32; | |
959 | void __iomem *target; | |
960 | ||
961 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
962 | val32 = be32_to_cpu(readl(target)); | |
963 | ||
964 | /* If no error, the agent ID in the CSR is not valid */ | |
965 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 966 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
967 | |
968 | /* reset error */ | |
e465058d JM |
969 | writel(0, target); |
970 | ||
971 | /* Disable bus that caused the error */ | |
972 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 973 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
974 | val32 = be32_to_cpu(readl(target)); |
975 | val32 |= PHB_SLOT_DISABLE; | |
976 | writel(cpu_to_be32(val32), target); | |
977 | readl(target); /* flush */ | |
978 | } else { | |
979 | /* Reset the timer */ | |
980 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
981 | } | |
982 | } | |
983 | ||
a2b663f6 MBY |
984 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
985 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
986 | { |
987 | u64 val64; | |
988 | void __iomem *target; | |
58db8548 | 989 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
990 | u64 mask; |
991 | ||
992 | switch (busno_to_phbid(busnum)) { | |
993 | case 0: phb_shift = (63 - 19); | |
994 | break; | |
995 | case 1: phb_shift = (63 - 23); | |
996 | break; | |
997 | case 2: phb_shift = (63 - 27); | |
998 | break; | |
999 | case 3: phb_shift = (63 - 35); | |
1000 | break; | |
1001 | default: | |
1002 | BUG_ON(busno_to_phbid(busnum)); | |
1003 | } | |
1004 | ||
1005 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
1006 | val64 = be64_to_cpu(readq(target)); | |
1007 | ||
1008 | /* zero out this PHB's timer bits */ | |
1009 | mask = ~(0xFUL << phb_shift); | |
1010 | val64 &= mask; | |
a2b663f6 | 1011 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
1012 | writeq(cpu_to_be64(val64), target); |
1013 | readq(target); /* flush */ | |
1014 | } | |
1015 | ||
31f3dff6 | 1016 | static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
c3860108 MBY |
1017 | { |
1018 | unsigned char busnum = dev->bus->number; | |
1019 | void __iomem *bbar = tbl->bbar; | |
1020 | void __iomem *target; | |
1021 | u32 val; | |
1022 | ||
8bcf7705 MBY |
1023 | /* |
1024 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
1025 | */ | |
1026 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
1027 | val = cpu_to_be32(readl(target)); | |
1028 | val |= 0x00800000; | |
1029 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
1030 | } |
1031 | ||
31f3dff6 | 1032 | static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
b8d2ea1b MBY |
1033 | { |
1034 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
1035 | |
1036 | /* | |
1037 | * Give split completion a longer timeout on bus 1 for aic94xx | |
1038 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
1039 | */ | |
c3860108 | 1040 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
1041 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
1042 | CCR_2SEC_TIMEOUT); | |
1043 | } | |
1044 | ||
e465058d JM |
1045 | static void __init calgary_enable_translation(struct pci_dev *dev) |
1046 | { | |
1047 | u32 val32; | |
1048 | unsigned char busnum; | |
1049 | void __iomem *target; | |
1050 | void __iomem *bbar; | |
1051 | struct iommu_table *tbl; | |
1052 | ||
1053 | busnum = dev->bus->number; | |
08f1c192 | 1054 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1055 | bbar = tbl->bbar; |
1056 | ||
1057 | /* enable TCE in PHB Config Register */ | |
1058 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1059 | val32 = be32_to_cpu(readl(target)); | |
1060 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
1061 | ||
8a244590 MBY |
1062 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
1063 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
1064 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1065 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1066 | "bus.\n"); | |
1067 | ||
1068 | writel(cpu_to_be32(val32), target); | |
1069 | readl(target); /* flush */ | |
1070 | ||
1071 | init_timer(&tbl->watchdog_timer); | |
1072 | tbl->watchdog_timer.function = &calgary_watchdog; | |
1073 | tbl->watchdog_timer.data = (unsigned long)dev; | |
1074 | mod_timer(&tbl->watchdog_timer, jiffies); | |
1075 | } | |
1076 | ||
1077 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1078 | { | |
1079 | u32 val32; | |
1080 | unsigned char busnum; | |
1081 | void __iomem *target; | |
1082 | void __iomem *bbar; | |
1083 | struct iommu_table *tbl; | |
1084 | ||
1085 | busnum = dev->bus->number; | |
08f1c192 | 1086 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1087 | bbar = tbl->bbar; |
1088 | ||
1089 | /* disable TCE in PHB Config Register */ | |
1090 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1091 | val32 = be32_to_cpu(readl(target)); | |
1092 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1093 | ||
70d666d6 | 1094 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1095 | writel(cpu_to_be32(val32), target); |
1096 | readl(target); /* flush */ | |
1097 | ||
1098 | del_timer_sync(&tbl->watchdog_timer); | |
1099 | } | |
1100 | ||
a4fc520a | 1101 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1102 | { |
871b1700 | 1103 | pci_dev_get(dev); |
08f1c192 | 1104 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1105 | |
1106 | /* is the device behind a bridge? */ | |
1107 | if (dev->bus->parent) | |
1108 | dev->bus->parent->self = dev; | |
1109 | else | |
1110 | dev->bus->self = dev; | |
e465058d JM |
1111 | } |
1112 | ||
1113 | static int __init calgary_init_one(struct pci_dev *dev) | |
1114 | { | |
e465058d | 1115 | void __iomem *bbar; |
ff297b8c | 1116 | struct iommu_table *tbl; |
e465058d JM |
1117 | int ret; |
1118 | ||
dedc9937 JM |
1119 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1120 | ||
eae93755 | 1121 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1122 | ret = calgary_setup_tar(dev, bbar); |
1123 | if (ret) | |
eae93755 | 1124 | goto done; |
e465058d | 1125 | |
871b1700 | 1126 | pci_dev_get(dev); |
8a244590 MBY |
1127 | |
1128 | if (dev->bus->parent) { | |
1129 | if (dev->bus->parent->self) | |
1130 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1131 | "bus->parent->self!\n", dev); | |
1132 | dev->bus->parent->self = dev; | |
1133 | } else | |
1134 | dev->bus->self = dev; | |
b8d2ea1b | 1135 | |
08f1c192 | 1136 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1137 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1138 | |
e465058d JM |
1139 | calgary_enable_translation(dev); |
1140 | ||
1141 | return 0; | |
1142 | ||
e465058d JM |
1143 | done: |
1144 | return ret; | |
1145 | } | |
1146 | ||
eae93755 | 1147 | static int __init calgary_locate_bbars(void) |
e465058d | 1148 | { |
eae93755 MBY |
1149 | int ret; |
1150 | int rioidx, phb, bus; | |
b34e90b8 LV |
1151 | void __iomem *bbar; |
1152 | void __iomem *target; | |
eae93755 | 1153 | unsigned long offset; |
b34e90b8 LV |
1154 | u8 start_bus, end_bus; |
1155 | u32 val; | |
1156 | ||
eae93755 MBY |
1157 | ret = -ENODATA; |
1158 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1159 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1160 | |
eae93755 | 1161 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1162 | continue; |
1163 | ||
1164 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1165 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1166 | if (!bbar) | |
1167 | goto error; | |
b34e90b8 LV |
1168 | |
1169 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1170 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1171 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1172 | |
b34e90b8 | 1173 | val = be32_to_cpu(readl(target)); |
8a244590 | 1174 | |
b34e90b8 | 1175 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1176 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1177 | |
1178 | if (end_bus) { | |
1179 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1180 | bus_info[bus].bbar = bbar; | |
1181 | bus_info[bus].phbid = phb; | |
1182 | } | |
1183 | } else { | |
1184 | bus_info[start_bus].bbar = bbar; | |
1185 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1186 | } |
1187 | } | |
1188 | } | |
1189 | ||
eae93755 MBY |
1190 | return 0; |
1191 | ||
1192 | error: | |
1193 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1194 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1195 | if (bus_info[bus].bbar) | |
1196 | iounmap(bus_info[bus].bbar); | |
1197 | ||
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | static int __init calgary_init(void) | |
1202 | { | |
1203 | int ret; | |
1204 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1205 | struct calgary_bus_info *info; |
eae93755 MBY |
1206 | |
1207 | ret = calgary_locate_bbars(); | |
1208 | if (ret) | |
1209 | return ret; | |
e465058d | 1210 | |
dedc9937 | 1211 | do { |
8a244590 | 1212 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1213 | if (!dev) |
1214 | break; | |
8a244590 MBY |
1215 | if (!is_cal_pci_dev(dev->device)) |
1216 | continue; | |
bc3c6058 MBY |
1217 | |
1218 | info = &bus_info[dev->bus->number]; | |
1219 | if (info->translation_disabled) { | |
e465058d JM |
1220 | calgary_init_one_nontraslated(dev); |
1221 | continue; | |
1222 | } | |
bc3c6058 MBY |
1223 | |
1224 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1225 | continue; |
12de257b | 1226 | |
e465058d JM |
1227 | ret = calgary_init_one(dev); |
1228 | if (ret) | |
1229 | goto error; | |
dedc9937 | 1230 | } while (1); |
e465058d JM |
1231 | |
1232 | return ret; | |
1233 | ||
1234 | error: | |
dedc9937 | 1235 | do { |
a2b5d877 | 1236 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
9f2dc46d MBY |
1237 | if (!dev) |
1238 | break; | |
8a244590 MBY |
1239 | if (!is_cal_pci_dev(dev->device)) |
1240 | continue; | |
bc3c6058 MBY |
1241 | |
1242 | info = &bus_info[dev->bus->number]; | |
1243 | if (info->translation_disabled) { | |
e465058d JM |
1244 | pci_dev_put(dev); |
1245 | continue; | |
1246 | } | |
bc3c6058 | 1247 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1248 | continue; |
871b1700 | 1249 | |
e465058d | 1250 | calgary_disable_translation(dev); |
b8f4fe66 | 1251 | calgary_free_bus(dev); |
871b1700 | 1252 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
dedc9937 | 1253 | } while (1); |
e465058d JM |
1254 | |
1255 | return ret; | |
1256 | } | |
1257 | ||
1258 | static inline int __init determine_tce_table_size(u64 ram) | |
1259 | { | |
1260 | int ret; | |
1261 | ||
1262 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1263 | return specified_table_size; | |
1264 | ||
1265 | /* | |
1266 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1267 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1268 | * larger table size has twice as many entries, so shift the | |
1269 | * max ram address by 13 to divide by 8K and then look at the | |
1270 | * order of the result to choose between 0-7. | |
1271 | */ | |
1272 | ret = get_order(ram >> 13); | |
1273 | if (ret > TCE_TABLE_SIZE_8M) | |
1274 | ret = TCE_TABLE_SIZE_8M; | |
1275 | ||
1276 | return ret; | |
1277 | } | |
1278 | ||
b34e90b8 LV |
1279 | static int __init build_detail_arrays(void) |
1280 | { | |
1281 | unsigned long ptr; | |
1282 | int i, scal_detail_size, rio_detail_size; | |
1283 | ||
1284 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){ | |
1285 | printk(KERN_WARNING | |
eae93755 | 1286 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 LV |
1287 | "but system has %d nodes.\n", |
1288 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1289 | return -ENODEV; | |
1290 | } | |
1291 | ||
1292 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1293 | case 2: |
1294 | scal_detail_size = 11; | |
1295 | rio_detail_size = 13; | |
1296 | break; | |
1297 | case 3: | |
1298 | scal_detail_size = 12; | |
1299 | rio_detail_size = 15; | |
1300 | break; | |
eae93755 MBY |
1301 | default: |
1302 | printk(KERN_WARNING | |
1303 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1304 | rio_table_hdr->version); | |
1305 | return -EPROTO; | |
b34e90b8 LV |
1306 | } |
1307 | ||
1308 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
1309 | for (i = 0; i < rio_table_hdr->num_scal_dev; | |
1310 | i++, ptr += scal_detail_size) | |
1311 | scal_devs[i] = (struct scal_detail *)ptr; | |
1312 | ||
1313 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1314 | i++, ptr += rio_detail_size) | |
1315 | rio_devs[i] = (struct rio_detail *)ptr; | |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
8a244590 | 1320 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1321 | { |
8a244590 | 1322 | int dev; |
e465058d | 1323 | u32 val; |
8a244590 MBY |
1324 | |
1325 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1326 | /* | |
1327 | * FIXME: properly scan for devices accross the | |
1328 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1329 | */ | |
1330 | return 1; | |
1331 | } | |
1332 | ||
1333 | for (dev = 1; dev < 8; dev++) { | |
1334 | val = read_pci_config(bus, dev, 0, 0); | |
1335 | if (val != 0xffffffff) | |
1336 | break; | |
1337 | } | |
1338 | return (val != 0xffffffff); | |
1339 | } | |
1340 | ||
1341 | void __init detect_calgary(void) | |
1342 | { | |
d2105b10 | 1343 | int bus; |
e465058d | 1344 | void *tbl; |
d2105b10 | 1345 | int calgary_found = 0; |
b34e90b8 | 1346 | unsigned long ptr; |
136f1e7a | 1347 | unsigned int offset, prev_offset; |
eae93755 | 1348 | int ret; |
e465058d JM |
1349 | |
1350 | /* | |
1351 | * if the user specified iommu=off or iommu=soft or we found | |
1352 | * another HW IOMMU already, bail out. | |
1353 | */ | |
1354 | if (swiotlb || no_iommu || iommu_detected) | |
1355 | return; | |
1356 | ||
bff6547b MBY |
1357 | if (!use_calgary) |
1358 | return; | |
1359 | ||
0637a70a AK |
1360 | if (!early_pci_allowed()) |
1361 | return; | |
1362 | ||
b92cc559 MBY |
1363 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1364 | ||
b34e90b8 LV |
1365 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1366 | ||
1367 | rio_table_hdr = NULL; | |
136f1e7a | 1368 | prev_offset = 0; |
b34e90b8 | 1369 | offset = 0x180; |
136f1e7a IM |
1370 | /* |
1371 | * The next offset is stored in the 1st word. | |
1372 | * Only parse up until the offset increases: | |
1373 | */ | |
1374 | while (offset > prev_offset) { | |
b34e90b8 LV |
1375 | /* The block id is stored in the 2nd word */ |
1376 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1377 | /* set the pointer past the offset & block id */ | |
eae93755 | 1378 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1379 | break; |
1380 | } | |
136f1e7a | 1381 | prev_offset = offset; |
b34e90b8 LV |
1382 | offset = *((unsigned short *)(ptr + offset)); |
1383 | } | |
eae93755 | 1384 | if (!rio_table_hdr) { |
b92cc559 MBY |
1385 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1386 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1387 | return; |
1388 | } | |
1389 | ||
eae93755 MBY |
1390 | ret = build_detail_arrays(); |
1391 | if (ret) { | |
b92cc559 | 1392 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1393 | return; |
eae93755 | 1394 | } |
b34e90b8 | 1395 | |
e465058d JM |
1396 | specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE); |
1397 | ||
d2105b10 | 1398 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1399 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1400 | unsigned short pci_device; |
1401 | u32 val; | |
1402 | ||
1403 | val = read_pci_config(bus, 0, 0, 0); | |
1404 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1405 | |
8a244590 | 1406 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1407 | continue; |
d2105b10 | 1408 | |
f38db651 | 1409 | if (info->translation_disabled) |
e465058d | 1410 | continue; |
f38db651 | 1411 | |
8a244590 MBY |
1412 | if (calgary_bus_has_devices(bus, pci_device) || |
1413 | translate_empty_slots) { | |
1414 | tbl = alloc_tce_table(); | |
1415 | if (!tbl) | |
1416 | goto cleanup; | |
1417 | info->tce_space = tbl; | |
1418 | calgary_found = 1; | |
d2105b10 | 1419 | } |
e465058d JM |
1420 | } |
1421 | ||
b92cc559 MBY |
1422 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1423 | calgary_found ? "found" : "not found"); | |
1424 | ||
d2105b10 | 1425 | if (calgary_found) { |
e465058d JM |
1426 | iommu_detected = 1; |
1427 | calgary_detected = 1; | |
de684652 MBY |
1428 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1429 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1430 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1431 | debugging ? "enabled" : "disabled"); | |
e465058d JM |
1432 | } |
1433 | return; | |
1434 | ||
1435 | cleanup: | |
f38db651 MBY |
1436 | for (--bus; bus >= 0; --bus) { |
1437 | struct calgary_bus_info *info = &bus_info[bus]; | |
1438 | ||
1439 | if (info->tce_space) | |
1440 | free_tce_table(info->tce_space); | |
1441 | } | |
e465058d JM |
1442 | } |
1443 | ||
1444 | int __init calgary_iommu_init(void) | |
1445 | { | |
1446 | int ret; | |
1447 | ||
1448 | if (no_iommu || swiotlb) | |
1449 | return -ENODEV; | |
1450 | ||
1451 | if (!calgary_detected) | |
1452 | return -ENODEV; | |
1453 | ||
1454 | /* ok, we're trying to use Calgary - let's roll */ | |
1455 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1456 | ||
1457 | ret = calgary_init(); | |
1458 | if (ret) { | |
1459 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1460 | "falling back to no_iommu\n", ret); | |
1461 | if (end_pfn > MAX_DMA32_PFN) | |
1462 | printk(KERN_ERR "WARNING more than 4GB of memory, " | |
1463 | "32bit PCI may malfunction.\n"); | |
1464 | return ret; | |
1465 | } | |
1466 | ||
1467 | force_iommu = 1; | |
310adfdd | 1468 | bad_dma_address = 0x0; |
e465058d JM |
1469 | dma_ops = &calgary_dma_ops; |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static int __init calgary_parse_options(char *p) | |
1475 | { | |
1476 | unsigned int bridge; | |
1477 | size_t len; | |
1478 | char* endp; | |
1479 | ||
1480 | while (*p) { | |
1481 | if (!strncmp(p, "64k", 3)) | |
1482 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1483 | else if (!strncmp(p, "128k", 4)) | |
1484 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1485 | else if (!strncmp(p, "256k", 4)) | |
1486 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1487 | else if (!strncmp(p, "512k", 4)) | |
1488 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1489 | else if (!strncmp(p, "1M", 2)) | |
1490 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1491 | else if (!strncmp(p, "2M", 2)) | |
1492 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1493 | else if (!strncmp(p, "4M", 2)) | |
1494 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1495 | else if (!strncmp(p, "8M", 2)) | |
1496 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1497 | ||
1498 | len = strlen("translate_empty_slots"); | |
1499 | if (!strncmp(p, "translate_empty_slots", len)) | |
1500 | translate_empty_slots = 1; | |
1501 | ||
1502 | len = strlen("disable"); | |
1503 | if (!strncmp(p, "disable", len)) { | |
1504 | p += len; | |
1505 | if (*p == '=') | |
1506 | ++p; | |
1507 | if (*p == '\0') | |
1508 | break; | |
1509 | bridge = simple_strtol(p, &endp, 0); | |
1510 | if (p == endp) | |
1511 | break; | |
1512 | ||
d2105b10 | 1513 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1514 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1515 | "translation for PHB %#x\n", bridge); |
f38db651 | 1516 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1517 | } |
1518 | } | |
1519 | ||
1520 | p = strpbrk(p, ","); | |
1521 | if (!p) | |
1522 | break; | |
1523 | ||
1524 | p++; /* skip ',' */ | |
1525 | } | |
1526 | return 1; | |
1527 | } | |
1528 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1529 | |
1530 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1531 | { | |
1532 | struct iommu_table *tbl; | |
1533 | unsigned int npages; | |
1534 | int i; | |
1535 | ||
08f1c192 | 1536 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1537 | |
1538 | for (i = 0; i < 4; i++) { | |
1539 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1540 | ||
1541 | /* Don't give out TCEs that map MEM resources */ | |
1542 | if (!(r->flags & IORESOURCE_MEM)) | |
1543 | continue; | |
1544 | ||
1545 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1546 | if (!r->start) | |
1547 | continue; | |
1548 | ||
1549 | /* cover the whole region */ | |
1550 | npages = (r->end - r->start) >> PAGE_SHIFT; | |
1551 | npages++; | |
1552 | ||
07877cf6 MBY |
1553 | iommu_range_reserve(tbl, r->start, npages); |
1554 | } | |
1555 | } | |
1556 | ||
1557 | static int __init calgary_fixup_tce_spaces(void) | |
1558 | { | |
1559 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1560 | struct calgary_bus_info *info; |
07877cf6 MBY |
1561 | |
1562 | if (no_iommu || swiotlb || !calgary_detected) | |
1563 | return -ENODEV; | |
1564 | ||
12de257b | 1565 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1566 | |
1567 | do { | |
1568 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1569 | if (!dev) | |
1570 | break; | |
1571 | if (!is_cal_pci_dev(dev->device)) | |
1572 | continue; | |
bc3c6058 MBY |
1573 | |
1574 | info = &bus_info[dev->bus->number]; | |
1575 | if (info->translation_disabled) | |
07877cf6 MBY |
1576 | continue; |
1577 | ||
bc3c6058 | 1578 | if (!info->tce_space) |
07877cf6 MBY |
1579 | continue; |
1580 | ||
1581 | calgary_fixup_one_tce_space(dev); | |
1582 | ||
1583 | } while (1); | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | /* | |
1589 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1590 | * and before device_initcall. | |
1591 | */ | |
1592 | rootfs_initcall(calgary_fixup_tce_spaces); |