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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
95b68dec | 32 | #include <linux/crash_dump.h> |
e465058d | 33 | #include <linux/dma-mapping.h> |
a66022c4 | 34 | #include <linux/bitmap.h> |
e465058d JM |
35 | #include <linux/pci_ids.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
8b87d9f4 | 38 | #include <linux/scatterlist.h> |
1b39b077 | 39 | #include <linux/iommu-helper.h> |
1956a96d | 40 | |
46a7fa27 | 41 | #include <asm/iommu.h> |
e465058d JM |
42 | #include <asm/calgary.h> |
43 | #include <asm/tce.h> | |
44 | #include <asm/pci-direct.h> | |
45 | #include <asm/system.h> | |
46 | #include <asm/dma.h> | |
b34e90b8 | 47 | #include <asm/rio.h> |
ae5830a6 | 48 | #include <asm/bios_ebda.h> |
d7b9f7be | 49 | #include <asm/x86_init.h> |
e465058d | 50 | |
bff6547b MBY |
51 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
52 | int use_calgary __read_mostly = 1; | |
53 | #else | |
54 | int use_calgary __read_mostly = 0; | |
55 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
56 | ||
e465058d | 57 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 58 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 59 | |
e465058d | 60 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
61 | #define CALGARY_CONFIG_REG 0x0108 |
62 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
63 | #define PHB_PLSSR_OFFSET 0x0120 |
64 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
65 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
66 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
67 | #define PHB_MEM_1_LOW 0x0190 | |
68 | #define PHB_MEM_1_HIGH 0x01A0 | |
69 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
70 | #define PHB_MEM_1_SIZE 0x01C0 | |
71 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
72 | #define PHB_AER_OFFSET 0x0200 | |
73 | #define PHB_CONFIG_0_HIGH 0x0220 | |
74 | #define PHB_CONFIG_0_LOW 0x0230 | |
75 | #define PHB_CONFIG_0_END 0x0240 | |
76 | #define PHB_MEM_2_LOW 0x02B0 | |
77 | #define PHB_MEM_2_HIGH 0x02C0 | |
78 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
79 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
80 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
81 | ||
c3860108 | 82 | /* CalIOC2 specific */ |
8bcf7705 MBY |
83 | #define PHB_SAVIOR_L2 0x0DB0 |
84 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
85 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 86 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 87 | |
e465058d JM |
88 | /* PHB_CONFIG_RW */ |
89 | #define PHB_TCE_ENABLE 0x20000000 | |
90 | #define PHB_SLOT_DISABLE 0x1C000000 | |
91 | #define PHB_DAC_DISABLE 0x01000000 | |
92 | #define PHB_MEM2_ENABLE 0x00400000 | |
93 | #define PHB_MCSR_ENABLE 0x00100000 | |
94 | /* TAR (Table Address Register) */ | |
95 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
96 | #define TAR_VALID 0x0000000000000008UL | |
97 | /* CSR (Channel/DMA Status Register) */ | |
98 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 99 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 100 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 101 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
102 | #define PMR_SOFTSTOP 0x80000000 |
103 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
104 | #define PMR_HARDSTOP 0x20000000 | |
e465058d JM |
105 | |
106 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 107 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
108 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
109 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
110 | #define PHBS_PER_CALGARY 4 |
111 | ||
112 | /* register offsets in Calgary's internal register space */ | |
113 | static const unsigned long tar_offsets[] = { | |
114 | 0x0580 /* TAR0 */, | |
115 | 0x0588 /* TAR1 */, | |
116 | 0x0590 /* TAR2 */, | |
117 | 0x0598 /* TAR3 */ | |
118 | }; | |
119 | ||
120 | static const unsigned long split_queue_offsets[] = { | |
121 | 0x4870 /* SPLIT QUEUE 0 */, | |
122 | 0x5870 /* SPLIT QUEUE 1 */, | |
123 | 0x6870 /* SPLIT QUEUE 2 */, | |
124 | 0x7870 /* SPLIT QUEUE 3 */ | |
125 | }; | |
126 | ||
127 | static const unsigned long phb_offsets[] = { | |
128 | 0x8000 /* PHB0 */, | |
129 | 0x9000 /* PHB1 */, | |
130 | 0xA000 /* PHB2 */, | |
131 | 0xB000 /* PHB3 */ | |
132 | }; | |
133 | ||
b34e90b8 LV |
134 | /* PHB debug registers */ |
135 | ||
136 | static const unsigned long phb_debug_offsets[] = { | |
137 | 0x4000 /* PHB 0 DEBUG */, | |
138 | 0x5000 /* PHB 1 DEBUG */, | |
139 | 0x6000 /* PHB 2 DEBUG */, | |
140 | 0x7000 /* PHB 3 DEBUG */ | |
141 | }; | |
142 | ||
143 | /* | |
144 | * STUFF register for each debug PHB, | |
145 | * byte 1 = start bus number, byte 2 = end bus number | |
146 | */ | |
147 | ||
148 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
149 | ||
310adfdd MBY |
150 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
151 | ||
e465058d JM |
152 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
153 | static int translate_empty_slots __read_mostly = 0; | |
154 | static int calgary_detected __read_mostly = 0; | |
155 | ||
b34e90b8 LV |
156 | static struct rio_table_hdr *rio_table_hdr __initdata; |
157 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 158 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 159 | |
f38db651 MBY |
160 | struct calgary_bus_info { |
161 | void *tce_space; | |
0577f148 | 162 | unsigned char translation_disabled; |
f38db651 | 163 | signed char phbid; |
b34e90b8 | 164 | void __iomem *bbar; |
f38db651 MBY |
165 | }; |
166 | ||
ff297b8c MBY |
167 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
168 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 169 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 170 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 171 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 172 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
95b68dec C |
173 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl); |
174 | static void get_tce_space_from_tar(void); | |
ff297b8c MBY |
175 | |
176 | static struct cal_chipset_ops calgary_chip_ops = { | |
177 | .handle_quirks = calgary_handle_quirks, | |
8cb32dc7 MBY |
178 | .tce_cache_blast = calgary_tce_cache_blast, |
179 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 180 | }; |
e465058d | 181 | |
c3860108 MBY |
182 | static struct cal_chipset_ops calioc2_chip_ops = { |
183 | .handle_quirks = calioc2_handle_quirks, | |
8cb32dc7 MBY |
184 | .tce_cache_blast = calioc2_tce_cache_blast, |
185 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
186 | }; |
187 | ||
ff297b8c | 188 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d | 189 | |
d588ba8c MBY |
190 | static inline int translation_enabled(struct iommu_table *tbl) |
191 | { | |
192 | /* only PHBs with translation enabled have an IOMMU table */ | |
193 | return (tbl != NULL); | |
194 | } | |
195 | ||
e465058d | 196 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 197 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
198 | { |
199 | unsigned long index; | |
200 | unsigned long end; | |
820a1497 | 201 | unsigned long flags; |
e465058d JM |
202 | |
203 | index = start_addr >> PAGE_SHIFT; | |
204 | ||
205 | /* bail out if we're asked to reserve a region we don't cover */ | |
206 | if (index >= tbl->it_size) | |
207 | return; | |
208 | ||
209 | end = index + npages; | |
210 | if (end > tbl->it_size) /* don't go off the table */ | |
211 | end = tbl->it_size; | |
212 | ||
820a1497 MBY |
213 | spin_lock_irqsave(&tbl->it_lock, flags); |
214 | ||
a66022c4 | 215 | bitmap_set(tbl->it_map, index, npages); |
820a1497 MBY |
216 | |
217 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
218 | } |
219 | ||
1b39b077 FT |
220 | static unsigned long iommu_range_alloc(struct device *dev, |
221 | struct iommu_table *tbl, | |
222 | unsigned int npages) | |
e465058d | 223 | { |
820a1497 | 224 | unsigned long flags; |
e465058d | 225 | unsigned long offset; |
1b39b077 FT |
226 | unsigned long boundary_size; |
227 | ||
228 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
229 | PAGE_SIZE) >> PAGE_SHIFT; | |
e465058d JM |
230 | |
231 | BUG_ON(npages == 0); | |
232 | ||
820a1497 MBY |
233 | spin_lock_irqsave(&tbl->it_lock, flags); |
234 | ||
1b39b077 FT |
235 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint, |
236 | npages, 0, boundary_size, 0); | |
e465058d | 237 | if (offset == ~0UL) { |
ff297b8c | 238 | tbl->chip_ops->tce_cache_blast(tbl); |
1b39b077 FT |
239 | |
240 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | |
241 | npages, 0, boundary_size, 0); | |
e465058d JM |
242 | if (offset == ~0UL) { |
243 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
820a1497 | 244 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
245 | if (panic_on_overflow) |
246 | panic("Calgary: fix the allocator.\n"); | |
247 | else | |
8fd524b3 | 248 | return DMA_ERROR_CODE; |
e465058d JM |
249 | } |
250 | } | |
251 | ||
e465058d JM |
252 | tbl->it_hint = offset + npages; |
253 | BUG_ON(tbl->it_hint > tbl->it_size); | |
254 | ||
820a1497 MBY |
255 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
256 | ||
e465058d JM |
257 | return offset; |
258 | } | |
259 | ||
1b39b077 FT |
260 | static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, |
261 | void *vaddr, unsigned int npages, int direction) | |
e465058d | 262 | { |
820a1497 | 263 | unsigned long entry; |
1f7564ca | 264 | dma_addr_t ret; |
e465058d | 265 | |
1b39b077 | 266 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d | 267 | |
1f7564ca FT |
268 | if (unlikely(entry == DMA_ERROR_CODE)) { |
269 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " | |
270 | "iommu %p\n", npages, tbl); | |
271 | return DMA_ERROR_CODE; | |
272 | } | |
e465058d JM |
273 | |
274 | /* set the return dma address */ | |
275 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
276 | ||
277 | /* put the TCEs in the HW table */ | |
278 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
279 | direction); | |
e465058d | 280 | return ret; |
e465058d JM |
281 | } |
282 | ||
3cc39bda | 283 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
284 | unsigned int npages) |
285 | { | |
286 | unsigned long entry; | |
310adfdd | 287 | unsigned long badend; |
820a1497 | 288 | unsigned long flags; |
310adfdd MBY |
289 | |
290 | /* were we called with bad_dma_address? */ | |
8fd524b3 FT |
291 | badend = DMA_ERROR_CODE + (EMERGENCY_PAGES * PAGE_SIZE); |
292 | if (unlikely((dma_addr >= DMA_ERROR_CODE) && (dma_addr < badend))) { | |
bde78a79 | 293 | WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA " |
310adfdd | 294 | "address 0x%Lx\n", dma_addr); |
310adfdd MBY |
295 | return; |
296 | } | |
e465058d JM |
297 | |
298 | entry = dma_addr >> PAGE_SHIFT; | |
299 | ||
300 | BUG_ON(entry + npages > tbl->it_size); | |
301 | ||
302 | tce_free(tbl, entry, npages); | |
303 | ||
820a1497 MBY |
304 | spin_lock_irqsave(&tbl->it_lock, flags); |
305 | ||
a66022c4 | 306 | bitmap_clear(tbl->it_map, entry, npages); |
820a1497 MBY |
307 | |
308 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
309 | } |
310 | ||
35b6dfa0 MBY |
311 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
312 | { | |
8a244590 MBY |
313 | struct pci_dev *pdev; |
314 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
315 | struct iommu_table *tbl; |
316 | ||
8a244590 MBY |
317 | pdev = to_pci_dev(dev); |
318 | ||
4528752f | 319 | /* search up the device tree for an iommu */ |
f055a061 | 320 | pbus = pdev->bus; |
4528752f DW |
321 | do { |
322 | tbl = pci_iommu(pbus); | |
323 | if (tbl && tbl->it_busno == pbus->number) | |
324 | break; | |
325 | tbl = NULL; | |
f055a061 | 326 | pbus = pbus->parent; |
4528752f | 327 | } while (pbus); |
7354b075 | 328 | |
f055a061 | 329 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
330 | |
331 | return tbl; | |
332 | } | |
333 | ||
160c1d8e FT |
334 | static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, |
335 | int nelems,enum dma_data_direction dir, | |
336 | struct dma_attrs *attrs) | |
e465058d | 337 | { |
3cc39bda | 338 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
339 | struct scatterlist *s; |
340 | int i; | |
3cc39bda | 341 | |
bc3c6058 | 342 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
343 | return; |
344 | ||
8b87d9f4 | 345 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 346 | unsigned int npages; |
8b87d9f4 JA |
347 | dma_addr_t dma = s->dma_address; |
348 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
349 | |
350 | if (dmalen == 0) | |
351 | break; | |
352 | ||
036b4c50 | 353 | npages = iommu_num_pages(dma, dmalen, PAGE_SIZE); |
3cc39bda | 354 | iommu_free(tbl, dma, npages); |
e465058d JM |
355 | } |
356 | } | |
357 | ||
0b11e1c6 | 358 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
160c1d8e FT |
359 | int nelems, enum dma_data_direction dir, |
360 | struct dma_attrs *attrs) | |
e465058d | 361 | { |
35b6dfa0 | 362 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 363 | struct scatterlist *s; |
e465058d JM |
364 | unsigned long vaddr; |
365 | unsigned int npages; | |
366 | unsigned long entry; | |
367 | int i; | |
368 | ||
8b87d9f4 | 369 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 370 | BUG_ON(!sg_page(s)); |
e465058d | 371 | |
58b053e4 | 372 | vaddr = (unsigned long) sg_virt(s); |
036b4c50 | 373 | npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE); |
e465058d | 374 | |
1b39b077 | 375 | entry = iommu_range_alloc(dev, tbl, npages); |
8fd524b3 | 376 | if (entry == DMA_ERROR_CODE) { |
e465058d JM |
377 | /* makes sure unmap knows to stop */ |
378 | s->dma_length = 0; | |
379 | goto error; | |
380 | } | |
381 | ||
382 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
383 | ||
384 | /* insert into HW table */ | |
160c1d8e | 385 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir); |
e465058d JM |
386 | |
387 | s->dma_length = s->length; | |
388 | } | |
389 | ||
e465058d JM |
390 | return nelems; |
391 | error: | |
160c1d8e | 392 | calgary_unmap_sg(dev, sg, nelems, dir, NULL); |
8b87d9f4 | 393 | for_each_sg(sg, s, nelems, i) { |
8fd524b3 | 394 | sg->dma_address = DMA_ERROR_CODE; |
8b87d9f4 | 395 | sg->dma_length = 0; |
e465058d | 396 | } |
e465058d JM |
397 | return 0; |
398 | } | |
399 | ||
3991605c FT |
400 | static dma_addr_t calgary_map_page(struct device *dev, struct page *page, |
401 | unsigned long offset, size_t size, | |
402 | enum dma_data_direction dir, | |
403 | struct dma_attrs *attrs) | |
e465058d | 404 | { |
3991605c | 405 | void *vaddr = page_address(page) + offset; |
e465058d JM |
406 | unsigned long uaddr; |
407 | unsigned int npages; | |
35b6dfa0 | 408 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
409 | |
410 | uaddr = (unsigned long)vaddr; | |
036b4c50 | 411 | npages = iommu_num_pages(uaddr, size, PAGE_SIZE); |
e465058d | 412 | |
3991605c | 413 | return iommu_alloc(dev, tbl, vaddr, npages, dir); |
e465058d JM |
414 | } |
415 | ||
3991605c FT |
416 | static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr, |
417 | size_t size, enum dma_data_direction dir, | |
418 | struct dma_attrs *attrs) | |
e465058d | 419 | { |
35b6dfa0 | 420 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
421 | unsigned int npages; |
422 | ||
3991605c FT |
423 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
424 | iommu_free(tbl, dma_addr, npages); | |
425 | } | |
426 | ||
0b11e1c6 | 427 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
e465058d JM |
428 | dma_addr_t *dma_handle, gfp_t flag) |
429 | { | |
430 | void *ret = NULL; | |
431 | dma_addr_t mapping; | |
432 | unsigned int npages, order; | |
35b6dfa0 | 433 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
434 | |
435 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
436 | npages = size >> PAGE_SHIFT; | |
437 | order = get_order(size); | |
438 | ||
f10ac8a2 FT |
439 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
440 | ||
e465058d JM |
441 | /* alloc enough pages (and possibly more) */ |
442 | ret = (void *)__get_free_pages(flag, order); | |
443 | if (!ret) | |
444 | goto error; | |
445 | memset(ret, 0, size); | |
446 | ||
1956a96d AB |
447 | /* set up tces to cover the allocated range */ |
448 | mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL); | |
8fd524b3 | 449 | if (mapping == DMA_ERROR_CODE) |
1956a96d AB |
450 | goto free; |
451 | *dma_handle = mapping; | |
e465058d | 452 | return ret; |
e465058d JM |
453 | free: |
454 | free_pages((unsigned long)ret, get_order(size)); | |
455 | ret = NULL; | |
456 | error: | |
457 | return ret; | |
458 | } | |
459 | ||
e4ad68b6 JR |
460 | static void calgary_free_coherent(struct device *dev, size_t size, |
461 | void *vaddr, dma_addr_t dma_handle) | |
462 | { | |
463 | unsigned int npages; | |
464 | struct iommu_table *tbl = find_iommu_table(dev); | |
465 | ||
466 | size = PAGE_ALIGN(size); | |
467 | npages = size >> PAGE_SHIFT; | |
468 | ||
469 | iommu_free(tbl, dma_handle, npages); | |
470 | free_pages((unsigned long)vaddr, get_order(size)); | |
471 | } | |
472 | ||
160c1d8e | 473 | static struct dma_map_ops calgary_dma_ops = { |
e465058d | 474 | .alloc_coherent = calgary_alloc_coherent, |
e4ad68b6 | 475 | .free_coherent = calgary_free_coherent, |
e465058d JM |
476 | .map_sg = calgary_map_sg, |
477 | .unmap_sg = calgary_unmap_sg, | |
3991605c FT |
478 | .map_page = calgary_map_page, |
479 | .unmap_page = calgary_unmap_page, | |
e465058d JM |
480 | }; |
481 | ||
b34e90b8 LV |
482 | static inline void __iomem * busno_to_bbar(unsigned char num) |
483 | { | |
484 | return bus_info[num].bbar; | |
485 | } | |
486 | ||
e465058d JM |
487 | static inline int busno_to_phbid(unsigned char num) |
488 | { | |
f38db651 | 489 | return bus_info[num].phbid; |
e465058d JM |
490 | } |
491 | ||
492 | static inline unsigned long split_queue_offset(unsigned char num) | |
493 | { | |
494 | size_t idx = busno_to_phbid(num); | |
495 | ||
496 | return split_queue_offsets[idx]; | |
497 | } | |
498 | ||
499 | static inline unsigned long tar_offset(unsigned char num) | |
500 | { | |
501 | size_t idx = busno_to_phbid(num); | |
502 | ||
503 | return tar_offsets[idx]; | |
504 | } | |
505 | ||
506 | static inline unsigned long phb_offset(unsigned char num) | |
507 | { | |
508 | size_t idx = busno_to_phbid(num); | |
509 | ||
510 | return phb_offsets[idx]; | |
511 | } | |
512 | ||
513 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
514 | { | |
515 | unsigned long target = ((unsigned long)bar) | offset; | |
516 | return (void __iomem*)target; | |
517 | } | |
518 | ||
8a244590 MBY |
519 | static inline int is_calioc2(unsigned short device) |
520 | { | |
521 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
522 | } | |
523 | ||
524 | static inline int is_calgary(unsigned short device) | |
525 | { | |
526 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
527 | } | |
528 | ||
529 | static inline int is_cal_pci_dev(unsigned short device) | |
530 | { | |
531 | return (is_calgary(device) || is_calioc2(device)); | |
532 | } | |
533 | ||
ff297b8c | 534 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
535 | { |
536 | u64 val; | |
537 | u32 aer; | |
538 | int i = 0; | |
539 | void __iomem *bbar = tbl->bbar; | |
540 | void __iomem *target; | |
541 | ||
542 | /* disable arbitration on the bus */ | |
543 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
544 | aer = readl(target); | |
545 | writel(0, target); | |
546 | ||
547 | /* read plssr to ensure it got there */ | |
548 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
549 | val = readl(target); | |
550 | ||
551 | /* poll split queues until all DMA activity is done */ | |
552 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
553 | do { | |
554 | val = readq(target); | |
555 | i++; | |
556 | } while ((val & 0xff) != 0xff && i < 100); | |
557 | if (i == 100) | |
558 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
559 | "continuing anyway\n"); | |
560 | ||
561 | /* invalidate TCE cache */ | |
562 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
563 | writeq(tbl->tar_val, target); | |
564 | ||
565 | /* enable arbitration */ | |
566 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
567 | writel(aer, target); | |
568 | (void)readl(target); /* flush */ | |
569 | } | |
570 | ||
00be3fa4 MBY |
571 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
572 | { | |
573 | void __iomem *bbar = tbl->bbar; | |
574 | void __iomem *target; | |
575 | u64 val64; | |
576 | u32 val; | |
577 | int i = 0; | |
578 | int count = 1; | |
579 | unsigned char bus = tbl->it_busno; | |
580 | ||
581 | begin: | |
582 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
583 | "sequence - count %d\n", bus, count); | |
584 | ||
585 | /* 1. using the Page Migration Control reg set SoftStop */ | |
586 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
587 | val = be32_to_cpu(readl(target)); | |
588 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
589 | val |= PMR_SOFTSTOP; | |
590 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
591 | writel(cpu_to_be32(val), target); | |
592 | ||
593 | /* 2. poll split queues until all DMA activity is done */ | |
594 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
595 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
596 | do { | |
597 | val64 = readq(target); | |
598 | i++; | |
599 | } while ((val64 & 0xff) != 0xff && i < 100); | |
600 | if (i == 100) | |
601 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | |
602 | "continuing anyway\n"); | |
603 | ||
604 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
605 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
606 | val = be32_to_cpu(readl(target)); | |
607 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
608 | ||
609 | /* 4. if SoftStopFault - goto (1) */ | |
610 | if (val & PMR_SOFTSTOPFAULT) { | |
611 | if (++count < 100) | |
612 | goto begin; | |
613 | else { | |
614 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | |
615 | "aborting TCE cache flush sequence!\n"); | |
616 | return; /* pray for the best */ | |
617 | } | |
618 | } | |
619 | ||
620 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
621 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
622 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
623 | val = be32_to_cpu(readl(target)); | |
624 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
625 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
626 | val = be32_to_cpu(readl(target)); | |
627 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
628 | ||
629 | /* 6. invalidate TCE cache */ | |
630 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
631 | target = calgary_reg(bbar, tar_offset(bus)); | |
632 | writeq(tbl->tar_val, target); | |
633 | ||
634 | /* 7. Re-read PMCR */ | |
635 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
636 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
637 | val = be32_to_cpu(readl(target)); | |
638 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
639 | ||
640 | /* 8. Remove HardStop */ | |
641 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
642 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
643 | val = 0; | |
644 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
645 | writel(cpu_to_be32(val), target); | |
646 | val = be32_to_cpu(readl(target)); | |
647 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
648 | } | |
649 | ||
e465058d JM |
650 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
651 | u64 limit) | |
652 | { | |
653 | unsigned int numpages; | |
654 | ||
655 | limit = limit | 0xfffff; | |
656 | limit++; | |
657 | ||
658 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 659 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
660 | } |
661 | ||
662 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
663 | { | |
664 | void __iomem *target; | |
665 | u64 low, high, sizelow; | |
666 | u64 start, limit; | |
08f1c192 | 667 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
668 | unsigned char busnum = dev->bus->number; |
669 | void __iomem *bbar = tbl->bbar; | |
670 | ||
671 | /* peripheral MEM_1 region */ | |
672 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
673 | low = be32_to_cpu(readl(target)); | |
674 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
675 | high = be32_to_cpu(readl(target)); | |
676 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
677 | sizelow = be32_to_cpu(readl(target)); | |
678 | ||
679 | start = (high << 32) | low; | |
680 | limit = sizelow; | |
681 | ||
682 | calgary_reserve_mem_region(dev, start, limit); | |
683 | } | |
684 | ||
685 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
686 | { | |
687 | void __iomem *target; | |
688 | u32 val32; | |
689 | u64 low, high, sizelow, sizehigh; | |
690 | u64 start, limit; | |
08f1c192 | 691 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
692 | unsigned char busnum = dev->bus->number; |
693 | void __iomem *bbar = tbl->bbar; | |
694 | ||
695 | /* is it enabled? */ | |
696 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
697 | val32 = be32_to_cpu(readl(target)); | |
698 | if (!(val32 & PHB_MEM2_ENABLE)) | |
699 | return; | |
700 | ||
701 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
702 | low = be32_to_cpu(readl(target)); | |
703 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
704 | high = be32_to_cpu(readl(target)); | |
705 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
706 | sizelow = be32_to_cpu(readl(target)); | |
707 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
708 | sizehigh = be32_to_cpu(readl(target)); | |
709 | ||
710 | start = (high << 32) | low; | |
711 | limit = (sizehigh << 32) | sizelow; | |
712 | ||
713 | calgary_reserve_mem_region(dev, start, limit); | |
714 | } | |
715 | ||
716 | /* | |
717 | * some regions of the IO address space do not get translated, so we | |
718 | * must not give devices IO addresses in those regions. The regions | |
719 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
720 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
721 | * later. | |
722 | */ | |
723 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
724 | { | |
725 | unsigned int npages; | |
e465058d | 726 | u64 start; |
08f1c192 | 727 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 728 | |
310adfdd | 729 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
8fd524b3 | 730 | iommu_range_reserve(tbl, DMA_ERROR_CODE, EMERGENCY_PAGES); |
e465058d JM |
731 | |
732 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 733 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
734 | if (is_calgary(dev->device)) { |
735 | start = (640 * 1024); | |
736 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
737 | } else { /* calioc2 */ | |
738 | start = 0; | |
e8f20414 | 739 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 740 | } |
e465058d JM |
741 | iommu_range_reserve(tbl, start, npages); |
742 | ||
743 | /* reserve the two PCI peripheral memory regions in IO space */ | |
744 | calgary_reserve_peripheral_mem_1(dev); | |
745 | calgary_reserve_peripheral_mem_2(dev); | |
746 | } | |
747 | ||
748 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
749 | { | |
750 | u64 val64; | |
751 | u64 table_phys; | |
752 | void __iomem *target; | |
753 | int ret; | |
754 | struct iommu_table *tbl; | |
755 | ||
756 | /* build TCE tables for each PHB */ | |
757 | ret = build_tce_table(dev, bbar); | |
758 | if (ret) | |
759 | return ret; | |
760 | ||
08f1c192 | 761 | tbl = pci_iommu(dev->bus); |
f38db651 | 762 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
95b68dec C |
763 | |
764 | if (is_kdump_kernel()) | |
765 | calgary_init_bitmap_from_tce_table(tbl); | |
766 | else | |
767 | tce_free(tbl, 0, tbl->it_size); | |
f38db651 | 768 | |
8bcf7705 MBY |
769 | if (is_calgary(dev->device)) |
770 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
771 | else if (is_calioc2(dev->device)) |
772 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
773 | else |
774 | BUG(); | |
ff297b8c | 775 | |
e465058d JM |
776 | calgary_reserve_regions(dev); |
777 | ||
778 | /* set TARs for each PHB */ | |
779 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
780 | val64 = be64_to_cpu(readq(target)); | |
781 | ||
782 | /* zero out all TAR bits under sw control */ | |
783 | val64 &= ~TAR_SW_BITS; | |
e465058d | 784 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 785 | |
e465058d JM |
786 | val64 |= table_phys; |
787 | ||
788 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
789 | val64 |= (u64) specified_table_size; | |
790 | ||
791 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 792 | |
e465058d JM |
793 | writeq(tbl->tar_val, target); |
794 | readq(target); /* flush */ | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
b8f4fe66 | 799 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
800 | { |
801 | u64 val64; | |
08f1c192 | 802 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 803 | void __iomem *target; |
b8f4fe66 | 804 | unsigned int bitmapsz; |
e465058d JM |
805 | |
806 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
807 | val64 = be64_to_cpu(readq(target)); | |
808 | val64 &= ~TAR_SW_BITS; | |
809 | writeq(cpu_to_be64(val64), target); | |
810 | readq(target); /* flush */ | |
811 | ||
b8f4fe66 MBY |
812 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
813 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
814 | tbl->it_map = NULL; | |
815 | ||
e465058d | 816 | kfree(tbl); |
08f1c192 MBY |
817 | |
818 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
819 | |
820 | /* Can't free bootmem allocated memory after system is up :-( */ | |
821 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
822 | } |
823 | ||
8a244590 MBY |
824 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
825 | { | |
826 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 827 | void __iomem *target; |
ddbd41b4 | 828 | u32 csr, plssr; |
8cb32dc7 MBY |
829 | |
830 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
831 | csr = be32_to_cpu(readl(target)); |
832 | ||
833 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
834 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
835 | |
836 | /* If no error, the agent ID in the CSR is not valid */ | |
837 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | |
ddbd41b4 | 838 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); |
8cb32dc7 MBY |
839 | } |
840 | ||
841 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
842 | { | |
843 | void __iomem *bbar = tbl->bbar; | |
844 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
845 | void __iomem *target; |
846 | unsigned long phboff = phb_offset(tbl->it_busno); | |
847 | unsigned long erroff; | |
848 | u32 errregs[7]; | |
849 | int i; | |
850 | ||
851 | /* dump CSR */ | |
852 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
853 | csr = be32_to_cpu(readl(target)); | |
854 | /* dump PLSSR */ | |
855 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
856 | plssr = be32_to_cpu(readl(target)); | |
857 | /* dump CSMR */ | |
858 | target = calgary_reg(bbar, phboff | 0x290); | |
859 | csmr = be32_to_cpu(readl(target)); | |
860 | /* dump mck */ | |
861 | target = calgary_reg(bbar, phboff | 0x800); | |
862 | mck = be32_to_cpu(readl(target)); | |
863 | ||
8cb32dc7 MBY |
864 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", |
865 | tbl->it_busno); | |
866 | ||
867 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | |
868 | csr, plssr, csmr, mck); | |
8a244590 MBY |
869 | |
870 | /* dump rest of error regs */ | |
871 | printk(KERN_EMERG "Calgary: "); | |
872 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
7354b075 MBY |
873 | /* err regs are at 0x810 - 0x870 */ |
874 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
875 | target = calgary_reg(bbar, phboff | erroff); |
876 | errregs[i] = be32_to_cpu(readl(target)); | |
877 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
878 | } | |
879 | printk("\n"); | |
8cb32dc7 MBY |
880 | |
881 | /* root complex status */ | |
882 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
883 | rcstat = be32_to_cpu(readl(target)); | |
884 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
885 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
886 | } |
887 | ||
e465058d JM |
888 | static void calgary_watchdog(unsigned long data) |
889 | { | |
890 | struct pci_dev *dev = (struct pci_dev *)data; | |
08f1c192 | 891 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
892 | void __iomem *bbar = tbl->bbar; |
893 | u32 val32; | |
894 | void __iomem *target; | |
895 | ||
896 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
897 | val32 = be32_to_cpu(readl(target)); | |
898 | ||
899 | /* If no error, the agent ID in the CSR is not valid */ | |
900 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 901 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
902 | |
903 | /* reset error */ | |
e465058d JM |
904 | writel(0, target); |
905 | ||
906 | /* Disable bus that caused the error */ | |
907 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 908 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
909 | val32 = be32_to_cpu(readl(target)); |
910 | val32 |= PHB_SLOT_DISABLE; | |
911 | writel(cpu_to_be32(val32), target); | |
912 | readl(target); /* flush */ | |
913 | } else { | |
914 | /* Reset the timer */ | |
915 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
916 | } | |
917 | } | |
918 | ||
a2b663f6 MBY |
919 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
920 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
921 | { |
922 | u64 val64; | |
923 | void __iomem *target; | |
58db8548 | 924 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
925 | u64 mask; |
926 | ||
927 | switch (busno_to_phbid(busnum)) { | |
928 | case 0: phb_shift = (63 - 19); | |
929 | break; | |
930 | case 1: phb_shift = (63 - 23); | |
931 | break; | |
932 | case 2: phb_shift = (63 - 27); | |
933 | break; | |
934 | case 3: phb_shift = (63 - 35); | |
935 | break; | |
936 | default: | |
937 | BUG_ON(busno_to_phbid(busnum)); | |
938 | } | |
939 | ||
940 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
941 | val64 = be64_to_cpu(readq(target)); | |
942 | ||
943 | /* zero out this PHB's timer bits */ | |
944 | mask = ~(0xFUL << phb_shift); | |
945 | val64 &= mask; | |
a2b663f6 | 946 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
947 | writeq(cpu_to_be64(val64), target); |
948 | readq(target); /* flush */ | |
949 | } | |
950 | ||
31f3dff6 | 951 | static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
c3860108 MBY |
952 | { |
953 | unsigned char busnum = dev->bus->number; | |
954 | void __iomem *bbar = tbl->bbar; | |
955 | void __iomem *target; | |
956 | u32 val; | |
957 | ||
8bcf7705 MBY |
958 | /* |
959 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
960 | */ | |
961 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
962 | val = cpu_to_be32(readl(target)); | |
963 | val |= 0x00800000; | |
964 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
965 | } |
966 | ||
31f3dff6 | 967 | static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
b8d2ea1b MBY |
968 | { |
969 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
970 | |
971 | /* | |
972 | * Give split completion a longer timeout on bus 1 for aic94xx | |
973 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
974 | */ | |
c3860108 | 975 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
976 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
977 | CCR_2SEC_TIMEOUT); | |
978 | } | |
979 | ||
e465058d JM |
980 | static void __init calgary_enable_translation(struct pci_dev *dev) |
981 | { | |
982 | u32 val32; | |
983 | unsigned char busnum; | |
984 | void __iomem *target; | |
985 | void __iomem *bbar; | |
986 | struct iommu_table *tbl; | |
987 | ||
988 | busnum = dev->bus->number; | |
08f1c192 | 989 | tbl = pci_iommu(dev->bus); |
e465058d JM |
990 | bbar = tbl->bbar; |
991 | ||
992 | /* enable TCE in PHB Config Register */ | |
993 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
994 | val32 = be32_to_cpu(readl(target)); | |
995 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
996 | ||
8a244590 MBY |
997 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
998 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
999 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1000 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1001 | "bus.\n"); | |
1002 | ||
1003 | writel(cpu_to_be32(val32), target); | |
1004 | readl(target); /* flush */ | |
1005 | ||
1006 | init_timer(&tbl->watchdog_timer); | |
1007 | tbl->watchdog_timer.function = &calgary_watchdog; | |
1008 | tbl->watchdog_timer.data = (unsigned long)dev; | |
1009 | mod_timer(&tbl->watchdog_timer, jiffies); | |
1010 | } | |
1011 | ||
1012 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1013 | { | |
1014 | u32 val32; | |
1015 | unsigned char busnum; | |
1016 | void __iomem *target; | |
1017 | void __iomem *bbar; | |
1018 | struct iommu_table *tbl; | |
1019 | ||
1020 | busnum = dev->bus->number; | |
08f1c192 | 1021 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1022 | bbar = tbl->bbar; |
1023 | ||
1024 | /* disable TCE in PHB Config Register */ | |
1025 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1026 | val32 = be32_to_cpu(readl(target)); | |
1027 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1028 | ||
70d666d6 | 1029 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1030 | writel(cpu_to_be32(val32), target); |
1031 | readl(target); /* flush */ | |
1032 | ||
1033 | del_timer_sync(&tbl->watchdog_timer); | |
1034 | } | |
1035 | ||
a4fc520a | 1036 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1037 | { |
871b1700 | 1038 | pci_dev_get(dev); |
08f1c192 | 1039 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1040 | |
1041 | /* is the device behind a bridge? */ | |
1042 | if (dev->bus->parent) | |
1043 | dev->bus->parent->self = dev; | |
1044 | else | |
1045 | dev->bus->self = dev; | |
e465058d JM |
1046 | } |
1047 | ||
1048 | static int __init calgary_init_one(struct pci_dev *dev) | |
1049 | { | |
e465058d | 1050 | void __iomem *bbar; |
ff297b8c | 1051 | struct iommu_table *tbl; |
e465058d JM |
1052 | int ret; |
1053 | ||
dedc9937 JM |
1054 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1055 | ||
eae93755 | 1056 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1057 | ret = calgary_setup_tar(dev, bbar); |
1058 | if (ret) | |
eae93755 | 1059 | goto done; |
e465058d | 1060 | |
871b1700 | 1061 | pci_dev_get(dev); |
8a244590 MBY |
1062 | |
1063 | if (dev->bus->parent) { | |
1064 | if (dev->bus->parent->self) | |
1065 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1066 | "bus->parent->self!\n", dev); | |
1067 | dev->bus->parent->self = dev; | |
1068 | } else | |
1069 | dev->bus->self = dev; | |
b8d2ea1b | 1070 | |
08f1c192 | 1071 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1072 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1073 | |
e465058d JM |
1074 | calgary_enable_translation(dev); |
1075 | ||
1076 | return 0; | |
1077 | ||
e465058d JM |
1078 | done: |
1079 | return ret; | |
1080 | } | |
1081 | ||
eae93755 | 1082 | static int __init calgary_locate_bbars(void) |
e465058d | 1083 | { |
eae93755 MBY |
1084 | int ret; |
1085 | int rioidx, phb, bus; | |
b34e90b8 LV |
1086 | void __iomem *bbar; |
1087 | void __iomem *target; | |
eae93755 | 1088 | unsigned long offset; |
b34e90b8 LV |
1089 | u8 start_bus, end_bus; |
1090 | u32 val; | |
1091 | ||
eae93755 MBY |
1092 | ret = -ENODATA; |
1093 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1094 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1095 | |
eae93755 | 1096 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1097 | continue; |
1098 | ||
1099 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1100 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1101 | if (!bbar) | |
1102 | goto error; | |
b34e90b8 LV |
1103 | |
1104 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1105 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1106 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1107 | |
b34e90b8 | 1108 | val = be32_to_cpu(readl(target)); |
8a244590 | 1109 | |
b34e90b8 | 1110 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1111 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1112 | |
1113 | if (end_bus) { | |
1114 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1115 | bus_info[bus].bbar = bbar; | |
1116 | bus_info[bus].phbid = phb; | |
1117 | } | |
1118 | } else { | |
1119 | bus_info[start_bus].bbar = bbar; | |
1120 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1121 | } |
1122 | } | |
1123 | } | |
1124 | ||
eae93755 MBY |
1125 | return 0; |
1126 | ||
1127 | error: | |
1128 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1129 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1130 | if (bus_info[bus].bbar) | |
1131 | iounmap(bus_info[bus].bbar); | |
1132 | ||
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | static int __init calgary_init(void) | |
1137 | { | |
1138 | int ret; | |
1139 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1140 | struct calgary_bus_info *info; |
eae93755 MBY |
1141 | |
1142 | ret = calgary_locate_bbars(); | |
1143 | if (ret) | |
1144 | return ret; | |
e465058d | 1145 | |
95b68dec C |
1146 | /* Purely for kdump kernel case */ |
1147 | if (is_kdump_kernel()) | |
1148 | get_tce_space_from_tar(); | |
1149 | ||
dedc9937 | 1150 | do { |
8a244590 | 1151 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1152 | if (!dev) |
1153 | break; | |
8a244590 MBY |
1154 | if (!is_cal_pci_dev(dev->device)) |
1155 | continue; | |
bc3c6058 MBY |
1156 | |
1157 | info = &bus_info[dev->bus->number]; | |
1158 | if (info->translation_disabled) { | |
e465058d JM |
1159 | calgary_init_one_nontraslated(dev); |
1160 | continue; | |
1161 | } | |
bc3c6058 MBY |
1162 | |
1163 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1164 | continue; |
12de257b | 1165 | |
e465058d JM |
1166 | ret = calgary_init_one(dev); |
1167 | if (ret) | |
1168 | goto error; | |
dedc9937 | 1169 | } while (1); |
e465058d | 1170 | |
1956a96d AB |
1171 | dev = NULL; |
1172 | for_each_pci_dev(dev) { | |
1173 | struct iommu_table *tbl; | |
1174 | ||
1175 | tbl = find_iommu_table(&dev->dev); | |
1176 | ||
1177 | if (translation_enabled(tbl)) | |
1178 | dev->dev.archdata.dma_ops = &calgary_dma_ops; | |
1179 | } | |
1180 | ||
e465058d JM |
1181 | return ret; |
1182 | ||
1183 | error: | |
dedc9937 | 1184 | do { |
a2b5d877 | 1185 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
9f2dc46d MBY |
1186 | if (!dev) |
1187 | break; | |
8a244590 MBY |
1188 | if (!is_cal_pci_dev(dev->device)) |
1189 | continue; | |
bc3c6058 MBY |
1190 | |
1191 | info = &bus_info[dev->bus->number]; | |
1192 | if (info->translation_disabled) { | |
e465058d JM |
1193 | pci_dev_put(dev); |
1194 | continue; | |
1195 | } | |
bc3c6058 | 1196 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1197 | continue; |
871b1700 | 1198 | |
e465058d | 1199 | calgary_disable_translation(dev); |
b8f4fe66 | 1200 | calgary_free_bus(dev); |
871b1700 | 1201 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
1956a96d | 1202 | dev->dev.archdata.dma_ops = NULL; |
dedc9937 | 1203 | } while (1); |
e465058d JM |
1204 | |
1205 | return ret; | |
1206 | } | |
1207 | ||
1208 | static inline int __init determine_tce_table_size(u64 ram) | |
1209 | { | |
1210 | int ret; | |
1211 | ||
1212 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1213 | return specified_table_size; | |
1214 | ||
1215 | /* | |
1216 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1217 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1218 | * larger table size has twice as many entries, so shift the | |
1219 | * max ram address by 13 to divide by 8K and then look at the | |
1220 | * order of the result to choose between 0-7. | |
1221 | */ | |
1222 | ret = get_order(ram >> 13); | |
1223 | if (ret > TCE_TABLE_SIZE_8M) | |
1224 | ret = TCE_TABLE_SIZE_8M; | |
1225 | ||
1226 | return ret; | |
1227 | } | |
1228 | ||
b34e90b8 LV |
1229 | static int __init build_detail_arrays(void) |
1230 | { | |
1231 | unsigned long ptr; | |
85d57797 DH |
1232 | unsigned numnodes, i; |
1233 | int scal_detail_size, rio_detail_size; | |
b34e90b8 | 1234 | |
85d57797 DH |
1235 | numnodes = rio_table_hdr->num_scal_dev; |
1236 | if (numnodes > MAX_NUMNODES){ | |
b34e90b8 | 1237 | printk(KERN_WARNING |
eae93755 | 1238 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 | 1239 | "but system has %d nodes.\n", |
85d57797 | 1240 | MAX_NUMNODES, numnodes); |
b34e90b8 LV |
1241 | return -ENODEV; |
1242 | } | |
1243 | ||
1244 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1245 | case 2: |
1246 | scal_detail_size = 11; | |
1247 | rio_detail_size = 13; | |
1248 | break; | |
1249 | case 3: | |
1250 | scal_detail_size = 12; | |
1251 | rio_detail_size = 15; | |
1252 | break; | |
eae93755 MBY |
1253 | default: |
1254 | printk(KERN_WARNING | |
1255 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1256 | rio_table_hdr->version); | |
1257 | return -EPROTO; | |
b34e90b8 LV |
1258 | } |
1259 | ||
1260 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
85d57797 | 1261 | for (i = 0; i < numnodes; i++, ptr += scal_detail_size) |
b34e90b8 LV |
1262 | scal_devs[i] = (struct scal_detail *)ptr; |
1263 | ||
1264 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1265 | i++, ptr += rio_detail_size) | |
1266 | rio_devs[i] = (struct rio_detail *)ptr; | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
8a244590 | 1271 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1272 | { |
8a244590 | 1273 | int dev; |
e465058d | 1274 | u32 val; |
8a244590 MBY |
1275 | |
1276 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1277 | /* | |
1278 | * FIXME: properly scan for devices accross the | |
1279 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1280 | */ | |
1281 | return 1; | |
1282 | } | |
1283 | ||
1284 | for (dev = 1; dev < 8; dev++) { | |
1285 | val = read_pci_config(bus, dev, 0, 0); | |
1286 | if (val != 0xffffffff) | |
1287 | break; | |
1288 | } | |
1289 | return (val != 0xffffffff); | |
1290 | } | |
1291 | ||
95b68dec C |
1292 | /* |
1293 | * calgary_init_bitmap_from_tce_table(): | |
1294 | * Funtion for kdump case. In the second/kdump kernel initialize | |
1295 | * the bitmap based on the tce table entries obtained from first kernel | |
1296 | */ | |
1297 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl) | |
1298 | { | |
1299 | u64 *tp; | |
1300 | unsigned int index; | |
1301 | tp = ((u64 *)tbl->it_base); | |
1302 | for (index = 0 ; index < tbl->it_size; index++) { | |
1303 | if (*tp != 0x0) | |
1304 | set_bit(index, tbl->it_map); | |
1305 | tp++; | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | /* | |
1310 | * get_tce_space_from_tar(): | |
1311 | * Function for kdump case. Get the tce tables from first kernel | |
3ad2f3fb | 1312 | * by reading the contents of the base address register of calgary iommu |
95b68dec | 1313 | */ |
f7106662 | 1314 | static void __init get_tce_space_from_tar(void) |
95b68dec C |
1315 | { |
1316 | int bus; | |
1317 | void __iomem *target; | |
1318 | unsigned long tce_space; | |
1319 | ||
1320 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { | |
1321 | struct calgary_bus_info *info = &bus_info[bus]; | |
1322 | unsigned short pci_device; | |
1323 | u32 val; | |
1324 | ||
1325 | val = read_pci_config(bus, 0, 0, 0); | |
1326 | pci_device = (val & 0xFFFF0000) >> 16; | |
1327 | ||
1328 | if (!is_cal_pci_dev(pci_device)) | |
1329 | continue; | |
1330 | if (info->translation_disabled) | |
1331 | continue; | |
1332 | ||
1333 | if (calgary_bus_has_devices(bus, pci_device) || | |
1334 | translate_empty_slots) { | |
1335 | target = calgary_reg(bus_info[bus].bbar, | |
1336 | tar_offset(bus)); | |
1337 | tce_space = be64_to_cpu(readq(target)); | |
1338 | tce_space = tce_space & TAR_SW_BITS; | |
1339 | ||
1340 | tce_space = tce_space & (~specified_table_size); | |
1341 | info->tce_space = (u64 *)__va(tce_space); | |
1342 | } | |
1343 | } | |
1344 | return; | |
1345 | } | |
1346 | ||
f4131c62 FT |
1347 | static int __init calgary_iommu_init(void) |
1348 | { | |
1349 | int ret; | |
1350 | ||
1351 | /* ok, we're trying to use Calgary - let's roll */ | |
1352 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1353 | ||
1354 | ret = calgary_init(); | |
1355 | if (ret) { | |
1356 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1357 | "falling back to no_iommu\n", ret); | |
1358 | return ret; | |
1359 | } | |
1360 | ||
f4131c62 FT |
1361 | return 0; |
1362 | } | |
d7b9f7be | 1363 | |
8a244590 MBY |
1364 | void __init detect_calgary(void) |
1365 | { | |
d2105b10 | 1366 | int bus; |
e465058d | 1367 | void *tbl; |
d2105b10 | 1368 | int calgary_found = 0; |
b34e90b8 | 1369 | unsigned long ptr; |
136f1e7a | 1370 | unsigned int offset, prev_offset; |
eae93755 | 1371 | int ret; |
e465058d JM |
1372 | |
1373 | /* | |
1374 | * if the user specified iommu=off or iommu=soft or we found | |
1375 | * another HW IOMMU already, bail out. | |
1376 | */ | |
75f1cdf1 | 1377 | if (no_iommu || iommu_detected) |
e465058d JM |
1378 | return; |
1379 | ||
bff6547b MBY |
1380 | if (!use_calgary) |
1381 | return; | |
1382 | ||
0637a70a AK |
1383 | if (!early_pci_allowed()) |
1384 | return; | |
1385 | ||
b92cc559 MBY |
1386 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1387 | ||
b34e90b8 LV |
1388 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1389 | ||
1390 | rio_table_hdr = NULL; | |
136f1e7a | 1391 | prev_offset = 0; |
b34e90b8 | 1392 | offset = 0x180; |
136f1e7a IM |
1393 | /* |
1394 | * The next offset is stored in the 1st word. | |
1395 | * Only parse up until the offset increases: | |
1396 | */ | |
1397 | while (offset > prev_offset) { | |
b34e90b8 LV |
1398 | /* The block id is stored in the 2nd word */ |
1399 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1400 | /* set the pointer past the offset & block id */ | |
eae93755 | 1401 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1402 | break; |
1403 | } | |
136f1e7a | 1404 | prev_offset = offset; |
b34e90b8 LV |
1405 | offset = *((unsigned short *)(ptr + offset)); |
1406 | } | |
eae93755 | 1407 | if (!rio_table_hdr) { |
b92cc559 MBY |
1408 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1409 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1410 | return; |
1411 | } | |
1412 | ||
eae93755 MBY |
1413 | ret = build_detail_arrays(); |
1414 | if (ret) { | |
b92cc559 | 1415 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1416 | return; |
eae93755 | 1417 | } |
b34e90b8 | 1418 | |
95b68dec C |
1419 | specified_table_size = determine_tce_table_size((is_kdump_kernel() ? |
1420 | saved_max_pfn : max_pfn) * PAGE_SIZE); | |
e465058d | 1421 | |
d2105b10 | 1422 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1423 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1424 | unsigned short pci_device; |
1425 | u32 val; | |
1426 | ||
1427 | val = read_pci_config(bus, 0, 0, 0); | |
1428 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1429 | |
8a244590 | 1430 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1431 | continue; |
d2105b10 | 1432 | |
f38db651 | 1433 | if (info->translation_disabled) |
e465058d | 1434 | continue; |
f38db651 | 1435 | |
8a244590 MBY |
1436 | if (calgary_bus_has_devices(bus, pci_device) || |
1437 | translate_empty_slots) { | |
95b68dec C |
1438 | /* |
1439 | * If it is kdump kernel, find and use tce tables | |
1440 | * from first kernel, else allocate tce tables here | |
1441 | */ | |
1442 | if (!is_kdump_kernel()) { | |
1443 | tbl = alloc_tce_table(); | |
1444 | if (!tbl) | |
1445 | goto cleanup; | |
1446 | info->tce_space = tbl; | |
1447 | } | |
8a244590 | 1448 | calgary_found = 1; |
d2105b10 | 1449 | } |
e465058d JM |
1450 | } |
1451 | ||
b92cc559 MBY |
1452 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1453 | calgary_found ? "found" : "not found"); | |
1454 | ||
d2105b10 | 1455 | if (calgary_found) { |
e465058d JM |
1456 | iommu_detected = 1; |
1457 | calgary_detected = 1; | |
de684652 | 1458 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
7e05575c FT |
1459 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n", |
1460 | specified_table_size); | |
1956a96d | 1461 | |
d7b9f7be | 1462 | x86_init.iommu.iommu_init = calgary_iommu_init; |
e465058d JM |
1463 | } |
1464 | return; | |
1465 | ||
1466 | cleanup: | |
f38db651 MBY |
1467 | for (--bus; bus >= 0; --bus) { |
1468 | struct calgary_bus_info *info = &bus_info[bus]; | |
1469 | ||
1470 | if (info->tce_space) | |
1471 | free_tce_table(info->tce_space); | |
1472 | } | |
e465058d JM |
1473 | } |
1474 | ||
e465058d JM |
1475 | static int __init calgary_parse_options(char *p) |
1476 | { | |
1477 | unsigned int bridge; | |
1478 | size_t len; | |
1479 | char* endp; | |
1480 | ||
1481 | while (*p) { | |
1482 | if (!strncmp(p, "64k", 3)) | |
1483 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1484 | else if (!strncmp(p, "128k", 4)) | |
1485 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1486 | else if (!strncmp(p, "256k", 4)) | |
1487 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1488 | else if (!strncmp(p, "512k", 4)) | |
1489 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1490 | else if (!strncmp(p, "1M", 2)) | |
1491 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1492 | else if (!strncmp(p, "2M", 2)) | |
1493 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1494 | else if (!strncmp(p, "4M", 2)) | |
1495 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1496 | else if (!strncmp(p, "8M", 2)) | |
1497 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1498 | ||
1499 | len = strlen("translate_empty_slots"); | |
1500 | if (!strncmp(p, "translate_empty_slots", len)) | |
1501 | translate_empty_slots = 1; | |
1502 | ||
1503 | len = strlen("disable"); | |
1504 | if (!strncmp(p, "disable", len)) { | |
1505 | p += len; | |
1506 | if (*p == '=') | |
1507 | ++p; | |
1508 | if (*p == '\0') | |
1509 | break; | |
eff79aee | 1510 | bridge = simple_strtoul(p, &endp, 0); |
e465058d JM |
1511 | if (p == endp) |
1512 | break; | |
1513 | ||
d2105b10 | 1514 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1515 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1516 | "translation for PHB %#x\n", bridge); |
f38db651 | 1517 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1518 | } |
1519 | } | |
1520 | ||
1521 | p = strpbrk(p, ","); | |
1522 | if (!p) | |
1523 | break; | |
1524 | ||
1525 | p++; /* skip ',' */ | |
1526 | } | |
1527 | return 1; | |
1528 | } | |
1529 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1530 | |
1531 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1532 | { | |
1533 | struct iommu_table *tbl; | |
1534 | unsigned int npages; | |
1535 | int i; | |
1536 | ||
08f1c192 | 1537 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1538 | |
1539 | for (i = 0; i < 4; i++) { | |
1540 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1541 | ||
1542 | /* Don't give out TCEs that map MEM resources */ | |
1543 | if (!(r->flags & IORESOURCE_MEM)) | |
1544 | continue; | |
1545 | ||
1546 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1547 | if (!r->start) | |
1548 | continue; | |
1549 | ||
1550 | /* cover the whole region */ | |
1551 | npages = (r->end - r->start) >> PAGE_SHIFT; | |
1552 | npages++; | |
1553 | ||
07877cf6 MBY |
1554 | iommu_range_reserve(tbl, r->start, npages); |
1555 | } | |
1556 | } | |
1557 | ||
1558 | static int __init calgary_fixup_tce_spaces(void) | |
1559 | { | |
1560 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1561 | struct calgary_bus_info *info; |
07877cf6 MBY |
1562 | |
1563 | if (no_iommu || swiotlb || !calgary_detected) | |
1564 | return -ENODEV; | |
1565 | ||
12de257b | 1566 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1567 | |
1568 | do { | |
1569 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1570 | if (!dev) | |
1571 | break; | |
1572 | if (!is_cal_pci_dev(dev->device)) | |
1573 | continue; | |
bc3c6058 MBY |
1574 | |
1575 | info = &bus_info[dev->bus->number]; | |
1576 | if (info->translation_disabled) | |
07877cf6 MBY |
1577 | continue; |
1578 | ||
bc3c6058 | 1579 | if (!info->tce_space) |
07877cf6 MBY |
1580 | continue; |
1581 | ||
1582 | calgary_fixup_one_tce_space(dev); | |
1583 | ||
1584 | } while (1); | |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | /* | |
1590 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1591 | * and before device_initcall. | |
1592 | */ | |
1593 | rootfs_initcall(calgary_fixup_tce_spaces); |