]>
Commit | Line | Data |
---|---|---|
459121c9 | 1 | #include <linux/dma-mapping.h> |
2118d0c5 | 2 | #include <linux/dma-debug.h> |
cb5867a5 | 3 | #include <linux/dmar.h> |
69c60c88 | 4 | #include <linux/export.h> |
116890d5 | 5 | #include <linux/bootmem.h> |
5a0e3ad6 | 6 | #include <linux/gfp.h> |
bca5c096 | 7 | #include <linux/pci.h> |
acde31dc | 8 | #include <linux/kmemleak.h> |
cb5867a5 | 9 | |
116890d5 GC |
10 | #include <asm/proto.h> |
11 | #include <asm/dma.h> | |
46a7fa27 | 12 | #include <asm/iommu.h> |
1d9b16d1 | 13 | #include <asm/gart.h> |
cb5867a5 | 14 | #include <asm/calgary.h> |
b4941a9a | 15 | #include <asm/x86_init.h> |
ee1f284f | 16 | #include <asm/iommu_table.h> |
459121c9 | 17 | |
3b15e581 FY |
18 | static int forbid_dac __read_mostly; |
19 | ||
a3b28ee1 | 20 | struct dma_map_ops *dma_ops = &nommu_dma_ops; |
85c246ee GC |
21 | EXPORT_SYMBOL(dma_ops); |
22 | ||
b4cdc430 | 23 | static int iommu_sac_force __read_mostly; |
8e0c3797 | 24 | |
f9c258de GC |
25 | #ifdef CONFIG_IOMMU_DEBUG |
26 | int panic_on_overflow __read_mostly = 1; | |
27 | int force_iommu __read_mostly = 1; | |
28 | #else | |
29 | int panic_on_overflow __read_mostly = 0; | |
30 | int force_iommu __read_mostly = 0; | |
31 | #endif | |
32 | ||
fae9a0d8 GC |
33 | int iommu_merge __read_mostly = 0; |
34 | ||
35 | int no_iommu __read_mostly; | |
36 | /* Set this to 1 if there is a HW IOMMU in the system */ | |
37 | int iommu_detected __read_mostly = 0; | |
38 | ||
ac0101d3 JR |
39 | /* |
40 | * This variable becomes 1 if iommu=pt is passed on the kernel command line. | |
e3be785f | 41 | * If this variable is 1, IOMMU implementations do no DMA translation for |
ac0101d3 | 42 | * devices and allow every device to access to whole physical memory. This is |
fb637f3c | 43 | * useful if a user wants to use an IOMMU only for KVM device assignment to |
ac0101d3 JR |
44 | * guests and not for driver dma translation. |
45 | */ | |
46 | int iommu_pass_through __read_mostly; | |
aed5d5f4 | 47 | |
ee1f284f KRW |
48 | extern struct iommu_table_entry __iommu_table[], __iommu_table_end[]; |
49 | ||
eb647138 | 50 | /* Dummy device used for NULL arguments (normally ISA). */ |
6c505ce3 | 51 | struct device x86_dma_fallback_dev = { |
1a927133 | 52 | .init_name = "fallback device", |
eb647138 | 53 | .coherent_dma_mask = ISA_DMA_BIT_MASK, |
6c505ce3 | 54 | .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask, |
098cb7f2 | 55 | }; |
6c505ce3 | 56 | EXPORT_SYMBOL(x86_dma_fallback_dev); |
098cb7f2 | 57 | |
2118d0c5 | 58 | /* Number of entries preallocated for DMA-API debugging */ |
73b664ce | 59 | #define PREALLOC_DMA_DEBUG_ENTRIES 65536 |
2118d0c5 | 60 | |
116890d5 GC |
61 | void __init pci_iommu_alloc(void) |
62 | { | |
ee1f284f KRW |
63 | struct iommu_table_entry *p; |
64 | ||
ee1f284f KRW |
65 | sort_iommu_table(__iommu_table, __iommu_table_end); |
66 | check_iommu_entries(__iommu_table, __iommu_table_end); | |
116890d5 | 67 | |
ee1f284f KRW |
68 | for (p = __iommu_table; p < __iommu_table_end; p++) { |
69 | if (p && p->detect && p->detect() > 0) { | |
70 | p->flags |= IOMMU_DETECTED; | |
71 | if (p->early_init) | |
72 | p->early_init(); | |
73 | if (p->flags & IOMMU_FINISH_IF_DETECTED) | |
74 | break; | |
75 | } | |
76 | } | |
116890d5 | 77 | } |
9f6ac577 | 78 | void *dma_generic_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
79 | dma_addr_t *dma_addr, gfp_t flag, |
80 | struct dma_attrs *attrs) | |
9f6ac577 FT |
81 | { |
82 | unsigned long dma_mask; | |
c080e26e | 83 | struct page *page; |
0a2b9a6e | 84 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
9f6ac577 FT |
85 | dma_addr_t addr; |
86 | ||
87 | dma_mask = dma_alloc_coherent_mask(dev, flag); | |
88 | ||
d92ef66c | 89 | flag &= ~__GFP_ZERO; |
9f6ac577 | 90 | again: |
c080e26e | 91 | page = NULL; |
c091c71a | 92 | /* CMA can be used only in the context which permits sleeping */ |
d0164adc | 93 | if (gfpflags_allow_blocking(flag)) { |
0a2b9a6e | 94 | page = dma_alloc_from_contiguous(dev, count, get_order(size)); |
38f7ea5a AM |
95 | if (page && page_to_phys(page) + size > dma_mask) { |
96 | dma_release_from_contiguous(dev, page, count); | |
97 | page = NULL; | |
98 | } | |
99 | } | |
c091c71a | 100 | /* fallback */ |
0a2b9a6e MS |
101 | if (!page) |
102 | page = alloc_pages_node(dev_to_node(dev), flag, get_order(size)); | |
9f6ac577 FT |
103 | if (!page) |
104 | return NULL; | |
105 | ||
106 | addr = page_to_phys(page); | |
a4c2baa6 | 107 | if (addr + size > dma_mask) { |
9f6ac577 FT |
108 | __free_pages(page, get_order(size)); |
109 | ||
284901a9 | 110 | if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) { |
9f6ac577 FT |
111 | flag = (flag & ~GFP_DMA32) | GFP_DMA; |
112 | goto again; | |
113 | } | |
114 | ||
115 | return NULL; | |
116 | } | |
d92ef66c | 117 | memset(page_address(page), 0, size); |
9f6ac577 FT |
118 | *dma_addr = addr; |
119 | return page_address(page); | |
120 | } | |
121 | ||
0a2b9a6e MS |
122 | void dma_generic_free_coherent(struct device *dev, size_t size, void *vaddr, |
123 | dma_addr_t dma_addr, struct dma_attrs *attrs) | |
124 | { | |
125 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
126 | struct page *page = virt_to_page(vaddr); | |
127 | ||
128 | if (!dma_release_from_contiguous(dev, page, count)) | |
129 | free_pages((unsigned long)vaddr, get_order(size)); | |
130 | } | |
131 | ||
6894258e | 132 | bool arch_dma_alloc_attrs(struct device **dev, gfp_t *gfp) |
0c7965ff | 133 | { |
298a96c1 VS |
134 | if (!*dev) |
135 | *dev = &x86_dma_fallback_dev; | |
136 | ||
6894258e | 137 | *gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
590f0787 | 138 | *gfp = dma_alloc_coherent_gfp_flags(*dev, *gfp); |
0c7965ff | 139 | |
6894258e CH |
140 | if (!is_device_dma_capable(*dev)) |
141 | return false; | |
142 | return true; | |
0c7965ff | 143 | |
f1dc154f | 144 | } |
6894258e | 145 | EXPORT_SYMBOL(arch_dma_alloc_attrs); |
f1dc154f | 146 | |
fae9a0d8 | 147 | /* |
395cf969 PB |
148 | * See <Documentation/x86/x86_64/boot-options.txt> for the iommu kernel |
149 | * parameter documentation. | |
fae9a0d8 GC |
150 | */ |
151 | static __init int iommu_setup(char *p) | |
152 | { | |
153 | iommu_merge = 1; | |
154 | ||
155 | if (!p) | |
156 | return -EINVAL; | |
157 | ||
158 | while (*p) { | |
159 | if (!strncmp(p, "off", 3)) | |
160 | no_iommu = 1; | |
161 | /* gart_parse_options has more force support */ | |
162 | if (!strncmp(p, "force", 5)) | |
163 | force_iommu = 1; | |
164 | if (!strncmp(p, "noforce", 7)) { | |
165 | iommu_merge = 0; | |
166 | force_iommu = 0; | |
167 | } | |
168 | ||
169 | if (!strncmp(p, "biomerge", 8)) { | |
fae9a0d8 GC |
170 | iommu_merge = 1; |
171 | force_iommu = 1; | |
172 | } | |
173 | if (!strncmp(p, "panic", 5)) | |
174 | panic_on_overflow = 1; | |
175 | if (!strncmp(p, "nopanic", 7)) | |
176 | panic_on_overflow = 0; | |
177 | if (!strncmp(p, "merge", 5)) { | |
178 | iommu_merge = 1; | |
179 | force_iommu = 1; | |
180 | } | |
181 | if (!strncmp(p, "nomerge", 7)) | |
182 | iommu_merge = 0; | |
183 | if (!strncmp(p, "forcesac", 8)) | |
184 | iommu_sac_force = 1; | |
185 | if (!strncmp(p, "allowdac", 8)) | |
186 | forbid_dac = 0; | |
187 | if (!strncmp(p, "nodac", 5)) | |
2ae8bb75 | 188 | forbid_dac = 1; |
fae9a0d8 GC |
189 | if (!strncmp(p, "usedac", 6)) { |
190 | forbid_dac = -1; | |
191 | return 1; | |
192 | } | |
193 | #ifdef CONFIG_SWIOTLB | |
194 | if (!strncmp(p, "soft", 4)) | |
195 | swiotlb = 1; | |
3238c0c4 | 196 | #endif |
80286879 | 197 | if (!strncmp(p, "pt", 2)) |
4ed0d3e6 | 198 | iommu_pass_through = 1; |
fae9a0d8 | 199 | |
fae9a0d8 | 200 | gart_parse_options(p); |
fae9a0d8 GC |
201 | |
202 | #ifdef CONFIG_CALGARY_IOMMU | |
203 | if (!strncmp(p, "calgary", 7)) | |
204 | use_calgary = 1; | |
205 | #endif /* CONFIG_CALGARY_IOMMU */ | |
206 | ||
207 | p += strcspn(p, ","); | |
208 | if (*p == ',') | |
209 | ++p; | |
210 | } | |
211 | return 0; | |
212 | } | |
213 | early_param("iommu", iommu_setup); | |
214 | ||
8e0c3797 GC |
215 | int dma_supported(struct device *dev, u64 mask) |
216 | { | |
160c1d8e | 217 | struct dma_map_ops *ops = get_dma_ops(dev); |
8d8bb39b | 218 | |
8e0c3797 GC |
219 | #ifdef CONFIG_PCI |
220 | if (mask > 0xffffffff && forbid_dac > 0) { | |
fc3a8828 | 221 | dev_info(dev, "PCI: Disallowing DAC for device\n"); |
8e0c3797 GC |
222 | return 0; |
223 | } | |
224 | #endif | |
225 | ||
8d8bb39b FT |
226 | if (ops->dma_supported) |
227 | return ops->dma_supported(dev, mask); | |
8e0c3797 GC |
228 | |
229 | /* Copied from i386. Doesn't make much sense, because it will | |
230 | only work for pci_alloc_coherent. | |
231 | The caller just has to use GFP_DMA in this case. */ | |
2f4f27d4 | 232 | if (mask < DMA_BIT_MASK(24)) |
8e0c3797 GC |
233 | return 0; |
234 | ||
235 | /* Tell the device to use SAC when IOMMU force is on. This | |
236 | allows the driver to use cheaper accesses in some cases. | |
237 | ||
238 | Problem with this is that if we overflow the IOMMU area and | |
239 | return DAC as fallback address the device may not handle it | |
240 | correctly. | |
241 | ||
242 | As a special case some controllers have a 39bit address | |
243 | mode that is as efficient as 32bit (aic79xx). Don't force | |
244 | SAC for these. Assume all masks <= 40 bits are of this | |
245 | type. Normally this doesn't make any difference, but gives | |
246 | more gentle handling of IOMMU overflow. */ | |
50cf156a | 247 | if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) { |
fc3a8828 | 248 | dev_info(dev, "Force SAC with mask %Lx\n", mask); |
8e0c3797 GC |
249 | return 0; |
250 | } | |
251 | ||
252 | return 1; | |
253 | } | |
254 | EXPORT_SYMBOL(dma_supported); | |
255 | ||
cb5867a5 GC |
256 | static int __init pci_iommu_init(void) |
257 | { | |
ee1f284f | 258 | struct iommu_table_entry *p; |
2118d0c5 JR |
259 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); |
260 | ||
86f31952 JR |
261 | #ifdef CONFIG_PCI |
262 | dma_debug_add_bus(&pci_bus_type); | |
263 | #endif | |
d07c1be0 FT |
264 | x86_init.iommu.iommu_init(); |
265 | ||
ee1f284f KRW |
266 | for (p = __iommu_table; p < __iommu_table_end; p++) { |
267 | if (p && (p->flags & IOMMU_DETECTED) && p->late_init) | |
268 | p->late_init(); | |
269 | } | |
75f1cdf1 | 270 | |
cb5867a5 GC |
271 | return 0; |
272 | } | |
cb5867a5 | 273 | /* Must execute after PCI subsystem */ |
9a821b23 | 274 | rootfs_initcall(pci_iommu_init); |
3b15e581 FY |
275 | |
276 | #ifdef CONFIG_PCI | |
277 | /* Many VIA bridges seem to corrupt data for DAC. Disable it here */ | |
278 | ||
a18e3690 | 279 | static void via_no_dac(struct pci_dev *dev) |
3b15e581 | 280 | { |
c484b241 | 281 | if (forbid_dac == 0) { |
13bf7576 | 282 | dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n"); |
3b15e581 FY |
283 | forbid_dac = 1; |
284 | } | |
285 | } | |
c484b241 YL |
286 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, |
287 | PCI_CLASS_BRIDGE_PCI, 8, via_no_dac); | |
3b15e581 | 288 | #endif |