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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 LT |
7 | * |
8 | * See Documentation/DMA-mapping.txt for the interface specification. | |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
cd76374e | 29 | #include <linux/sysdev.h> |
1da177e4 LT |
30 | #include <asm/atomic.h> |
31 | #include <asm/io.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/proto.h> | |
46a7fa27 | 35 | #include <asm/iommu.h> |
395624fc | 36 | #include <asm/gart.h> |
1da177e4 | 37 | #include <asm/cacheflush.h> |
17a941d8 MBY |
38 | #include <asm/swiotlb.h> |
39 | #include <asm/dma.h> | |
a32073bf | 40 | #include <asm/k8.h> |
1da177e4 | 41 | |
79da0874 | 42 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 43 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
44 | static unsigned long iommu_pages; /* .. and in pages */ |
45 | ||
05fccb0e | 46 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 47 | |
05fccb0e IM |
48 | /* |
49 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
50 | * of only flushing when an mapping is reused. With it true the GART is | |
51 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
52 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
53 | * has been also also seen with Qlogic at least). | |
54 | */ | |
1da177e4 LT |
55 | int iommu_fullflush = 1; |
56 | ||
05fccb0e | 57 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 58 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
59 | /* Guarded by iommu_bitmap_lock: */ |
60 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 61 | |
05fccb0e | 62 | static u32 gart_unmapped_entry; |
1da177e4 LT |
63 | |
64 | #define GPTE_VALID 1 | |
65 | #define GPTE_COHERENT 2 | |
66 | #define GPTE_ENCODE(x) \ | |
67 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
68 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
69 | ||
05fccb0e | 70 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
71 | |
72 | #ifdef CONFIG_AGP | |
73 | #define AGPEXTERN extern | |
74 | #else | |
75 | #define AGPEXTERN | |
76 | #endif | |
77 | ||
78 | /* backdoor interface to AGP driver */ | |
79 | AGPEXTERN int agp_memory_reserved; | |
80 | AGPEXTERN __u32 *agp_gatt_table; | |
81 | ||
82 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
05fccb0e | 83 | static int need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 84 | |
fde9a109 | 85 | static unsigned long alloc_iommu(struct device *dev, int size) |
05fccb0e | 86 | { |
1da177e4 | 87 | unsigned long offset, flags; |
fde9a109 FT |
88 | unsigned long boundary_size; |
89 | unsigned long base_index; | |
90 | ||
91 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
92 | PAGE_SIZE) >> PAGE_SHIFT; | |
93 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
94 | PAGE_SIZE) >> PAGE_SHIFT; | |
1da177e4 | 95 | |
05fccb0e | 96 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 FT |
97 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
98 | size, base_index, boundary_size, 0); | |
1da177e4 LT |
99 | if (offset == -1) { |
100 | need_flush = 1; | |
fde9a109 FT |
101 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
102 | size, base_index, boundary_size, 0); | |
1da177e4 | 103 | } |
05fccb0e | 104 | if (offset != -1) { |
05fccb0e IM |
105 | next_bit = offset+size; |
106 | if (next_bit >= iommu_pages) { | |
1da177e4 LT |
107 | next_bit = 0; |
108 | need_flush = 1; | |
05fccb0e IM |
109 | } |
110 | } | |
1da177e4 LT |
111 | if (iommu_fullflush) |
112 | need_flush = 1; | |
05fccb0e IM |
113 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
114 | ||
1da177e4 | 115 | return offset; |
05fccb0e | 116 | } |
1da177e4 LT |
117 | |
118 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 119 | { |
1da177e4 | 120 | unsigned long flags; |
05fccb0e | 121 | |
1da177e4 | 122 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 123 | iommu_area_free(iommu_gart_bitmap, offset, size); |
1da177e4 | 124 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 125 | } |
1da177e4 | 126 | |
05fccb0e | 127 | /* |
1da177e4 LT |
128 | * Use global flush state to avoid races with multiple flushers. |
129 | */ | |
a32073bf | 130 | static void flush_gart(void) |
05fccb0e | 131 | { |
1da177e4 | 132 | unsigned long flags; |
05fccb0e | 133 | |
1da177e4 | 134 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
135 | if (need_flush) { |
136 | k8_flush_garts(); | |
1da177e4 | 137 | need_flush = 0; |
05fccb0e | 138 | } |
1da177e4 | 139 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 140 | } |
1da177e4 | 141 | |
1da177e4 LT |
142 | #ifdef CONFIG_IOMMU_LEAK |
143 | ||
05fccb0e IM |
144 | #define SET_LEAK(x) \ |
145 | do { \ | |
146 | if (iommu_leak_tab) \ | |
147 | iommu_leak_tab[x] = __builtin_return_address(0);\ | |
148 | } while (0) | |
149 | ||
150 | #define CLEAR_LEAK(x) \ | |
151 | do { \ | |
152 | if (iommu_leak_tab) \ | |
153 | iommu_leak_tab[x] = NULL; \ | |
154 | } while (0) | |
1da177e4 LT |
155 | |
156 | /* Debugging aid for drivers that don't free their IOMMU tables */ | |
05fccb0e | 157 | static void **iommu_leak_tab; |
1da177e4 | 158 | static int leak_trace; |
79da0874 | 159 | static int iommu_leak_pages = 20; |
05fccb0e | 160 | |
79da0874 | 161 | static void dump_leak(void) |
1da177e4 LT |
162 | { |
163 | int i; | |
05fccb0e IM |
164 | static int dump; |
165 | ||
166 | if (dump || !iommu_leak_tab) | |
167 | return; | |
1da177e4 | 168 | dump = 1; |
05fccb0e IM |
169 | show_stack(NULL, NULL); |
170 | ||
171 | /* Very crude. dump some from the end of the table too */ | |
172 | printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n", | |
173 | iommu_leak_pages); | |
174 | for (i = 0; i < iommu_leak_pages; i += 2) { | |
175 | printk(KERN_DEBUG "%lu: ", iommu_pages-i); | |
bc850d6b | 176 | printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0); |
05fccb0e IM |
177 | printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' '); |
178 | } | |
179 | printk(KERN_DEBUG "\n"); | |
1da177e4 LT |
180 | } |
181 | #else | |
05fccb0e IM |
182 | # define SET_LEAK(x) |
183 | # define CLEAR_LEAK(x) | |
1da177e4 LT |
184 | #endif |
185 | ||
17a941d8 | 186 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 187 | { |
05fccb0e | 188 | /* |
1da177e4 LT |
189 | * Ran out of IOMMU space for this operation. This is very bad. |
190 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 191 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
192 | * let the Northbridge deal with it. This will result in garbage |
193 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 194 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 195 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
196 | */ |
197 | ||
fc3a8828 | 198 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 199 | |
17a941d8 | 200 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
201 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
202 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
203 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
204 | panic(KERN_ERR | |
205 | "PCI-DMA: Random memory would be DMAed\n"); | |
206 | } | |
1da177e4 | 207 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 208 | dump_leak(); |
1da177e4 | 209 | #endif |
05fccb0e | 210 | } |
1da177e4 | 211 | |
05fccb0e IM |
212 | static inline int |
213 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
214 | { | |
1da177e4 | 215 | u64 mask = *dev->dma_mask; |
00edefae | 216 | int high = addr + size > mask; |
1da177e4 | 217 | int mmu = high; |
05fccb0e IM |
218 | |
219 | if (force_iommu) | |
220 | mmu = 1; | |
221 | ||
222 | return mmu; | |
1da177e4 LT |
223 | } |
224 | ||
05fccb0e IM |
225 | static inline int |
226 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
227 | { | |
1da177e4 | 228 | u64 mask = *dev->dma_mask; |
00edefae | 229 | int high = addr + size > mask; |
1da177e4 | 230 | int mmu = high; |
05fccb0e IM |
231 | |
232 | return mmu; | |
1da177e4 LT |
233 | } |
234 | ||
235 | /* Map a single continuous physical area into the IOMMU. | |
236 | * Caller needs to check if the iommu is needed and flush. | |
237 | */ | |
17a941d8 MBY |
238 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
239 | size_t size, int dir) | |
05fccb0e | 240 | { |
87e39ea5 | 241 | unsigned long npages = iommu_num_pages(phys_mem, size); |
fde9a109 | 242 | unsigned long iommu_page = alloc_iommu(dev, npages); |
1da177e4 | 243 | int i; |
05fccb0e | 244 | |
1da177e4 LT |
245 | if (iommu_page == -1) { |
246 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 247 | return phys_mem; |
1da177e4 LT |
248 | if (panic_on_overflow) |
249 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 250 | iommu_full(dev, size, dir); |
1da177e4 LT |
251 | return bad_dma_address; |
252 | } | |
253 | ||
254 | for (i = 0; i < npages; i++) { | |
255 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
256 | SET_LEAK(iommu_page + i); | |
257 | phys_mem += PAGE_SIZE; | |
258 | } | |
259 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
260 | } | |
261 | ||
05fccb0e | 262 | static dma_addr_t |
2be62149 | 263 | gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir) |
17a941d8 | 264 | { |
2be62149 | 265 | dma_addr_t map = dma_map_area(dev, paddr, size, dir); |
05fccb0e | 266 | |
a32073bf | 267 | flush_gart(); |
05fccb0e | 268 | |
17a941d8 MBY |
269 | return map; |
270 | } | |
271 | ||
1da177e4 | 272 | /* Map a single area into the IOMMU */ |
05fccb0e | 273 | static dma_addr_t |
2be62149 | 274 | gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir) |
1da177e4 | 275 | { |
2be62149 | 276 | unsigned long bus; |
1da177e4 | 277 | |
1da177e4 LT |
278 | if (!dev) |
279 | dev = &fallback_dev; | |
280 | ||
2be62149 IM |
281 | if (!need_iommu(dev, paddr, size)) |
282 | return paddr; | |
1da177e4 | 283 | |
2be62149 | 284 | bus = gart_map_simple(dev, paddr, size, dir); |
05fccb0e IM |
285 | |
286 | return bus; | |
17a941d8 MBY |
287 | } |
288 | ||
7c2d9cd2 JM |
289 | /* |
290 | * Free a DMA mapping. | |
291 | */ | |
1048fa52 | 292 | static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, |
05fccb0e | 293 | size_t size, int direction) |
7c2d9cd2 JM |
294 | { |
295 | unsigned long iommu_page; | |
296 | int npages; | |
297 | int i; | |
298 | ||
299 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
300 | dma_addr >= iommu_bus_base + iommu_size) | |
301 | return; | |
05fccb0e | 302 | |
7c2d9cd2 | 303 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
87e39ea5 | 304 | npages = iommu_num_pages(dma_addr, size); |
7c2d9cd2 JM |
305 | for (i = 0; i < npages; i++) { |
306 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
307 | CLEAR_LEAK(iommu_page + i); | |
308 | } | |
309 | free_iommu(iommu_page, npages); | |
310 | } | |
311 | ||
17a941d8 MBY |
312 | /* |
313 | * Wrapper for pci_unmap_single working with scatterlists. | |
314 | */ | |
05fccb0e IM |
315 | static void |
316 | gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
17a941d8 | 317 | { |
9ee1bea4 | 318 | struct scatterlist *s; |
17a941d8 MBY |
319 | int i; |
320 | ||
9ee1bea4 | 321 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 322 | if (!s->dma_length || !s->length) |
17a941d8 | 323 | break; |
7c2d9cd2 | 324 | gart_unmap_single(dev, s->dma_address, s->dma_length, dir); |
17a941d8 MBY |
325 | } |
326 | } | |
1da177e4 LT |
327 | |
328 | /* Fallback for dma_map_sg in case of overflow */ | |
329 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
330 | int nents, int dir) | |
331 | { | |
9ee1bea4 | 332 | struct scatterlist *s; |
1da177e4 LT |
333 | int i; |
334 | ||
335 | #ifdef CONFIG_IOMMU_DEBUG | |
336 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
337 | #endif | |
338 | ||
9ee1bea4 | 339 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 340 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
341 | |
342 | if (nonforced_iommu(dev, addr, s->length)) { | |
17a941d8 | 343 | addr = dma_map_area(dev, addr, s->length, dir); |
05fccb0e IM |
344 | if (addr == bad_dma_address) { |
345 | if (i > 0) | |
17a941d8 | 346 | gart_unmap_sg(dev, sg, i, dir); |
05fccb0e | 347 | nents = 0; |
1da177e4 LT |
348 | sg[0].dma_length = 0; |
349 | break; | |
350 | } | |
351 | } | |
352 | s->dma_address = addr; | |
353 | s->dma_length = s->length; | |
354 | } | |
a32073bf | 355 | flush_gart(); |
05fccb0e | 356 | |
1da177e4 LT |
357 | return nents; |
358 | } | |
359 | ||
360 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
361 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
362 | int nelems, struct scatterlist *sout, | |
363 | unsigned long pages) | |
1da177e4 | 364 | { |
fde9a109 | 365 | unsigned long iommu_start = alloc_iommu(dev, pages); |
05fccb0e | 366 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 367 | struct scatterlist *s; |
1da177e4 LT |
368 | int i; |
369 | ||
370 | if (iommu_start == -1) | |
371 | return -1; | |
9ee1bea4 JA |
372 | |
373 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
374 | unsigned long pages, addr; |
375 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 376 | |
9ee1bea4 JA |
377 | BUG_ON(s != start && s->offset); |
378 | if (s == start) { | |
1da177e4 LT |
379 | sout->dma_address = iommu_bus_base; |
380 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
381 | sout->dma_length = s->length; | |
05fccb0e IM |
382 | } else { |
383 | sout->dma_length += s->length; | |
1da177e4 LT |
384 | } |
385 | ||
386 | addr = phys_addr; | |
87e39ea5 | 387 | pages = iommu_num_pages(s->offset, s->length); |
05fccb0e IM |
388 | while (pages--) { |
389 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
390 | SET_LEAK(iommu_page); |
391 | addr += PAGE_SIZE; | |
392 | iommu_page++; | |
0d541064 | 393 | } |
05fccb0e IM |
394 | } |
395 | BUG_ON(iommu_page - iommu_start != pages); | |
396 | ||
1da177e4 LT |
397 | return 0; |
398 | } | |
399 | ||
05fccb0e | 400 | static inline int |
fde9a109 FT |
401 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
402 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 403 | { |
9ee1bea4 JA |
404 | if (!need) { |
405 | BUG_ON(nelems != 1); | |
e88a39de | 406 | sout->dma_address = start->dma_address; |
9ee1bea4 | 407 | sout->dma_length = start->length; |
1da177e4 | 408 | return 0; |
9ee1bea4 | 409 | } |
fde9a109 | 410 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 411 | } |
05fccb0e | 412 | |
1da177e4 LT |
413 | /* |
414 | * DMA map all entries in a scatterlist. | |
05fccb0e | 415 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 416 | */ |
05fccb0e IM |
417 | static int |
418 | gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
1da177e4 | 419 | { |
9ee1bea4 | 420 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
421 | int need = 0, nextneed, i, out, start; |
422 | unsigned long pages = 0; | |
42d00284 FT |
423 | unsigned int seg_size; |
424 | unsigned int max_seg_size; | |
1da177e4 | 425 | |
05fccb0e | 426 | if (nents == 0) |
1da177e4 LT |
427 | return 0; |
428 | ||
1da177e4 LT |
429 | if (!dev) |
430 | dev = &fallback_dev; | |
431 | ||
432 | out = 0; | |
433 | start = 0; | |
9ee1bea4 | 434 | start_sg = sgmap = sg; |
42d00284 FT |
435 | seg_size = 0; |
436 | max_seg_size = dma_get_max_seg_size(dev); | |
9ee1bea4 JA |
437 | ps = NULL; /* shut up gcc */ |
438 | for_each_sg(sg, s, nents, i) { | |
58b053e4 | 439 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 440 | |
1da177e4 | 441 | s->dma_address = addr; |
05fccb0e | 442 | BUG_ON(s->length == 0); |
1da177e4 | 443 | |
05fccb0e | 444 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
445 | |
446 | /* Handle the previous not yet processed entries */ | |
447 | if (i > start) { | |
05fccb0e IM |
448 | /* |
449 | * Can only merge when the last chunk ends on a | |
450 | * page boundary and the new one doesn't have an | |
451 | * offset. | |
452 | */ | |
1da177e4 | 453 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 454 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 455 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
456 | if (dma_map_cont(dev, start_sg, i - start, |
457 | sgmap, pages, need) < 0) | |
1da177e4 LT |
458 | goto error; |
459 | out++; | |
42d00284 | 460 | seg_size = 0; |
9ee1bea4 | 461 | sgmap = sg_next(sgmap); |
1da177e4 | 462 | pages = 0; |
9ee1bea4 JA |
463 | start = i; |
464 | start_sg = s; | |
1da177e4 LT |
465 | } |
466 | } | |
467 | ||
42d00284 | 468 | seg_size += s->length; |
1da177e4 | 469 | need = nextneed; |
87e39ea5 | 470 | pages += iommu_num_pages(s->offset, s->length); |
9ee1bea4 | 471 | ps = s; |
1da177e4 | 472 | } |
fde9a109 | 473 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
474 | goto error; |
475 | out++; | |
a32073bf | 476 | flush_gart(); |
9ee1bea4 JA |
477 | if (out < nents) { |
478 | sgmap = sg_next(sgmap); | |
479 | sgmap->dma_length = 0; | |
480 | } | |
1da177e4 LT |
481 | return out; |
482 | ||
483 | error: | |
a32073bf | 484 | flush_gart(); |
5336940d | 485 | gart_unmap_sg(dev, sg, out, dir); |
05fccb0e | 486 | |
a1002a48 KV |
487 | /* When it was forced or merged try again in a dumb way */ |
488 | if (force_iommu || iommu_merge) { | |
489 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
490 | if (out > 0) | |
491 | return out; | |
492 | } | |
1da177e4 LT |
493 | if (panic_on_overflow) |
494 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 495 | |
17a941d8 | 496 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 JA |
497 | for_each_sg(sg, s, nents, i) |
498 | s->dma_address = bad_dma_address; | |
1da177e4 | 499 | return 0; |
05fccb0e | 500 | } |
1da177e4 | 501 | |
17a941d8 | 502 | static int no_agp; |
1da177e4 LT |
503 | |
504 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
505 | { |
506 | unsigned long a; | |
507 | ||
508 | if (!iommu_size) { | |
509 | iommu_size = aper_size; | |
510 | if (!no_agp) | |
511 | iommu_size /= 2; | |
512 | } | |
513 | ||
514 | a = aper + iommu_size; | |
31422c51 | 515 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 516 | |
05fccb0e | 517 | if (iommu_size < 64*1024*1024) { |
1da177e4 | 518 | printk(KERN_WARNING |
05fccb0e IM |
519 | "PCI-DMA: Warning: Small IOMMU %luMB." |
520 | " Consider increasing the AGP aperture in BIOS\n", | |
521 | iommu_size >> 20); | |
522 | } | |
523 | ||
1da177e4 | 524 | return iommu_size; |
05fccb0e | 525 | } |
1da177e4 | 526 | |
05fccb0e IM |
527 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
528 | { | |
529 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 530 | u64 aper_base; |
1da177e4 | 531 | |
3bb6fbf9 PM |
532 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
533 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 534 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 535 | |
05fccb0e | 536 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
537 | aper_base <<= 25; |
538 | ||
05fccb0e IM |
539 | aper_size = (32 * 1024 * 1024) << aper_order; |
540 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
541 | aper_base = 0; |
542 | ||
543 | *size = aper_size; | |
544 | return aper_base; | |
05fccb0e | 545 | } |
1da177e4 | 546 | |
6703f6d1 RW |
547 | static void enable_gart_translations(void) |
548 | { | |
549 | int i; | |
550 | ||
551 | for (i = 0; i < num_k8_northbridges; i++) { | |
552 | struct pci_dev *dev = k8_northbridges[i]; | |
553 | ||
554 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
555 | } | |
556 | } | |
557 | ||
558 | /* | |
559 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
560 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
561 | */ | |
562 | static bool fix_up_north_bridges; | |
563 | static u32 aperture_order; | |
564 | static u32 aperture_alloc; | |
565 | ||
566 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
567 | { | |
568 | fix_up_north_bridges = true; | |
569 | aperture_order = aper_order; | |
570 | aperture_alloc = aper_alloc; | |
571 | } | |
572 | ||
cd76374e PM |
573 | static int gart_resume(struct sys_device *dev) |
574 | { | |
6703f6d1 RW |
575 | printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n"); |
576 | ||
577 | if (fix_up_north_bridges) { | |
578 | int i; | |
579 | ||
580 | printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n"); | |
581 | ||
582 | for (i = 0; i < num_k8_northbridges; i++) { | |
583 | struct pci_dev *dev = k8_northbridges[i]; | |
584 | ||
585 | /* | |
586 | * Don't enable translations just yet. That is the next | |
587 | * step. Restore the pre-suspend aperture settings. | |
588 | */ | |
589 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, | |
590 | aperture_order << 1); | |
591 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, | |
592 | aperture_alloc >> 25); | |
593 | } | |
594 | } | |
595 | ||
596 | enable_gart_translations(); | |
597 | ||
cd76374e PM |
598 | return 0; |
599 | } | |
600 | ||
601 | static int gart_suspend(struct sys_device *dev, pm_message_t state) | |
602 | { | |
6703f6d1 | 603 | return 0; |
cd76374e PM |
604 | } |
605 | ||
606 | static struct sysdev_class gart_sysdev_class = { | |
607 | .name = "gart", | |
608 | .suspend = gart_suspend, | |
609 | .resume = gart_resume, | |
610 | ||
611 | }; | |
612 | ||
613 | static struct sys_device device_gart = { | |
614 | .id = 0, | |
615 | .cls = &gart_sysdev_class, | |
616 | }; | |
617 | ||
05fccb0e | 618 | /* |
1da177e4 | 619 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 620 | * AGP driver for some reason. |
1da177e4 LT |
621 | */ |
622 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
623 | { |
624 | unsigned aper_size, gatt_size, new_aper_size; | |
625 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
626 | struct pci_dev *dev; |
627 | void *gatt; | |
cd76374e | 628 | int i, error; |
7ab073b6 | 629 | unsigned long start_pfn, end_pfn; |
a32073bf | 630 | |
1da177e4 LT |
631 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); |
632 | aper_size = aper_base = info->aper_size = 0; | |
a32073bf AK |
633 | dev = NULL; |
634 | for (i = 0; i < num_k8_northbridges; i++) { | |
635 | dev = k8_northbridges[i]; | |
05fccb0e IM |
636 | new_aper_base = read_aperture(dev, &new_aper_size); |
637 | if (!new_aper_base) | |
638 | goto nommu; | |
639 | ||
640 | if (!aper_base) { | |
1da177e4 LT |
641 | aper_size = new_aper_size; |
642 | aper_base = new_aper_base; | |
05fccb0e IM |
643 | } |
644 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
645 | goto nommu; |
646 | } | |
647 | if (!aper_base) | |
05fccb0e | 648 | goto nommu; |
1da177e4 | 649 | info->aper_base = aper_base; |
05fccb0e | 650 | info->aper_size = aper_size >> 20; |
1da177e4 | 651 | |
05fccb0e IM |
652 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
653 | gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size)); | |
654 | if (!gatt) | |
cf6387da | 655 | panic("Cannot allocate GATT table"); |
6d238cc4 | 656 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 657 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 658 | |
05fccb0e | 659 | memset(gatt, 0, gatt_size); |
1da177e4 | 660 | agp_gatt_table = gatt; |
a32073bf | 661 | |
6703f6d1 | 662 | enable_gart_translations(); |
cd76374e PM |
663 | |
664 | error = sysdev_class_register(&gart_sysdev_class); | |
665 | if (!error) | |
666 | error = sysdev_register(&device_gart); | |
667 | if (error) | |
668 | panic("Could not register gart_sysdev -- would corrupt data on next suspend"); | |
6703f6d1 | 669 | |
a32073bf | 670 | flush_gart(); |
05fccb0e IM |
671 | |
672 | printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n", | |
673 | aper_base, aper_size>>10); | |
7ab073b6 YL |
674 | |
675 | /* need to map that range */ | |
676 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
677 | if (end_pfn > max_low_pfn_mapped) { | |
32b23e9a YL |
678 | start_pfn = (aper_base>>PAGE_SHIFT); |
679 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | |
7ab073b6 | 680 | } |
1da177e4 LT |
681 | return 0; |
682 | ||
683 | nommu: | |
05fccb0e | 684 | /* Should not happen anymore */ |
8f59610d PM |
685 | printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
686 | KERN_WARNING "falling back to iommu=soft.\n"); | |
05fccb0e IM |
687 | return -1; |
688 | } | |
1da177e4 LT |
689 | |
690 | extern int agp_amd64_init(void); | |
691 | ||
8d8bb39b | 692 | static struct dma_mapping_ops gart_dma_ops = { |
05fccb0e IM |
693 | .map_single = gart_map_single, |
694 | .map_simple = gart_map_simple, | |
695 | .unmap_single = gart_unmap_single, | |
696 | .sync_single_for_cpu = NULL, | |
697 | .sync_single_for_device = NULL, | |
698 | .sync_single_range_for_cpu = NULL, | |
699 | .sync_single_range_for_device = NULL, | |
700 | .sync_sg_for_cpu = NULL, | |
701 | .sync_sg_for_device = NULL, | |
702 | .map_sg = gart_map_sg, | |
703 | .unmap_sg = gart_unmap_sg, | |
17a941d8 MBY |
704 | }; |
705 | ||
bc2cea6a YL |
706 | void gart_iommu_shutdown(void) |
707 | { | |
708 | struct pci_dev *dev; | |
709 | int i; | |
710 | ||
711 | if (no_agp && (dma_ops != &gart_dma_ops)) | |
712 | return; | |
713 | ||
05fccb0e IM |
714 | for (i = 0; i < num_k8_northbridges; i++) { |
715 | u32 ctl; | |
bc2cea6a | 716 | |
05fccb0e | 717 | dev = k8_northbridges[i]; |
3bb6fbf9 | 718 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 719 | |
3bb6fbf9 | 720 | ctl &= ~GARTEN; |
bc2cea6a | 721 | |
3bb6fbf9 | 722 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 723 | } |
bc2cea6a YL |
724 | } |
725 | ||
0dc243ae | 726 | void __init gart_iommu_init(void) |
05fccb0e | 727 | { |
1da177e4 | 728 | struct agp_kern_info info; |
1da177e4 | 729 | unsigned long iommu_start; |
05fccb0e | 730 | unsigned long aper_size; |
1da177e4 LT |
731 | unsigned long scratch; |
732 | long i; | |
733 | ||
a32073bf AK |
734 | if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) { |
735 | printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n"); | |
0dc243ae | 736 | return; |
a32073bf AK |
737 | } |
738 | ||
1da177e4 | 739 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 740 | no_agp = 1; |
1da177e4 LT |
741 | #else |
742 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
743 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
744 | no_agp = no_agp || |
745 | (agp_amd64_init() < 0) || | |
1da177e4 | 746 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 747 | #endif |
1da177e4 | 748 | |
60b08c67 | 749 | if (swiotlb) |
0dc243ae | 750 | return; |
60b08c67 | 751 | |
8d4f6b93 | 752 | /* Did we detect a different HW IOMMU? */ |
0440d4c0 | 753 | if (iommu_detected && !gart_iommu_aperture) |
0dc243ae | 754 | return; |
8d4f6b93 | 755 | |
1da177e4 | 756 | if (no_iommu || |
c987d12f | 757 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 758 | !gart_iommu_aperture || |
1da177e4 | 759 | (no_agp && init_k8_gatt(&info) < 0)) { |
c987d12f | 760 | if (max_pfn > MAX_DMA32_PFN) { |
8f59610d PM |
761 | printk(KERN_WARNING "More than 4GB of memory " |
762 | "but GART IOMMU not available.\n" | |
763 | KERN_WARNING "falling back to iommu=soft.\n"); | |
5b7b644c | 764 | } |
0dc243ae | 765 | return; |
1da177e4 LT |
766 | } |
767 | ||
5b7b644c | 768 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
769 | aper_size = info.aper_size * 1024 * 1024; |
770 | iommu_size = check_iommu_size(info.aper_base, aper_size); | |
771 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
772 | ||
773 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL, | |
774 | get_order(iommu_pages/8)); | |
775 | if (!iommu_gart_bitmap) | |
776 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
777 | memset(iommu_gart_bitmap, 0, iommu_pages/8); |
778 | ||
779 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e IM |
780 | if (leak_trace) { |
781 | iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL, | |
1da177e4 | 782 | get_order(iommu_pages*sizeof(void *))); |
05fccb0e IM |
783 | if (iommu_leak_tab) |
784 | memset(iommu_leak_tab, 0, iommu_pages * 8); | |
1da177e4 | 785 | else |
05fccb0e IM |
786 | printk(KERN_DEBUG |
787 | "PCI-DMA: Cannot allocate leak trace area\n"); | |
788 | } | |
1da177e4 LT |
789 | #endif |
790 | ||
05fccb0e | 791 | /* |
1da177e4 | 792 | * Out of IOMMU space handling. |
05fccb0e IM |
793 | * Reserve some invalid pages at the beginning of the GART. |
794 | */ | |
795 | set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES); | |
1da177e4 | 796 | |
05fccb0e | 797 | agp_memory_reserved = iommu_size; |
1da177e4 LT |
798 | printk(KERN_INFO |
799 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
05fccb0e | 800 | iommu_size >> 20); |
1da177e4 | 801 | |
05fccb0e IM |
802 | iommu_start = aper_size - iommu_size; |
803 | iommu_bus_base = info.aper_base + iommu_start; | |
1da177e4 LT |
804 | bad_dma_address = iommu_bus_base; |
805 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
806 | ||
05fccb0e | 807 | /* |
1da177e4 LT |
808 | * Unmap the IOMMU part of the GART. The alias of the page is |
809 | * always mapped with cache enabled and there is no full cache | |
810 | * coherency across the GART remapping. The unmapping avoids | |
811 | * automatic prefetches from the CPU allocating cache lines in | |
812 | * there. All CPU accesses are done via the direct mapping to | |
813 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 814 | * devices. |
1da177e4 | 815 | */ |
28d6ee41 AK |
816 | set_memory_np((unsigned long)__va(iommu_bus_base), |
817 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
818 | /* |
819 | * Tricky. The GART table remaps the physical memory range, | |
820 | * so the CPU wont notice potential aliases and if the memory | |
821 | * is remapped to UC later on, we might surprise the PCI devices | |
822 | * with a stray writeout of a cacheline. So play it sure and | |
823 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
824 | * the pages as Not-Present: | |
825 | */ | |
826 | wbinvd(); | |
1da177e4 | 827 | |
05fccb0e | 828 | /* |
fa3d319a | 829 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 830 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 831 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 832 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 833 | */ |
05fccb0e IM |
834 | scratch = get_zeroed_page(GFP_KERNEL); |
835 | if (!scratch) | |
1da177e4 LT |
836 | panic("Cannot allocate iommu scratch page"); |
837 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 838 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
839 | iommu_gatt_base[i] = gart_unmapped_entry; |
840 | ||
a32073bf | 841 | flush_gart(); |
17a941d8 | 842 | dma_ops = &gart_dma_ops; |
05fccb0e | 843 | } |
1da177e4 | 844 | |
43999d9e | 845 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
846 | { |
847 | int arg; | |
848 | ||
1da177e4 | 849 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 850 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
851 | leak_trace = 1; |
852 | p += 4; | |
853 | if (*p == '=') ++p; | |
854 | if (isdigit(*p) && get_option(&p, &arg)) | |
855 | iommu_leak_pages = arg; | |
856 | } | |
1da177e4 | 857 | #endif |
17a941d8 MBY |
858 | if (isdigit(*p) && get_option(&p, &arg)) |
859 | iommu_size = arg; | |
05fccb0e | 860 | if (!strncmp(p, "fullflush", 8)) |
17a941d8 | 861 | iommu_fullflush = 1; |
05fccb0e | 862 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 863 | iommu_fullflush = 0; |
05fccb0e | 864 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 865 | no_agp = 1; |
05fccb0e | 866 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
867 | fix_aperture = 0; |
868 | /* duplicated from pci-dma.c */ | |
05fccb0e | 869 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 870 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 871 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 872 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
873 | if (!strncmp(p, "memaper", 7)) { |
874 | fallback_aper_force = 1; | |
875 | p += 7; | |
876 | if (*p == '=') { | |
877 | ++p; | |
878 | if (get_option(&p, &arg)) | |
879 | fallback_aper_order = arg; | |
880 | } | |
881 | } | |
882 | } |