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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
162a688e | 12 | #include <linux/tick.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
b253149b | 27 | #include <asm/mwait.h> |
389d1fb1 | 28 | #include <asm/i387.h> |
1361b83a | 29 | #include <asm/fpu-internal.h> |
66cb5917 | 30 | #include <asm/debugreg.h> |
90e24014 | 31 | #include <asm/nmi.h> |
375074cc | 32 | #include <asm/tlbflush.h> |
90e24014 | 33 | |
45046892 TG |
34 | /* |
35 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
36 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
37 | * so they are allowed to end up in the .data..cacheline_aligned | |
38 | * section. Since TSS's are completely CPU-local, we want them | |
39 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
40 | */ | |
d0a0de21 AL |
41 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
42 | .x86_tss = { | |
d9e05cc5 | 43 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
44 | #ifdef CONFIG_X86_32 |
45 | .ss0 = __KERNEL_DS, | |
46 | .ss1 = __KERNEL_CS, | |
47 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
48 | #endif | |
49 | }, | |
50 | #ifdef CONFIG_X86_32 | |
51 | /* | |
52 | * Note that the .io_bitmap member must be extra-big. This is because | |
53 | * the CPU will access an additional byte beyond the end of the IO | |
54 | * permission bitmap. The extra byte must be all 1 bits, and must | |
55 | * be within the limit. | |
56 | */ | |
57 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
58 | #endif | |
59 | }; | |
de71ad2c | 60 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 61 | |
90e24014 RW |
62 | #ifdef CONFIG_X86_64 |
63 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
64 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
65 | ||
66 | void idle_notifier_register(struct notifier_block *n) | |
67 | { | |
68 | atomic_notifier_chain_register(&idle_notifier, n); | |
69 | } | |
70 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
71 | ||
72 | void idle_notifier_unregister(struct notifier_block *n) | |
73 | { | |
74 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
75 | } | |
76 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
77 | #endif | |
c1e3b377 | 78 | |
aa283f49 | 79 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 80 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 81 | |
55ccf3fe SS |
82 | /* |
83 | * this gets called so that we can store lazy state into memory and copy the | |
84 | * current task into the new thread. | |
85 | */ | |
61c4628b SS |
86 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
87 | { | |
88 | *dst = *src; | |
f1853505 | 89 | |
dc56c0f9 | 90 | dst->thread.fpu_counter = 0; |
5e23fee2 | 91 | dst->thread.fpu.has_fpu = 0; |
5e23fee2 | 92 | dst->thread.fpu.state = NULL; |
6a5fe895 | 93 | task_disable_lazy_fpu_restore(dst); |
f1853505 ON |
94 | if (tsk_used_math(src)) { |
95 | int err = fpu_alloc(&dst->thread.fpu); | |
96 | if (err) | |
97 | return err; | |
304bceda | 98 | fpu_copy(dst, src); |
aa283f49 | 99 | } |
61c4628b SS |
100 | return 0; |
101 | } | |
102 | ||
aa283f49 | 103 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 104 | { |
86603283 | 105 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
106 | } |
107 | ||
38e7c572 | 108 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 109 | { |
38e7c572 | 110 | free_thread_xstate(tsk); |
61c4628b SS |
111 | } |
112 | ||
113 | void arch_task_cache_init(void) | |
114 | { | |
115 | task_xstate_cachep = | |
116 | kmem_cache_create("task_xstate", xstate_size, | |
117 | __alignof__(union thread_xstate), | |
2dff4405 | 118 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
7496d645 | 119 | setup_xstate_comp(); |
61c4628b | 120 | } |
7f424a8b | 121 | |
389d1fb1 JF |
122 | /* |
123 | * Free current thread data structures etc.. | |
124 | */ | |
125 | void exit_thread(void) | |
126 | { | |
127 | struct task_struct *me = current; | |
128 | struct thread_struct *t = &me->thread; | |
250981e6 | 129 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 130 | |
250981e6 | 131 | if (bp) { |
24933b82 | 132 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 133 | |
389d1fb1 JF |
134 | t->io_bitmap_ptr = NULL; |
135 | clear_thread_flag(TIF_IO_BITMAP); | |
136 | /* | |
137 | * Careful, clear this in the TSS too: | |
138 | */ | |
139 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
140 | t->io_bitmap_max = 0; | |
141 | put_cpu(); | |
250981e6 | 142 | kfree(bp); |
389d1fb1 | 143 | } |
1dcc8d7b SS |
144 | |
145 | drop_fpu(me); | |
389d1fb1 JF |
146 | } |
147 | ||
148 | void flush_thread(void) | |
149 | { | |
150 | struct task_struct *tsk = current; | |
151 | ||
24f1e32c | 152 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 153 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 154 | |
f893959b ON |
155 | if (!use_eager_fpu()) { |
156 | /* FPU state will be reallocated lazily at the first use. */ | |
157 | drop_fpu(tsk); | |
304bceda | 158 | free_thread_xstate(tsk); |
f893959b | 159 | } else if (!used_math()) { |
110d7f75 | 160 | /* kthread execs. TODO: cleanup this horror. */ |
f893959b ON |
161 | if (WARN_ON(init_fpu(tsk))) |
162 | force_sig(SIGKILL, tsk); | |
9cb6ce82 ON |
163 | user_fpu_begin(); |
164 | restore_init_xstate(); | |
110d7f75 | 165 | } |
389d1fb1 JF |
166 | } |
167 | ||
168 | static void hard_disable_TSC(void) | |
169 | { | |
375074cc | 170 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
171 | } |
172 | ||
173 | void disable_TSC(void) | |
174 | { | |
175 | preempt_disable(); | |
176 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
177 | /* | |
178 | * Must flip the CPU state synchronously with | |
179 | * TIF_NOTSC in the current running context. | |
180 | */ | |
181 | hard_disable_TSC(); | |
182 | preempt_enable(); | |
183 | } | |
184 | ||
185 | static void hard_enable_TSC(void) | |
186 | { | |
375074cc | 187 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
188 | } |
189 | ||
190 | static void enable_TSC(void) | |
191 | { | |
192 | preempt_disable(); | |
193 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
194 | /* | |
195 | * Must flip the CPU state synchronously with | |
196 | * TIF_NOTSC in the current running context. | |
197 | */ | |
198 | hard_enable_TSC(); | |
199 | preempt_enable(); | |
200 | } | |
201 | ||
202 | int get_tsc_mode(unsigned long adr) | |
203 | { | |
204 | unsigned int val; | |
205 | ||
206 | if (test_thread_flag(TIF_NOTSC)) | |
207 | val = PR_TSC_SIGSEGV; | |
208 | else | |
209 | val = PR_TSC_ENABLE; | |
210 | ||
211 | return put_user(val, (unsigned int __user *)adr); | |
212 | } | |
213 | ||
214 | int set_tsc_mode(unsigned int val) | |
215 | { | |
216 | if (val == PR_TSC_SIGSEGV) | |
217 | disable_TSC(); | |
218 | else if (val == PR_TSC_ENABLE) | |
219 | enable_TSC(); | |
220 | else | |
221 | return -EINVAL; | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
227 | struct tss_struct *tss) | |
228 | { | |
229 | struct thread_struct *prev, *next; | |
230 | ||
231 | prev = &prev_p->thread; | |
232 | next = &next_p->thread; | |
233 | ||
ea8e61b7 PZ |
234 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
235 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
236 | unsigned long debugctl = get_debugctlmsr(); | |
237 | ||
238 | debugctl &= ~DEBUGCTLMSR_BTF; | |
239 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
240 | debugctl |= DEBUGCTLMSR_BTF; | |
241 | ||
242 | update_debugctlmsr(debugctl); | |
243 | } | |
389d1fb1 | 244 | |
389d1fb1 JF |
245 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
246 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
247 | /* prev and next are different */ | |
248 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
249 | hard_disable_TSC(); | |
250 | else | |
251 | hard_enable_TSC(); | |
252 | } | |
253 | ||
254 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
255 | /* | |
256 | * Copy the relevant range of the IO bitmap. | |
257 | * Normally this is 128 bytes or less: | |
258 | */ | |
259 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
260 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
261 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
262 | /* | |
263 | * Clear any possible leftover bits: | |
264 | */ | |
265 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
266 | } | |
7c68af6e | 267 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
268 | } |
269 | ||
00dba564 TG |
270 | /* |
271 | * Idle related variables and functions | |
272 | */ | |
d1896049 | 273 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
274 | EXPORT_SYMBOL(boot_option_idle_override); |
275 | ||
a476bda3 | 276 | static void (*x86_idle)(void); |
00dba564 | 277 | |
90e24014 RW |
278 | #ifndef CONFIG_SMP |
279 | static inline void play_dead(void) | |
280 | { | |
281 | BUG(); | |
282 | } | |
283 | #endif | |
284 | ||
285 | #ifdef CONFIG_X86_64 | |
286 | void enter_idle(void) | |
287 | { | |
c6ae41e7 | 288 | this_cpu_write(is_idle, 1); |
90e24014 RW |
289 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
290 | } | |
291 | ||
292 | static void __exit_idle(void) | |
293 | { | |
294 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
295 | return; | |
296 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
297 | } | |
298 | ||
299 | /* Called from interrupts to signify idle end */ | |
300 | void exit_idle(void) | |
301 | { | |
302 | /* idle loop has pid 0 */ | |
303 | if (current->pid) | |
304 | return; | |
305 | __exit_idle(); | |
306 | } | |
307 | #endif | |
308 | ||
7d1a9417 TG |
309 | void arch_cpu_idle_enter(void) |
310 | { | |
311 | local_touch_nmi(); | |
312 | enter_idle(); | |
313 | } | |
90e24014 | 314 | |
7d1a9417 TG |
315 | void arch_cpu_idle_exit(void) |
316 | { | |
317 | __exit_idle(); | |
318 | } | |
90e24014 | 319 | |
7d1a9417 TG |
320 | void arch_cpu_idle_dead(void) |
321 | { | |
322 | play_dead(); | |
323 | } | |
90e24014 | 324 | |
7d1a9417 TG |
325 | /* |
326 | * Called from the generic idle code. | |
327 | */ | |
328 | void arch_cpu_idle(void) | |
329 | { | |
16f8b05a | 330 | x86_idle(); |
90e24014 RW |
331 | } |
332 | ||
00dba564 | 333 | /* |
7d1a9417 | 334 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
335 | */ |
336 | void default_idle(void) | |
337 | { | |
4d0e42cc | 338 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 339 | safe_halt(); |
4d0e42cc | 340 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 341 | } |
60b8b1de | 342 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
343 | EXPORT_SYMBOL(default_idle); |
344 | #endif | |
345 | ||
6a377ddc LB |
346 | #ifdef CONFIG_XEN |
347 | bool xen_set_default_idle(void) | |
e5fd47bf | 348 | { |
a476bda3 | 349 | bool ret = !!x86_idle; |
e5fd47bf | 350 | |
a476bda3 | 351 | x86_idle = default_idle; |
e5fd47bf KRW |
352 | |
353 | return ret; | |
354 | } | |
6a377ddc | 355 | #endif |
d3ec5cae IV |
356 | void stop_this_cpu(void *dummy) |
357 | { | |
358 | local_irq_disable(); | |
359 | /* | |
360 | * Remove this CPU: | |
361 | */ | |
4f062896 | 362 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
363 | disable_local_APIC(); |
364 | ||
27be4570 LB |
365 | for (;;) |
366 | halt(); | |
7f424a8b PZ |
367 | } |
368 | ||
02c68a02 LB |
369 | bool amd_e400_c1e_detected; |
370 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 371 | |
02c68a02 | 372 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 373 | |
02c68a02 | 374 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 375 | { |
02c68a02 LB |
376 | if (amd_e400_c1e_mask != NULL) |
377 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
378 | } |
379 | ||
aa276e1c | 380 | /* |
02c68a02 | 381 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
382 | * pending message MSR. If we detect C1E, then we handle it the same |
383 | * way as C3 power states (local apic timer and TSC stop) | |
384 | */ | |
02c68a02 | 385 | static void amd_e400_idle(void) |
aa276e1c | 386 | { |
02c68a02 | 387 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
388 | u32 lo, hi; |
389 | ||
390 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 391 | |
aa276e1c | 392 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 393 | amd_e400_c1e_detected = true; |
40fb1715 | 394 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 395 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 396 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
397 | } |
398 | } | |
399 | ||
02c68a02 | 400 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
401 | int cpu = smp_processor_id(); |
402 | ||
02c68a02 LB |
403 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
404 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
162a688e TG |
405 | /* Force broadcast so ACPI can not interfere. */ |
406 | tick_broadcast_force(); | |
c767a54b | 407 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c | 408 | } |
435c350e | 409 | tick_broadcast_enter(); |
0beefa20 | 410 | |
aa276e1c | 411 | default_idle(); |
0beefa20 TG |
412 | |
413 | /* | |
414 | * The switch back from broadcast mode needs to be | |
415 | * called with interrupts disabled. | |
416 | */ | |
ea811747 | 417 | local_irq_disable(); |
435c350e | 418 | tick_broadcast_exit(); |
ea811747 | 419 | local_irq_enable(); |
aa276e1c TG |
420 | } else |
421 | default_idle(); | |
422 | } | |
423 | ||
b253149b LB |
424 | /* |
425 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
426 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
427 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
428 | * | |
429 | * Some AMD machines are the opposite, they depend on using HALT. | |
430 | * | |
431 | * So for default C1, which is used during boot until cpuidle loads, | |
432 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
433 | */ | |
434 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
435 | { | |
436 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
437 | return 0; | |
438 | ||
439 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
440 | return 0; | |
441 | ||
442 | return 1; | |
443 | } | |
444 | ||
445 | /* | |
446 | * MONITOR/MWAIT with no hints, used for default default C1 state. | |
447 | * This invokes MWAIT with interrutps enabled and no flags, | |
448 | * which is backwards compatible with the original MWAIT implementation. | |
449 | */ | |
450 | ||
451 | static void mwait_idle(void) | |
452 | { | |
f8e617f4 MG |
453 | if (!current_set_polling_and_test()) { |
454 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
455 | smp_mb(); /* quirk */ | |
b253149b | 456 | clflush((void *)¤t_thread_info()->flags); |
f8e617f4 MG |
457 | smp_mb(); /* quirk */ |
458 | } | |
b253149b LB |
459 | |
460 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
461 | if (!need_resched()) |
462 | __sti_mwait(0, 0); | |
463 | else | |
464 | local_irq_enable(); | |
f8e617f4 | 465 | } else { |
b253149b | 466 | local_irq_enable(); |
f8e617f4 MG |
467 | } |
468 | __current_clr_polling(); | |
b253149b LB |
469 | } |
470 | ||
148f9bb8 | 471 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 472 | { |
3e5095d1 | 473 | #ifdef CONFIG_SMP |
7d1a9417 | 474 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 475 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 476 | #endif |
7d1a9417 | 477 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
478 | return; |
479 | ||
7d7dc116 | 480 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 481 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 482 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 483 | x86_idle = amd_e400_idle; |
b253149b LB |
484 | } else if (prefer_mwait_c1_over_halt(c)) { |
485 | pr_info("using mwait in idle threads\n"); | |
486 | x86_idle = mwait_idle; | |
6ddd2a27 | 487 | } else |
a476bda3 | 488 | x86_idle = default_idle; |
7f424a8b PZ |
489 | } |
490 | ||
02c68a02 | 491 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 492 | { |
02c68a02 | 493 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 494 | if (x86_idle == amd_e400_idle) |
02c68a02 | 495 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
496 | } |
497 | ||
7f424a8b PZ |
498 | static int __init idle_setup(char *str) |
499 | { | |
ab6bc3e3 CG |
500 | if (!str) |
501 | return -EINVAL; | |
502 | ||
7f424a8b | 503 | if (!strcmp(str, "poll")) { |
c767a54b | 504 | pr_info("using polling idle threads\n"); |
d1896049 | 505 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 506 | cpu_idle_poll_ctrl(true); |
d1896049 | 507 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
508 | /* |
509 | * When the boot option of idle=halt is added, halt is | |
510 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
511 | * won't be used again. | |
512 | * To continue to load the CPU idle driver, don't touch | |
513 | * the boot_option_idle_override. | |
514 | */ | |
a476bda3 | 515 | x86_idle = default_idle; |
d1896049 | 516 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
517 | } else if (!strcmp(str, "nomwait")) { |
518 | /* | |
519 | * If the boot option of "idle=nomwait" is added, | |
520 | * it means that mwait will be disabled for CPU C2/C3 | |
521 | * states. In such case it won't touch the variable | |
522 | * of boot_option_idle_override. | |
523 | */ | |
d1896049 | 524 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 525 | } else |
7f424a8b PZ |
526 | return -1; |
527 | ||
7f424a8b PZ |
528 | return 0; |
529 | } | |
530 | early_param("idle", idle_setup); | |
531 | ||
9d62dcdf AW |
532 | unsigned long arch_align_stack(unsigned long sp) |
533 | { | |
534 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
535 | sp -= get_random_int() % 8192; | |
536 | return sp & ~0xf; | |
537 | } | |
538 | ||
539 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
540 | { | |
541 | unsigned long range_end = mm->brk + 0x02000000; | |
542 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
543 | } | |
544 |