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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1995 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
6 | */ | |
7 | ||
8 | /* | |
9 | * This file handles the architecture-dependent parts of process handling.. | |
10 | */ | |
11 | ||
f3705136 | 12 | #include <linux/cpu.h> |
1da177e4 LT |
13 | #include <linux/errno.h> |
14 | #include <linux/sched.h> | |
29930025 | 15 | #include <linux/sched/task.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
1da177e4 LT |
17 | #include <linux/fs.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/elfcore.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/stddef.h> |
23 | #include <linux/slab.h> | |
24 | #include <linux/vmalloc.h> | |
25 | #include <linux/user.h> | |
1da177e4 | 26 | #include <linux/interrupt.h> |
1da177e4 LT |
27 | #include <linux/delay.h> |
28 | #include <linux/reboot.h> | |
1da177e4 | 29 | #include <linux/mc146818rtc.h> |
186f4360 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/kallsyms.h> |
32 | #include <linux/ptrace.h> | |
c16b63e0 | 33 | #include <linux/personality.h> |
7c3576d2 | 34 | #include <linux/percpu.h> |
529e25f6 | 35 | #include <linux/prctl.h> |
8b96f011 | 36 | #include <linux/ftrace.h> |
befa9e78 JSR |
37 | #include <linux/uaccess.h> |
38 | #include <linux/io.h> | |
39 | #include <linux/kdebug.h> | |
79170fda | 40 | #include <linux/syscalls.h> |
1da177e4 | 41 | |
1da177e4 LT |
42 | #include <asm/ldt.h> |
43 | #include <asm/processor.h> | |
ce78f596 | 44 | #include <asm/fpu/sched.h> |
1da177e4 | 45 | #include <asm/desc.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | #include <linux/err.h> |
48 | ||
f3705136 ZM |
49 | #include <asm/tlbflush.h> |
50 | #include <asm/cpu.h> | |
66cb5917 | 51 | #include <asm/debugreg.h> |
f05e798a | 52 | #include <asm/switch_to.h> |
ba3e127e | 53 | #include <asm/vm86.h> |
8dd97c65 | 54 | #include <asm/resctrl.h> |
79170fda | 55 | #include <asm/proto.h> |
f3705136 | 56 | |
ff16701a TG |
57 | #include "process.h" |
58 | ||
44e21535 DS |
59 | void __show_regs(struct pt_regs *regs, enum show_regs_mode mode, |
60 | const char *log_lvl) | |
1da177e4 LT |
61 | { |
62 | unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; | |
bb1995d5 | 63 | unsigned long d0, d1, d2, d3, d6, d7; |
3c88c692 | 64 | unsigned short gs; |
9d975ebd | 65 | |
3c88c692 | 66 | if (user_mode(regs)) |
d9a89a26 | 67 | gs = get_user_gs(regs); |
3c88c692 | 68 | else |
9d975ebd | 69 | savesegment(gs, gs); |
1da177e4 | 70 | |
44e21535 | 71 | show_ip(regs, log_lvl); |
1da177e4 | 72 | |
44e21535 DS |
73 | printk("%sEAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", |
74 | log_lvl, regs->ax, regs->bx, regs->cx, regs->dx); | |
75 | printk("%sESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", | |
76 | log_lvl, regs->si, regs->di, regs->bp, regs->sp); | |
77 | printk("%sDS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n", | |
78 | log_lvl, (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, regs->ss, regs->flags); | |
9d975ebd | 79 | |
9fe6299d | 80 | if (mode != SHOW_REGS_ALL) |
9d975ebd | 81 | return; |
1da177e4 | 82 | |
4bb0d3ec ZA |
83 | cr0 = read_cr0(); |
84 | cr2 = read_cr2(); | |
6c690ee1 | 85 | cr3 = __read_cr3(); |
1ef55be1 | 86 | cr4 = __read_cr4(); |
44e21535 DS |
87 | printk("%sCR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", |
88 | log_lvl, cr0, cr2, cr3, cr4); | |
bb1995d5 AS |
89 | |
90 | get_debugreg(d0, 0); | |
91 | get_debugreg(d1, 1); | |
92 | get_debugreg(d2, 2); | |
93 | get_debugreg(d3, 3); | |
bb1995d5 AS |
94 | get_debugreg(d6, 6); |
95 | get_debugreg(d7, 7); | |
4338774c DJ |
96 | |
97 | /* Only print out debug registers if they are in their non-default state. */ | |
98 | if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && | |
99 | (d6 == DR6_RESERVED) && (d7 == 0x400)) | |
100 | return; | |
101 | ||
44e21535 DS |
102 | printk("%sDR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n", |
103 | log_lvl, d0, d1, d2, d3); | |
104 | printk("%sDR6: %08lx DR7: %08lx\n", | |
105 | log_lvl, d6, d7); | |
9d975ebd | 106 | } |
bb1995d5 | 107 | |
1da177e4 LT |
108 | void release_thread(struct task_struct *dead_task) |
109 | { | |
2684927c | 110 | BUG_ON(dead_task->mm); |
1da177e4 LT |
111 | release_vm86_irqs(dead_task); |
112 | } | |
113 | ||
513ad84b IM |
114 | void |
115 | start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) | |
116 | { | |
d9a89a26 | 117 | set_user_gs(regs, 0); |
513ad84b | 118 | regs->fs = 0; |
513ad84b IM |
119 | regs->ds = __USER_DS; |
120 | regs->es = __USER_DS; | |
121 | regs->ss = __USER_DS; | |
122 | regs->cs = __USER_CS; | |
123 | regs->ip = new_ip; | |
124 | regs->sp = new_sp; | |
6783eaa2 | 125 | regs->flags = X86_EFLAGS_IF; |
513ad84b IM |
126 | } |
127 | EXPORT_SYMBOL_GPL(start_thread); | |
128 | ||
1da177e4 LT |
129 | |
130 | /* | |
ea70ef3d | 131 | * switch_to(x,y) should switch tasks from x to y. |
1da177e4 LT |
132 | * |
133 | * We fsave/fwait so that an exception goes off at the right time | |
134 | * (as a call from the fsave or fwait in effect) rather than to | |
135 | * the wrong process. Lazy FP saving no longer makes any sense | |
136 | * with modern CPU's, and this simplifies a lot of things (SMP | |
137 | * and UP become the same). | |
138 | * | |
139 | * NOTE! We used to use the x86 hardware context switching. The | |
140 | * reason for not using it any more becomes apparent when you | |
141 | * try to recover gracefully from saved state that is no longer | |
142 | * valid (stale segment register values in particular). With the | |
143 | * hardware task-switch, there is no way to fix up bad state in | |
144 | * a reasonable manner. | |
145 | * | |
146 | * The fact that Intel documents the hardware task-switching to | |
147 | * be slow is a fairly red herring - this code is not noticeably | |
148 | * faster. However, there _is_ some room for improvement here, | |
149 | * so the performance issues may eventually be a valid point. | |
150 | * More important, however, is the fact that this allows us much | |
151 | * more flexibility. | |
152 | * | |
65ea5b03 | 153 | * The return value (in %ax) will be the "prev" task after |
1da177e4 LT |
154 | * the task-switch, and shows up in ret_from_fork in entry.S, |
155 | * for example. | |
156 | */ | |
35ea7903 | 157 | __visible __notrace_funcgraph struct task_struct * |
8b96f011 | 158 | __switch_to(struct task_struct *prev_p, struct task_struct *next_p) |
1da177e4 LT |
159 | { |
160 | struct thread_struct *prev = &prev_p->thread, | |
384a23f9 IM |
161 | *next = &next_p->thread; |
162 | struct fpu *prev_fpu = &prev->fpu; | |
1da177e4 | 163 | int cpu = smp_processor_id(); |
1da177e4 LT |
164 | |
165 | /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */ | |
166 | ||
5f409e20 RR |
167 | if (!test_thread_flag(TIF_NEED_FPU_LOAD)) |
168 | switch_fpu_prepare(prev_fpu, cpu); | |
acc20761 | 169 | |
1da177e4 | 170 | /* |
464d1a78 | 171 | * Save away %gs. No need to save %fs, as it was saved on the |
f95d47ca JF |
172 | * stack on entry. No need to save %es and %ds, as those are |
173 | * always kernel segments while inside the kernel. Doing this | |
174 | * before setting the new TLS descriptors avoids the situation | |
175 | * where we temporarily have non-reloadable segments in %fs | |
176 | * and %gs. This could be an issue if the NMI handler ever | |
177 | * used %fs or %gs (it does not today), or if the kernel is | |
178 | * running inside of a hypervisor layer. | |
1da177e4 | 179 | */ |
ccbeed3a | 180 | lazy_save_gs(prev->gs); |
1da177e4 LT |
181 | |
182 | /* | |
e7a2ff59 | 183 | * Load the per-thread Thread-Local Storage descriptor. |
1da177e4 | 184 | */ |
e7a2ff59 | 185 | load_TLS(next, cpu); |
1da177e4 | 186 | |
ff16701a | 187 | switch_to_extra(prev_p, next_p); |
ffaa8bd6 | 188 | |
9226d125 ZA |
189 | /* |
190 | * Leave lazy mode, flushing any hypercalls made here. | |
191 | * This must be done before restoring TLS segments so | |
6dd677a0 | 192 | * the GDT and LDT are properly updated. |
9226d125 | 193 | */ |
224101ed | 194 | arch_end_context_switch(next_p); |
9226d125 | 195 | |
b27559a4 | 196 | /* |
fed7c3f0 | 197 | * Reload esp0 and cpu_current_top_of_stack. This changes |
bd7dc5a6 AL |
198 | * current_thread_info(). Refresh the SYSENTER configuration in |
199 | * case prev or next is vm86. | |
b27559a4 | 200 | */ |
252e1a05 | 201 | update_task_stack(next_p); |
bd7dc5a6 | 202 | refresh_sysenter_cs(next); |
a7fcf28d AL |
203 | this_cpu_write(cpu_current_top_of_stack, |
204 | (unsigned long)task_stack_page(next_p) + | |
205 | THREAD_SIZE); | |
198d208d | 206 | |
9226d125 ZA |
207 | /* |
208 | * Restore %gs if needed (which is common) | |
209 | */ | |
210 | if (prev->gs | next->gs) | |
ccbeed3a | 211 | lazy_load_gs(next->gs); |
9226d125 | 212 | |
c6ae41e7 | 213 | this_cpu_write(current_task, next_p); |
9226d125 | 214 | |
71ad92ec | 215 | switch_fpu_finish(); |
2722146e | 216 | |
4f341a5e | 217 | /* Load the Intel cache allocation PQR MSR. */ |
352940ec | 218 | resctrl_sched_in(); |
4f341a5e | 219 | |
1da177e4 LT |
220 | return prev_p; |
221 | } | |
79170fda KH |
222 | |
223 | SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2) | |
224 | { | |
225 | return do_arch_prctl_common(current, option, arg2); | |
226 | } |