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1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
f3705136 12#include <linux/cpu.h>
1da177e4
LT
13#include <linux/errno.h>
14#include <linux/sched.h>
29930025 15#include <linux/sched/task.h>
1da177e4
LT
16#include <linux/fs.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/elfcore.h>
20#include <linux/smp.h>
1da177e4
LT
21#include <linux/stddef.h>
22#include <linux/slab.h>
23#include <linux/vmalloc.h>
24#include <linux/user.h>
1da177e4 25#include <linux/interrupt.h>
1da177e4
LT
26#include <linux/delay.h>
27#include <linux/reboot.h>
1da177e4 28#include <linux/mc146818rtc.h>
186f4360 29#include <linux/export.h>
1da177e4
LT
30#include <linux/kallsyms.h>
31#include <linux/ptrace.h>
c16b63e0 32#include <linux/personality.h>
7c3576d2 33#include <linux/percpu.h>
529e25f6 34#include <linux/prctl.h>
8b96f011 35#include <linux/ftrace.h>
befa9e78
JSR
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/kdebug.h>
1da177e4 39
1da177e4 40#include <asm/pgtable.h>
1da177e4
LT
41#include <asm/ldt.h>
42#include <asm/processor.h>
78f7f1e5 43#include <asm/fpu/internal.h>
1da177e4
LT
44#include <asm/desc.h>
45#ifdef CONFIG_MATH_EMULATION
46#include <asm/math_emu.h>
47#endif
48
1da177e4
LT
49#include <linux/err.h>
50
f3705136
ZM
51#include <asm/tlbflush.h>
52#include <asm/cpu.h>
bbc1f698 53#include <asm/syscalls.h>
66cb5917 54#include <asm/debugreg.h>
f05e798a 55#include <asm/switch_to.h>
ba3e127e 56#include <asm/vm86.h>
4f341a5e 57#include <asm/intel_rdt.h>
f3705136 58
e2ce07c8 59void __show_regs(struct pt_regs *regs, int all)
1da177e4
LT
60{
61 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
bb1995d5 62 unsigned long d0, d1, d2, d3, d6, d7;
65ea5b03 63 unsigned long sp;
9d975ebd
PE
64 unsigned short ss, gs;
65
f39b6f0e 66 if (user_mode(regs)) {
65ea5b03
PA
67 sp = regs->sp;
68 ss = regs->ss & 0xffff;
d9a89a26 69 gs = get_user_gs(regs);
9d975ebd 70 } else {
def3c5d0 71 sp = kernel_stack_pointer(regs);
9d975ebd
PE
72 savesegment(ss, ss);
73 savesegment(gs, gs);
74 }
1da177e4 75
bb5e5ce5
JP
76 printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
77 printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
78 smp_processor_id());
1da177e4 79
d015a092 80 printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
65ea5b03 81 regs->ax, regs->bx, regs->cx, regs->dx);
d015a092 82 printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
65ea5b03 83 regs->si, regs->di, regs->bp, sp);
d015a092 84 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
92bc2056 85 (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
9d975ebd
PE
86
87 if (!all)
88 return;
1da177e4 89
4bb0d3ec
ZA
90 cr0 = read_cr0();
91 cr2 = read_cr2();
92 cr3 = read_cr3();
1ef55be1 93 cr4 = __read_cr4();
d015a092 94 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
9d975ebd 95 cr0, cr2, cr3, cr4);
bb1995d5
AS
96
97 get_debugreg(d0, 0);
98 get_debugreg(d1, 1);
99 get_debugreg(d2, 2);
100 get_debugreg(d3, 3);
bb1995d5
AS
101 get_debugreg(d6, 6);
102 get_debugreg(d7, 7);
4338774c
DJ
103
104 /* Only print out debug registers if they are in their non-default state. */
105 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
106 (d6 == DR6_RESERVED) && (d7 == 0x400))
107 return;
108
109 printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
110 d0, d1, d2, d3);
d015a092 111 printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
9d975ebd
PE
112 d6, d7);
113}
bb1995d5 114
1da177e4
LT
115void release_thread(struct task_struct *dead_task)
116{
2684927c 117 BUG_ON(dead_task->mm);
1da177e4
LT
118 release_vm86_irqs(dead_task);
119}
120
c1bd55f9
JT
121int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
122 unsigned long arg, struct task_struct *p, unsigned long tls)
1da177e4 123{
7076aada 124 struct pt_regs *childregs = task_pt_regs(p);
0100301b
BG
125 struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
126 struct inactive_task_frame *frame = &fork_frame->frame;
1da177e4
LT
127 struct task_struct *tsk;
128 int err;
129
0100301b 130 frame->bp = 0;
616d2483 131 frame->ret_addr = (unsigned long) ret_from_fork;
0100301b 132 p->thread.sp = (unsigned long) fork_frame;
7076aada 133 p->thread.sp0 = (unsigned long) (childregs+1);
6f46b3ae 134 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
7076aada 135
1d4b4b29 136 if (unlikely(p->flags & PF_KTHREAD)) {
7076aada
AV
137 /* kernel thread */
138 memset(childregs, 0, sizeof(struct pt_regs));
616d2483
BG
139 frame->bx = sp; /* function */
140 frame->di = arg;
7076aada 141 p->thread.io_bitmap_ptr = NULL;
7076aada
AV
142 return 0;
143 }
616d2483 144 frame->bx = 0;
1d4b4b29 145 *childregs = *current_pt_regs();
65ea5b03 146 childregs->ax = 0;
1d4b4b29
AV
147 if (sp)
148 childregs->sp = sp;
f48d9663 149
1d4b4b29 150 task_user_gs(p) = get_user_gs(current_pt_regs());
1da177e4 151
66cb5917 152 p->thread.io_bitmap_ptr = NULL;
1da177e4 153 tsk = current;
66cb5917 154 err = -ENOMEM;
24f1e32c 155
b3cf2576 156 if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
52978be6
AD
157 p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
158 IO_BITMAP_BYTES, GFP_KERNEL);
1da177e4
LT
159 if (!p->thread.io_bitmap_ptr) {
160 p->thread.io_bitmap_max = 0;
161 return -ENOMEM;
162 }
b3cf2576 163 set_tsk_thread_flag(p, TIF_IO_BITMAP);
1da177e4
LT
164 }
165
efd1ca52
RM
166 err = 0;
167
1da177e4
LT
168 /*
169 * Set a new TLS for the child thread?
170 */
efd1ca52
RM
171 if (clone_flags & CLONE_SETTLS)
172 err = do_set_thread_area(p, -1,
c1bd55f9 173 (struct user_desc __user *)tls, 0);
1da177e4 174
1da177e4
LT
175 if (err && p->thread.io_bitmap_ptr) {
176 kfree(p->thread.io_bitmap_ptr);
177 p->thread.io_bitmap_max = 0;
178 }
179 return err;
180}
181
513ad84b
IM
182void
183start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
184{
d9a89a26 185 set_user_gs(regs, 0);
513ad84b 186 regs->fs = 0;
513ad84b
IM
187 regs->ds = __USER_DS;
188 regs->es = __USER_DS;
189 regs->ss = __USER_DS;
190 regs->cs = __USER_CS;
191 regs->ip = new_ip;
192 regs->sp = new_sp;
6783eaa2 193 regs->flags = X86_EFLAGS_IF;
1daeaa31 194 force_iret();
513ad84b
IM
195}
196EXPORT_SYMBOL_GPL(start_thread);
197
1da177e4
LT
198
199/*
ea70ef3d 200 * switch_to(x,y) should switch tasks from x to y.
1da177e4
LT
201 *
202 * We fsave/fwait so that an exception goes off at the right time
203 * (as a call from the fsave or fwait in effect) rather than to
204 * the wrong process. Lazy FP saving no longer makes any sense
205 * with modern CPU's, and this simplifies a lot of things (SMP
206 * and UP become the same).
207 *
208 * NOTE! We used to use the x86 hardware context switching. The
209 * reason for not using it any more becomes apparent when you
210 * try to recover gracefully from saved state that is no longer
211 * valid (stale segment register values in particular). With the
212 * hardware task-switch, there is no way to fix up bad state in
213 * a reasonable manner.
214 *
215 * The fact that Intel documents the hardware task-switching to
216 * be slow is a fairly red herring - this code is not noticeably
217 * faster. However, there _is_ some room for improvement here,
218 * so the performance issues may eventually be a valid point.
219 * More important, however, is the fact that this allows us much
220 * more flexibility.
221 *
65ea5b03 222 * The return value (in %ax) will be the "prev" task after
1da177e4
LT
223 * the task-switch, and shows up in ret_from_fork in entry.S,
224 * for example.
225 */
35ea7903 226__visible __notrace_funcgraph struct task_struct *
8b96f011 227__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
1da177e4
LT
228{
229 struct thread_struct *prev = &prev_p->thread,
384a23f9
IM
230 *next = &next_p->thread;
231 struct fpu *prev_fpu = &prev->fpu;
232 struct fpu *next_fpu = &next->fpu;
1da177e4 233 int cpu = smp_processor_id();
24933b82 234 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
1da177e4
LT
235
236 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
237
c474e507 238 switch_fpu_prepare(prev_fpu, cpu);
acc20761 239
1da177e4 240 /*
464d1a78 241 * Save away %gs. No need to save %fs, as it was saved on the
f95d47ca
JF
242 * stack on entry. No need to save %es and %ds, as those are
243 * always kernel segments while inside the kernel. Doing this
244 * before setting the new TLS descriptors avoids the situation
245 * where we temporarily have non-reloadable segments in %fs
246 * and %gs. This could be an issue if the NMI handler ever
247 * used %fs or %gs (it does not today), or if the kernel is
248 * running inside of a hypervisor layer.
1da177e4 249 */
ccbeed3a 250 lazy_save_gs(prev->gs);
1da177e4
LT
251
252 /*
e7a2ff59 253 * Load the per-thread Thread-Local Storage descriptor.
1da177e4 254 */
e7a2ff59 255 load_TLS(next, cpu);
1da177e4 256
8b151144
ZA
257 /*
258 * Restore IOPL if needed. In normal use, the flags restore
259 * in the switch assembly will handle this. But if the kernel
260 * is running virtualized at a non-zero CPL, the popf will
261 * not restore flags, so it must be done in a separate step.
262 */
263 if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
264 set_iopl_mask(next->iopl);
265
1da177e4 266 /*
b3cf2576 267 * Now maybe handle debug registers and/or IO bitmaps
1da177e4 268 */
cf99abac
AA
269 if (unlikely(task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV ||
270 task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT))
271 __switch_to_xtra(prev_p, next_p, tss);
ffaa8bd6 272
9226d125
ZA
273 /*
274 * Leave lazy mode, flushing any hypercalls made here.
275 * This must be done before restoring TLS segments so
276 * the GDT and LDT are properly updated, and must be
3a0aee48 277 * done before fpu__restore(), so the TS bit is up
9226d125
ZA
278 * to date.
279 */
224101ed 280 arch_end_context_switch(next_p);
9226d125 281
b27559a4 282 /*
fed7c3f0 283 * Reload esp0 and cpu_current_top_of_stack. This changes
a7fcf28d 284 * current_thread_info().
b27559a4
AL
285 */
286 load_sp0(tss, next);
a7fcf28d
AL
287 this_cpu_write(cpu_current_top_of_stack,
288 (unsigned long)task_stack_page(next_p) +
289 THREAD_SIZE);
198d208d 290
9226d125
ZA
291 /*
292 * Restore %gs if needed (which is common)
293 */
294 if (prev->gs | next->gs)
ccbeed3a 295 lazy_load_gs(next->gs);
9226d125 296
c474e507 297 switch_fpu_finish(next_fpu, cpu);
34ddc81a 298
c6ae41e7 299 this_cpu_write(current_task, next_p);
9226d125 300
4f341a5e
FY
301 /* Load the Intel cache allocation PQR MSR. */
302 intel_rdt_sched_in();
303
1da177e4
LT
304 return prev_p;
305}