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1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
f3705136 12#include <linux/cpu.h>
1da177e4
LT
13#include <linux/errno.h>
14#include <linux/sched.h>
29930025 15#include <linux/sched/task.h>
68db0cf1 16#include <linux/sched/task_stack.h>
1da177e4
LT
17#include <linux/fs.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/elfcore.h>
21#include <linux/smp.h>
1da177e4
LT
22#include <linux/stddef.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/user.h>
1da177e4 26#include <linux/interrupt.h>
1da177e4
LT
27#include <linux/delay.h>
28#include <linux/reboot.h>
1da177e4 29#include <linux/mc146818rtc.h>
186f4360 30#include <linux/export.h>
1da177e4
LT
31#include <linux/kallsyms.h>
32#include <linux/ptrace.h>
c16b63e0 33#include <linux/personality.h>
7c3576d2 34#include <linux/percpu.h>
529e25f6 35#include <linux/prctl.h>
8b96f011 36#include <linux/ftrace.h>
befa9e78
JSR
37#include <linux/uaccess.h>
38#include <linux/io.h>
39#include <linux/kdebug.h>
1da177e4 40
1da177e4 41#include <asm/pgtable.h>
1da177e4
LT
42#include <asm/ldt.h>
43#include <asm/processor.h>
78f7f1e5 44#include <asm/fpu/internal.h>
1da177e4
LT
45#include <asm/desc.h>
46#ifdef CONFIG_MATH_EMULATION
47#include <asm/math_emu.h>
48#endif
49
1da177e4
LT
50#include <linux/err.h>
51
f3705136
ZM
52#include <asm/tlbflush.h>
53#include <asm/cpu.h>
bbc1f698 54#include <asm/syscalls.h>
66cb5917 55#include <asm/debugreg.h>
f05e798a 56#include <asm/switch_to.h>
ba3e127e 57#include <asm/vm86.h>
4f341a5e 58#include <asm/intel_rdt.h>
f3705136 59
e2ce07c8 60void __show_regs(struct pt_regs *regs, int all)
1da177e4
LT
61{
62 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
bb1995d5 63 unsigned long d0, d1, d2, d3, d6, d7;
65ea5b03 64 unsigned long sp;
9d975ebd
PE
65 unsigned short ss, gs;
66
f39b6f0e 67 if (user_mode(regs)) {
65ea5b03
PA
68 sp = regs->sp;
69 ss = regs->ss & 0xffff;
d9a89a26 70 gs = get_user_gs(regs);
9d975ebd 71 } else {
def3c5d0 72 sp = kernel_stack_pointer(regs);
9d975ebd
PE
73 savesegment(ss, ss);
74 savesegment(gs, gs);
75 }
1da177e4 76
bb5e5ce5
JP
77 printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
78 printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
79 smp_processor_id());
1da177e4 80
d015a092 81 printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
65ea5b03 82 regs->ax, regs->bx, regs->cx, regs->dx);
d015a092 83 printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
65ea5b03 84 regs->si, regs->di, regs->bp, sp);
d015a092 85 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
92bc2056 86 (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
9d975ebd
PE
87
88 if (!all)
89 return;
1da177e4 90
4bb0d3ec
ZA
91 cr0 = read_cr0();
92 cr2 = read_cr2();
93 cr3 = read_cr3();
1ef55be1 94 cr4 = __read_cr4();
d015a092 95 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
9d975ebd 96 cr0, cr2, cr3, cr4);
bb1995d5
AS
97
98 get_debugreg(d0, 0);
99 get_debugreg(d1, 1);
100 get_debugreg(d2, 2);
101 get_debugreg(d3, 3);
bb1995d5
AS
102 get_debugreg(d6, 6);
103 get_debugreg(d7, 7);
4338774c
DJ
104
105 /* Only print out debug registers if they are in their non-default state. */
106 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
107 (d6 == DR6_RESERVED) && (d7 == 0x400))
108 return;
109
110 printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
111 d0, d1, d2, d3);
d015a092 112 printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
9d975ebd
PE
113 d6, d7);
114}
bb1995d5 115
1da177e4
LT
116void release_thread(struct task_struct *dead_task)
117{
2684927c 118 BUG_ON(dead_task->mm);
1da177e4
LT
119 release_vm86_irqs(dead_task);
120}
121
c1bd55f9
JT
122int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
123 unsigned long arg, struct task_struct *p, unsigned long tls)
1da177e4 124{
7076aada 125 struct pt_regs *childregs = task_pt_regs(p);
0100301b
BG
126 struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
127 struct inactive_task_frame *frame = &fork_frame->frame;
1da177e4
LT
128 struct task_struct *tsk;
129 int err;
130
0100301b 131 frame->bp = 0;
616d2483 132 frame->ret_addr = (unsigned long) ret_from_fork;
0100301b 133 p->thread.sp = (unsigned long) fork_frame;
7076aada 134 p->thread.sp0 = (unsigned long) (childregs+1);
6f46b3ae 135 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
7076aada 136
1d4b4b29 137 if (unlikely(p->flags & PF_KTHREAD)) {
7076aada
AV
138 /* kernel thread */
139 memset(childregs, 0, sizeof(struct pt_regs));
616d2483
BG
140 frame->bx = sp; /* function */
141 frame->di = arg;
7076aada 142 p->thread.io_bitmap_ptr = NULL;
7076aada
AV
143 return 0;
144 }
616d2483 145 frame->bx = 0;
1d4b4b29 146 *childregs = *current_pt_regs();
65ea5b03 147 childregs->ax = 0;
1d4b4b29
AV
148 if (sp)
149 childregs->sp = sp;
f48d9663 150
1d4b4b29 151 task_user_gs(p) = get_user_gs(current_pt_regs());
1da177e4 152
66cb5917 153 p->thread.io_bitmap_ptr = NULL;
1da177e4 154 tsk = current;
66cb5917 155 err = -ENOMEM;
24f1e32c 156
b3cf2576 157 if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
52978be6
AD
158 p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
159 IO_BITMAP_BYTES, GFP_KERNEL);
1da177e4
LT
160 if (!p->thread.io_bitmap_ptr) {
161 p->thread.io_bitmap_max = 0;
162 return -ENOMEM;
163 }
b3cf2576 164 set_tsk_thread_flag(p, TIF_IO_BITMAP);
1da177e4
LT
165 }
166
efd1ca52
RM
167 err = 0;
168
1da177e4
LT
169 /*
170 * Set a new TLS for the child thread?
171 */
efd1ca52
RM
172 if (clone_flags & CLONE_SETTLS)
173 err = do_set_thread_area(p, -1,
c1bd55f9 174 (struct user_desc __user *)tls, 0);
1da177e4 175
1da177e4
LT
176 if (err && p->thread.io_bitmap_ptr) {
177 kfree(p->thread.io_bitmap_ptr);
178 p->thread.io_bitmap_max = 0;
179 }
180 return err;
181}
182
513ad84b
IM
183void
184start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
185{
d9a89a26 186 set_user_gs(regs, 0);
513ad84b 187 regs->fs = 0;
513ad84b
IM
188 regs->ds = __USER_DS;
189 regs->es = __USER_DS;
190 regs->ss = __USER_DS;
191 regs->cs = __USER_CS;
192 regs->ip = new_ip;
193 regs->sp = new_sp;
6783eaa2 194 regs->flags = X86_EFLAGS_IF;
1daeaa31 195 force_iret();
513ad84b
IM
196}
197EXPORT_SYMBOL_GPL(start_thread);
198
1da177e4
LT
199
200/*
ea70ef3d 201 * switch_to(x,y) should switch tasks from x to y.
1da177e4
LT
202 *
203 * We fsave/fwait so that an exception goes off at the right time
204 * (as a call from the fsave or fwait in effect) rather than to
205 * the wrong process. Lazy FP saving no longer makes any sense
206 * with modern CPU's, and this simplifies a lot of things (SMP
207 * and UP become the same).
208 *
209 * NOTE! We used to use the x86 hardware context switching. The
210 * reason for not using it any more becomes apparent when you
211 * try to recover gracefully from saved state that is no longer
212 * valid (stale segment register values in particular). With the
213 * hardware task-switch, there is no way to fix up bad state in
214 * a reasonable manner.
215 *
216 * The fact that Intel documents the hardware task-switching to
217 * be slow is a fairly red herring - this code is not noticeably
218 * faster. However, there _is_ some room for improvement here,
219 * so the performance issues may eventually be a valid point.
220 * More important, however, is the fact that this allows us much
221 * more flexibility.
222 *
65ea5b03 223 * The return value (in %ax) will be the "prev" task after
1da177e4
LT
224 * the task-switch, and shows up in ret_from_fork in entry.S,
225 * for example.
226 */
35ea7903 227__visible __notrace_funcgraph struct task_struct *
8b96f011 228__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
1da177e4
LT
229{
230 struct thread_struct *prev = &prev_p->thread,
384a23f9
IM
231 *next = &next_p->thread;
232 struct fpu *prev_fpu = &prev->fpu;
233 struct fpu *next_fpu = &next->fpu;
1da177e4 234 int cpu = smp_processor_id();
24933b82 235 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
1da177e4
LT
236
237 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
238
c474e507 239 switch_fpu_prepare(prev_fpu, cpu);
acc20761 240
1da177e4 241 /*
464d1a78 242 * Save away %gs. No need to save %fs, as it was saved on the
f95d47ca
JF
243 * stack on entry. No need to save %es and %ds, as those are
244 * always kernel segments while inside the kernel. Doing this
245 * before setting the new TLS descriptors avoids the situation
246 * where we temporarily have non-reloadable segments in %fs
247 * and %gs. This could be an issue if the NMI handler ever
248 * used %fs or %gs (it does not today), or if the kernel is
249 * running inside of a hypervisor layer.
1da177e4 250 */
ccbeed3a 251 lazy_save_gs(prev->gs);
1da177e4
LT
252
253 /*
e7a2ff59 254 * Load the per-thread Thread-Local Storage descriptor.
1da177e4 255 */
e7a2ff59 256 load_TLS(next, cpu);
1da177e4 257
8b151144
ZA
258 /*
259 * Restore IOPL if needed. In normal use, the flags restore
260 * in the switch assembly will handle this. But if the kernel
261 * is running virtualized at a non-zero CPL, the popf will
262 * not restore flags, so it must be done in a separate step.
263 */
264 if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
265 set_iopl_mask(next->iopl);
266
1da177e4 267 /*
b3cf2576 268 * Now maybe handle debug registers and/or IO bitmaps
1da177e4 269 */
cf99abac
AA
270 if (unlikely(task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV ||
271 task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT))
272 __switch_to_xtra(prev_p, next_p, tss);
ffaa8bd6 273
9226d125
ZA
274 /*
275 * Leave lazy mode, flushing any hypercalls made here.
276 * This must be done before restoring TLS segments so
277 * the GDT and LDT are properly updated, and must be
3a0aee48 278 * done before fpu__restore(), so the TS bit is up
9226d125
ZA
279 * to date.
280 */
224101ed 281 arch_end_context_switch(next_p);
9226d125 282
b27559a4 283 /*
fed7c3f0 284 * Reload esp0 and cpu_current_top_of_stack. This changes
a7fcf28d 285 * current_thread_info().
b27559a4
AL
286 */
287 load_sp0(tss, next);
a7fcf28d
AL
288 this_cpu_write(cpu_current_top_of_stack,
289 (unsigned long)task_stack_page(next_p) +
290 THREAD_SIZE);
198d208d 291
9226d125
ZA
292 /*
293 * Restore %gs if needed (which is common)
294 */
295 if (prev->gs | next->gs)
ccbeed3a 296 lazy_load_gs(next->gs);
9226d125 297
c474e507 298 switch_fpu_finish(next_fpu, cpu);
34ddc81a 299
c6ae41e7 300 this_cpu_write(current_task, next_p);
9226d125 301
4f341a5e
FY
302 /* Load the Intel cache allocation PQR MSR. */
303 intel_rdt_sched_in();
304
1da177e4
LT
305 return prev_p;
306}