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x86/process: Consolidate and simplify switch_to_xtra() code
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CommitLineData
1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
f3705136 12#include <linux/cpu.h>
1da177e4
LT
13#include <linux/errno.h>
14#include <linux/sched.h>
29930025 15#include <linux/sched/task.h>
68db0cf1 16#include <linux/sched/task_stack.h>
1da177e4
LT
17#include <linux/fs.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/elfcore.h>
21#include <linux/smp.h>
1da177e4
LT
22#include <linux/stddef.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/user.h>
1da177e4 26#include <linux/interrupt.h>
1da177e4
LT
27#include <linux/delay.h>
28#include <linux/reboot.h>
1da177e4 29#include <linux/mc146818rtc.h>
186f4360 30#include <linux/export.h>
1da177e4
LT
31#include <linux/kallsyms.h>
32#include <linux/ptrace.h>
c16b63e0 33#include <linux/personality.h>
7c3576d2 34#include <linux/percpu.h>
529e25f6 35#include <linux/prctl.h>
8b96f011 36#include <linux/ftrace.h>
befa9e78
JSR
37#include <linux/uaccess.h>
38#include <linux/io.h>
39#include <linux/kdebug.h>
79170fda 40#include <linux/syscalls.h>
1da177e4 41
1da177e4 42#include <asm/pgtable.h>
1da177e4
LT
43#include <asm/ldt.h>
44#include <asm/processor.h>
78f7f1e5 45#include <asm/fpu/internal.h>
1da177e4
LT
46#include <asm/desc.h>
47#ifdef CONFIG_MATH_EMULATION
48#include <asm/math_emu.h>
49#endif
50
1da177e4
LT
51#include <linux/err.h>
52
f3705136
ZM
53#include <asm/tlbflush.h>
54#include <asm/cpu.h>
bbc1f698 55#include <asm/syscalls.h>
66cb5917 56#include <asm/debugreg.h>
f05e798a 57#include <asm/switch_to.h>
ba3e127e 58#include <asm/vm86.h>
05830204 59#include <asm/intel_rdt_sched.h>
79170fda 60#include <asm/proto.h>
f3705136 61
b84511cd
TG
62#include "process.h"
63
e2ce07c8 64void __show_regs(struct pt_regs *regs, int all)
1da177e4
LT
65{
66 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
bb1995d5 67 unsigned long d0, d1, d2, d3, d6, d7;
65ea5b03 68 unsigned long sp;
9d975ebd
PE
69 unsigned short ss, gs;
70
f39b6f0e 71 if (user_mode(regs)) {
65ea5b03 72 sp = regs->sp;
99504819 73 ss = regs->ss;
d9a89a26 74 gs = get_user_gs(regs);
9d975ebd 75 } else {
def3c5d0 76 sp = kernel_stack_pointer(regs);
9d975ebd
PE
77 savesegment(ss, ss);
78 savesegment(gs, gs);
79 }
1da177e4 80
bb5e5ce5
JP
81 printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
82 printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
5d9070b1 83 raw_smp_processor_id());
1da177e4 84
d015a092 85 printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
65ea5b03 86 regs->ax, regs->bx, regs->cx, regs->dx);
d015a092 87 printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
65ea5b03 88 regs->si, regs->di, regs->bp, sp);
d015a092 89 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
92bc2056 90 (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
9d975ebd
PE
91
92 if (!all)
93 return;
1da177e4 94
4bb0d3ec
ZA
95 cr0 = read_cr0();
96 cr2 = read_cr2();
6c690ee1 97 cr3 = __read_cr3();
1ef55be1 98 cr4 = __read_cr4();
d015a092 99 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
9d975ebd 100 cr0, cr2, cr3, cr4);
bb1995d5
AS
101
102 get_debugreg(d0, 0);
103 get_debugreg(d1, 1);
104 get_debugreg(d2, 2);
105 get_debugreg(d3, 3);
bb1995d5
AS
106 get_debugreg(d6, 6);
107 get_debugreg(d7, 7);
4338774c
DJ
108
109 /* Only print out debug registers if they are in their non-default state. */
110 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
111 (d6 == DR6_RESERVED) && (d7 == 0x400))
112 return;
113
114 printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
115 d0, d1, d2, d3);
d015a092 116 printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
9d975ebd
PE
117 d6, d7);
118}
bb1995d5 119
1da177e4
LT
120void release_thread(struct task_struct *dead_task)
121{
2684927c 122 BUG_ON(dead_task->mm);
1da177e4
LT
123 release_vm86_irqs(dead_task);
124}
125
c1bd55f9
JT
126int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
127 unsigned long arg, struct task_struct *p, unsigned long tls)
1da177e4 128{
7076aada 129 struct pt_regs *childregs = task_pt_regs(p);
0100301b
BG
130 struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
131 struct inactive_task_frame *frame = &fork_frame->frame;
1da177e4
LT
132 struct task_struct *tsk;
133 int err;
134
0100301b 135 frame->bp = 0;
616d2483 136 frame->ret_addr = (unsigned long) ret_from_fork;
0100301b 137 p->thread.sp = (unsigned long) fork_frame;
7076aada 138 p->thread.sp0 = (unsigned long) (childregs+1);
6f46b3ae 139 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
7076aada 140
1d4b4b29 141 if (unlikely(p->flags & PF_KTHREAD)) {
7076aada
AV
142 /* kernel thread */
143 memset(childregs, 0, sizeof(struct pt_regs));
616d2483
BG
144 frame->bx = sp; /* function */
145 frame->di = arg;
7076aada 146 p->thread.io_bitmap_ptr = NULL;
7076aada
AV
147 return 0;
148 }
616d2483 149 frame->bx = 0;
1d4b4b29 150 *childregs = *current_pt_regs();
65ea5b03 151 childregs->ax = 0;
1d4b4b29
AV
152 if (sp)
153 childregs->sp = sp;
f48d9663 154
1d4b4b29 155 task_user_gs(p) = get_user_gs(current_pt_regs());
1da177e4 156
66cb5917 157 p->thread.io_bitmap_ptr = NULL;
1da177e4 158 tsk = current;
66cb5917 159 err = -ENOMEM;
24f1e32c 160
b3cf2576 161 if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
52978be6
AD
162 p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
163 IO_BITMAP_BYTES, GFP_KERNEL);
1da177e4
LT
164 if (!p->thread.io_bitmap_ptr) {
165 p->thread.io_bitmap_max = 0;
166 return -ENOMEM;
167 }
b3cf2576 168 set_tsk_thread_flag(p, TIF_IO_BITMAP);
1da177e4
LT
169 }
170
efd1ca52
RM
171 err = 0;
172
1da177e4
LT
173 /*
174 * Set a new TLS for the child thread?
175 */
efd1ca52
RM
176 if (clone_flags & CLONE_SETTLS)
177 err = do_set_thread_area(p, -1,
c1bd55f9 178 (struct user_desc __user *)tls, 0);
1da177e4 179
1da177e4
LT
180 if (err && p->thread.io_bitmap_ptr) {
181 kfree(p->thread.io_bitmap_ptr);
182 p->thread.io_bitmap_max = 0;
183 }
184 return err;
185}
186
513ad84b
IM
187void
188start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
189{
d9a89a26 190 set_user_gs(regs, 0);
513ad84b 191 regs->fs = 0;
513ad84b
IM
192 regs->ds = __USER_DS;
193 regs->es = __USER_DS;
194 regs->ss = __USER_DS;
195 regs->cs = __USER_CS;
196 regs->ip = new_ip;
197 regs->sp = new_sp;
6783eaa2 198 regs->flags = X86_EFLAGS_IF;
1daeaa31 199 force_iret();
513ad84b
IM
200}
201EXPORT_SYMBOL_GPL(start_thread);
202
1da177e4
LT
203
204/*
ea70ef3d 205 * switch_to(x,y) should switch tasks from x to y.
1da177e4
LT
206 *
207 * We fsave/fwait so that an exception goes off at the right time
208 * (as a call from the fsave or fwait in effect) rather than to
209 * the wrong process. Lazy FP saving no longer makes any sense
210 * with modern CPU's, and this simplifies a lot of things (SMP
211 * and UP become the same).
212 *
213 * NOTE! We used to use the x86 hardware context switching. The
214 * reason for not using it any more becomes apparent when you
215 * try to recover gracefully from saved state that is no longer
216 * valid (stale segment register values in particular). With the
217 * hardware task-switch, there is no way to fix up bad state in
218 * a reasonable manner.
219 *
220 * The fact that Intel documents the hardware task-switching to
221 * be slow is a fairly red herring - this code is not noticeably
222 * faster. However, there _is_ some room for improvement here,
223 * so the performance issues may eventually be a valid point.
224 * More important, however, is the fact that this allows us much
225 * more flexibility.
226 *
65ea5b03 227 * The return value (in %ax) will be the "prev" task after
1da177e4
LT
228 * the task-switch, and shows up in ret_from_fork in entry.S,
229 * for example.
230 */
35ea7903 231__visible __notrace_funcgraph struct task_struct *
8b96f011 232__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
1da177e4
LT
233{
234 struct thread_struct *prev = &prev_p->thread,
384a23f9
IM
235 *next = &next_p->thread;
236 struct fpu *prev_fpu = &prev->fpu;
237 struct fpu *next_fpu = &next->fpu;
1da177e4 238 int cpu = smp_processor_id();
1da177e4
LT
239
240 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
241
c474e507 242 switch_fpu_prepare(prev_fpu, cpu);
acc20761 243
1da177e4 244 /*
464d1a78 245 * Save away %gs. No need to save %fs, as it was saved on the
f95d47ca
JF
246 * stack on entry. No need to save %es and %ds, as those are
247 * always kernel segments while inside the kernel. Doing this
248 * before setting the new TLS descriptors avoids the situation
249 * where we temporarily have non-reloadable segments in %fs
250 * and %gs. This could be an issue if the NMI handler ever
251 * used %fs or %gs (it does not today), or if the kernel is
252 * running inside of a hypervisor layer.
1da177e4 253 */
ccbeed3a 254 lazy_save_gs(prev->gs);
1da177e4
LT
255
256 /*
e7a2ff59 257 * Load the per-thread Thread-Local Storage descriptor.
1da177e4 258 */
e7a2ff59 259 load_TLS(next, cpu);
1da177e4 260
8b151144
ZA
261 /*
262 * Restore IOPL if needed. In normal use, the flags restore
263 * in the switch assembly will handle this. But if the kernel
264 * is running virtualized at a non-zero CPL, the popf will
265 * not restore flags, so it must be done in a separate step.
266 */
267 if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
268 set_iopl_mask(next->iopl);
269
b84511cd 270 switch_to_extra(prev_p, next_p);
ffaa8bd6 271
9226d125
ZA
272 /*
273 * Leave lazy mode, flushing any hypercalls made here.
274 * This must be done before restoring TLS segments so
275 * the GDT and LDT are properly updated, and must be
3a0aee48 276 * done before fpu__restore(), so the TS bit is up
9226d125
ZA
277 * to date.
278 */
224101ed 279 arch_end_context_switch(next_p);
9226d125 280
b27559a4 281 /*
fed7c3f0 282 * Reload esp0 and cpu_current_top_of_stack. This changes
bd7dc5a6
AL
283 * current_thread_info(). Refresh the SYSENTER configuration in
284 * case prev or next is vm86.
b27559a4 285 */
46f5a10a 286 update_sp0(next_p);
bd7dc5a6 287 refresh_sysenter_cs(next);
a7fcf28d
AL
288 this_cpu_write(cpu_current_top_of_stack,
289 (unsigned long)task_stack_page(next_p) +
290 THREAD_SIZE);
198d208d 291
9226d125
ZA
292 /*
293 * Restore %gs if needed (which is common)
294 */
295 if (prev->gs | next->gs)
ccbeed3a 296 lazy_load_gs(next->gs);
9226d125 297
c474e507 298 switch_fpu_finish(next_fpu, cpu);
34ddc81a 299
c6ae41e7 300 this_cpu_write(current_task, next_p);
9226d125 301
4f341a5e
FY
302 /* Load the Intel cache allocation PQR MSR. */
303 intel_rdt_sched_in();
304
1da177e4
LT
305 return prev_p;
306}
79170fda
KH
307
308SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
309{
310 return do_arch_prctl_common(current, option, arg2);
311}