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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1995 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
6612538c | 6 | * |
1da177e4 LT |
7 | * X86-64 port |
8 | * Andi Kleen. | |
76e4f660 AR |
9 | * |
10 | * CPU hotplug support - ashok.raj@intel.com | |
1da177e4 LT |
11 | */ |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of process handling.. | |
15 | */ | |
16 | ||
76e4f660 | 17 | #include <linux/cpu.h> |
1da177e4 LT |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
6612538c | 20 | #include <linux/fs.h> |
1da177e4 LT |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/elfcore.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/user.h> | |
1da177e4 LT |
27 | #include <linux/interrupt.h> |
28 | #include <linux/delay.h> | |
186f4360 | 29 | #include <linux/export.h> |
1da177e4 | 30 | #include <linux/ptrace.h> |
95833c83 | 31 | #include <linux/notifier.h> |
c6fd91f0 | 32 | #include <linux/kprobes.h> |
1eeb66a1 | 33 | #include <linux/kdebug.h> |
529e25f6 | 34 | #include <linux/prctl.h> |
7de08b4e GP |
35 | #include <linux/uaccess.h> |
36 | #include <linux/io.h> | |
8b96f011 | 37 | #include <linux/ftrace.h> |
1da177e4 | 38 | |
1da177e4 | 39 | #include <asm/pgtable.h> |
1da177e4 | 40 | #include <asm/processor.h> |
78f7f1e5 | 41 | #include <asm/fpu/internal.h> |
1da177e4 | 42 | #include <asm/mmu_context.h> |
1da177e4 | 43 | #include <asm/prctl.h> |
1da177e4 LT |
44 | #include <asm/desc.h> |
45 | #include <asm/proto.h> | |
46 | #include <asm/ia32.h> | |
95833c83 | 47 | #include <asm/idle.h> |
bbc1f698 | 48 | #include <asm/syscalls.h> |
66cb5917 | 49 | #include <asm/debugreg.h> |
f05e798a | 50 | #include <asm/switch_to.h> |
b7a58459 | 51 | #include <asm/xen/hypervisor.h> |
1da177e4 LT |
52 | |
53 | asmlinkage extern void ret_from_fork(void); | |
54 | ||
c38e5038 | 55 | __visible DEFINE_PER_CPU(unsigned long, rsp_scratch); |
1da177e4 | 56 | |
6612538c | 57 | /* Prints also some state that isn't saved in the pt_regs */ |
e2ce07c8 | 58 | void __show_regs(struct pt_regs *regs, int all) |
1da177e4 LT |
59 | { |
60 | unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs; | |
bb1995d5 | 61 | unsigned long d0, d1, d2, d3, d6, d7; |
6612538c HS |
62 | unsigned int fsindex, gsindex; |
63 | unsigned int ds, cs, es; | |
814e2c84 | 64 | |
d015a092 | 65 | printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip); |
5f01c988 | 66 | printk_address(regs->ip); |
d015a092 | 67 | printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss, |
8092c654 | 68 | regs->sp, regs->flags); |
d015a092 | 69 | printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n", |
65ea5b03 | 70 | regs->ax, regs->bx, regs->cx); |
d015a092 | 71 | printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n", |
65ea5b03 | 72 | regs->dx, regs->si, regs->di); |
d015a092 | 73 | printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n", |
65ea5b03 | 74 | regs->bp, regs->r8, regs->r9); |
d015a092 | 75 | printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n", |
7de08b4e | 76 | regs->r10, regs->r11, regs->r12); |
d015a092 | 77 | printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n", |
7de08b4e | 78 | regs->r13, regs->r14, regs->r15); |
1da177e4 | 79 | |
7de08b4e GP |
80 | asm("movl %%ds,%0" : "=r" (ds)); |
81 | asm("movl %%cs,%0" : "=r" (cs)); | |
82 | asm("movl %%es,%0" : "=r" (es)); | |
1da177e4 LT |
83 | asm("movl %%fs,%0" : "=r" (fsindex)); |
84 | asm("movl %%gs,%0" : "=r" (gsindex)); | |
85 | ||
86 | rdmsrl(MSR_FS_BASE, fs); | |
7de08b4e GP |
87 | rdmsrl(MSR_GS_BASE, gs); |
88 | rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); | |
1da177e4 | 89 | |
e2ce07c8 PE |
90 | if (!all) |
91 | return; | |
1da177e4 | 92 | |
f51c9452 GOC |
93 | cr0 = read_cr0(); |
94 | cr2 = read_cr2(); | |
95 | cr3 = read_cr3(); | |
1e02ce4c | 96 | cr4 = __read_cr4(); |
1da177e4 | 97 | |
d015a092 | 98 | printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", |
7de08b4e | 99 | fs, fsindex, gs, gsindex, shadowgs); |
d015a092 | 100 | printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds, |
8092c654 | 101 | es, cr0); |
d015a092 | 102 | printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3, |
8092c654 | 103 | cr4); |
bb1995d5 AS |
104 | |
105 | get_debugreg(d0, 0); | |
106 | get_debugreg(d1, 1); | |
107 | get_debugreg(d2, 2); | |
bb1995d5 AS |
108 | get_debugreg(d3, 3); |
109 | get_debugreg(d6, 6); | |
110 | get_debugreg(d7, 7); | |
4338774c DJ |
111 | |
112 | /* Only print out debug registers if they are in their non-default state. */ | |
113 | if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && | |
114 | (d6 == DR6_RESERVED) && (d7 == 0x400)) | |
115 | return; | |
116 | ||
117 | printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2); | |
d015a092 | 118 | printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7); |
4338774c | 119 | |
c0b17b5b DH |
120 | if (boot_cpu_has(X86_FEATURE_OSPKE)) |
121 | printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru()); | |
1da177e4 LT |
122 | } |
123 | ||
1da177e4 LT |
124 | void release_thread(struct task_struct *dead_task) |
125 | { | |
126 | if (dead_task->mm) { | |
a5b9e5a2 | 127 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 | 128 | if (dead_task->mm->context.ldt) { |
349eab6e | 129 | pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n", |
c767a54b | 130 | dead_task->comm, |
0d430e3f | 131 | dead_task->mm->context.ldt->entries, |
37868fe1 | 132 | dead_task->mm->context.ldt->size); |
1da177e4 LT |
133 | BUG(); |
134 | } | |
a5b9e5a2 | 135 | #endif |
1da177e4 LT |
136 | } |
137 | } | |
138 | ||
c1bd55f9 JT |
139 | int copy_thread_tls(unsigned long clone_flags, unsigned long sp, |
140 | unsigned long arg, struct task_struct *p, unsigned long tls) | |
1da177e4 LT |
141 | { |
142 | int err; | |
7de08b4e | 143 | struct pt_regs *childregs; |
0100301b BG |
144 | struct fork_frame *fork_frame; |
145 | struct inactive_task_frame *frame; | |
1da177e4 LT |
146 | struct task_struct *me = current; |
147 | ||
7076aada AV |
148 | p->thread.sp0 = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
149 | childregs = task_pt_regs(p); | |
0100301b BG |
150 | fork_frame = container_of(childregs, struct fork_frame, regs); |
151 | frame = &fork_frame->frame; | |
152 | frame->bp = 0; | |
153 | frame->ret_addr = (unsigned long) ret_from_fork; | |
154 | p->thread.sp = (unsigned long) fork_frame; | |
66cb5917 | 155 | p->thread.io_bitmap_ptr = NULL; |
1da177e4 | 156 | |
ada85708 | 157 | savesegment(gs, p->thread.gsindex); |
296f781a | 158 | p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase; |
ada85708 | 159 | savesegment(fs, p->thread.fsindex); |
296f781a | 160 | p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase; |
ada85708 JF |
161 | savesegment(es, p->thread.es); |
162 | savesegment(ds, p->thread.ds); | |
7076aada AV |
163 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
164 | ||
1d4b4b29 | 165 | if (unlikely(p->flags & PF_KTHREAD)) { |
7076aada AV |
166 | /* kernel thread */ |
167 | memset(childregs, 0, sizeof(struct pt_regs)); | |
168 | childregs->sp = (unsigned long)childregs; | |
169 | childregs->ss = __KERNEL_DS; | |
170 | childregs->bx = sp; /* function */ | |
171 | childregs->bp = arg; | |
172 | childregs->orig_ax = -1; | |
173 | childregs->cs = __KERNEL_CS | get_kernel_rpl(); | |
1adfa76a | 174 | childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED; |
7076aada AV |
175 | return 0; |
176 | } | |
1d4b4b29 | 177 | *childregs = *current_pt_regs(); |
7076aada AV |
178 | |
179 | childregs->ax = 0; | |
1d4b4b29 AV |
180 | if (sp) |
181 | childregs->sp = sp; | |
1da177e4 | 182 | |
66cb5917 | 183 | err = -ENOMEM; |
d3a4f48d | 184 | if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) { |
cced4022 TM |
185 | p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr, |
186 | IO_BITMAP_BYTES, GFP_KERNEL); | |
1da177e4 LT |
187 | if (!p->thread.io_bitmap_ptr) { |
188 | p->thread.io_bitmap_max = 0; | |
189 | return -ENOMEM; | |
190 | } | |
d3a4f48d | 191 | set_tsk_thread_flag(p, TIF_IO_BITMAP); |
6612538c | 192 | } |
1da177e4 LT |
193 | |
194 | /* | |
195 | * Set a new TLS for the child thread? | |
196 | */ | |
197 | if (clone_flags & CLONE_SETTLS) { | |
198 | #ifdef CONFIG_IA32_EMULATION | |
abfb9498 | 199 | if (in_ia32_syscall()) |
efd1ca52 | 200 | err = do_set_thread_area(p, -1, |
c1bd55f9 | 201 | (struct user_desc __user *)tls, 0); |
7de08b4e GP |
202 | else |
203 | #endif | |
c1bd55f9 | 204 | err = do_arch_prctl(p, ARCH_SET_FS, tls); |
7de08b4e | 205 | if (err) |
1da177e4 LT |
206 | goto out; |
207 | } | |
208 | err = 0; | |
209 | out: | |
210 | if (err && p->thread.io_bitmap_ptr) { | |
211 | kfree(p->thread.io_bitmap_ptr); | |
212 | p->thread.io_bitmap_max = 0; | |
213 | } | |
66cb5917 | 214 | |
1da177e4 LT |
215 | return err; |
216 | } | |
217 | ||
e634d8fc PA |
218 | static void |
219 | start_thread_common(struct pt_regs *regs, unsigned long new_ip, | |
220 | unsigned long new_sp, | |
221 | unsigned int _cs, unsigned int _ss, unsigned int _ds) | |
513ad84b | 222 | { |
ada85708 | 223 | loadsegment(fs, 0); |
e634d8fc PA |
224 | loadsegment(es, _ds); |
225 | loadsegment(ds, _ds); | |
513ad84b IM |
226 | load_gs_index(0); |
227 | regs->ip = new_ip; | |
228 | regs->sp = new_sp; | |
e634d8fc PA |
229 | regs->cs = _cs; |
230 | regs->ss = _ss; | |
a6f05a6a | 231 | regs->flags = X86_EFLAGS_IF; |
1daeaa31 | 232 | force_iret(); |
513ad84b | 233 | } |
e634d8fc PA |
234 | |
235 | void | |
236 | start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) | |
237 | { | |
238 | start_thread_common(regs, new_ip, new_sp, | |
239 | __USER_CS, __USER_DS, 0); | |
240 | } | |
513ad84b | 241 | |
7da77078 BG |
242 | #ifdef CONFIG_COMPAT |
243 | void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp) | |
a6f05a6a | 244 | { |
e634d8fc | 245 | start_thread_common(regs, new_ip, new_sp, |
d1a797f3 PA |
246 | test_thread_flag(TIF_X32) |
247 | ? __USER_CS : __USER32_CS, | |
248 | __USER_DS, __USER_DS); | |
a6f05a6a PA |
249 | } |
250 | #endif | |
513ad84b | 251 | |
1da177e4 LT |
252 | /* |
253 | * switch_to(x,y) should switch tasks from x to y. | |
254 | * | |
6612538c | 255 | * This could still be optimized: |
1da177e4 LT |
256 | * - fold all the options into a flag word and test it with a single test. |
257 | * - could test fs/gs bitsliced | |
099f318b AK |
258 | * |
259 | * Kprobes not supported here. Set the probe on schedule instead. | |
8b96f011 | 260 | * Function graph tracer not supported too. |
1da177e4 | 261 | */ |
35ea7903 | 262 | __visible __notrace_funcgraph struct task_struct * |
a88cde13 | 263 | __switch_to(struct task_struct *prev_p, struct task_struct *next_p) |
1da177e4 | 264 | { |
87b935a0 JF |
265 | struct thread_struct *prev = &prev_p->thread; |
266 | struct thread_struct *next = &next_p->thread; | |
384a23f9 IM |
267 | struct fpu *prev_fpu = &prev->fpu; |
268 | struct fpu *next_fpu = &next->fpu; | |
6612538c | 269 | int cpu = smp_processor_id(); |
24933b82 | 270 | struct tss_struct *tss = &per_cpu(cpu_tss, cpu); |
3e2b68d7 | 271 | unsigned prev_fsindex, prev_gsindex; |
384a23f9 | 272 | fpu_switch_t fpu_switch; |
e07e23e1 | 273 | |
384a23f9 | 274 | fpu_switch = switch_fpu_prepare(prev_fpu, next_fpu, cpu); |
4903062b | 275 | |
478de5a9 JF |
276 | /* We must save %fs and %gs before load_TLS() because |
277 | * %fs and %gs may be cleared by load_TLS(). | |
278 | * | |
279 | * (e.g. xen_load_tls()) | |
280 | */ | |
3e2b68d7 AL |
281 | savesegment(fs, prev_fsindex); |
282 | savesegment(gs, prev_gsindex); | |
478de5a9 | 283 | |
f647d7c1 AL |
284 | /* |
285 | * Load TLS before restoring any segments so that segment loads | |
286 | * reference the correct GDT entries. | |
287 | */ | |
1da177e4 LT |
288 | load_TLS(next, cpu); |
289 | ||
3fe0a63e | 290 | /* |
f647d7c1 AL |
291 | * Leave lazy mode, flushing any hypercalls made here. This |
292 | * must be done after loading TLS entries in the GDT but before | |
293 | * loading segments that might reference them, and and it must | |
3a0aee48 | 294 | * be done before fpu__restore(), so the TS bit is up to |
f647d7c1 | 295 | * date. |
3fe0a63e | 296 | */ |
224101ed | 297 | arch_end_context_switch(next_p); |
3fe0a63e | 298 | |
f647d7c1 AL |
299 | /* Switch DS and ES. |
300 | * | |
301 | * Reading them only returns the selectors, but writing them (if | |
302 | * nonzero) loads the full descriptor from the GDT or LDT. The | |
303 | * LDT for next is loaded in switch_mm, and the GDT is loaded | |
304 | * above. | |
305 | * | |
306 | * We therefore need to write new values to the segment | |
307 | * registers on every context switch unless both the new and old | |
308 | * values are zero. | |
309 | * | |
310 | * Note that we don't need to do anything for CS and SS, as | |
311 | * those are saved and restored as part of pt_regs. | |
312 | */ | |
313 | savesegment(es, prev->es); | |
314 | if (unlikely(next->es | prev->es)) | |
315 | loadsegment(es, next->es); | |
316 | ||
317 | savesegment(ds, prev->ds); | |
318 | if (unlikely(next->ds | prev->ds)) | |
319 | loadsegment(ds, next->ds); | |
320 | ||
7de08b4e | 321 | /* |
1da177e4 | 322 | * Switch FS and GS. |
87b935a0 | 323 | * |
558a65bc | 324 | * These are even more complicated than DS and ES: they have |
3e2b68d7 AL |
325 | * 64-bit bases are that controlled by arch_prctl. The bases |
326 | * don't necessarily match the selectors, as user code can do | |
327 | * any number of things to cause them to be inconsistent. | |
f647d7c1 | 328 | * |
3e2b68d7 AL |
329 | * We don't promise to preserve the bases if the selectors are |
330 | * nonzero. We also don't promise to preserve the base if the | |
331 | * selector is zero and the base doesn't match whatever was | |
332 | * most recently passed to ARCH_SET_FS/GS. (If/when the | |
333 | * FSGSBASE instructions are enabled, we'll need to offer | |
334 | * stronger guarantees.) | |
f647d7c1 | 335 | * |
3e2b68d7 | 336 | * As an invariant, |
296f781a | 337 | * (fsbase != 0 && fsindex != 0) || (gsbase != 0 && gsindex != 0) is |
3e2b68d7 | 338 | * impossible. |
1da177e4 | 339 | */ |
3e2b68d7 AL |
340 | if (next->fsindex) { |
341 | /* Loading a nonzero value into FS sets the index and base. */ | |
87b935a0 | 342 | loadsegment(fs, next->fsindex); |
3e2b68d7 | 343 | } else { |
296f781a | 344 | if (next->fsbase) { |
3e2b68d7 AL |
345 | /* Next index is zero but next base is nonzero. */ |
346 | if (prev_fsindex) | |
347 | loadsegment(fs, 0); | |
296f781a | 348 | wrmsrl(MSR_FS_BASE, next->fsbase); |
3e2b68d7 AL |
349 | } else { |
350 | /* Next base and index are both zero. */ | |
351 | if (static_cpu_has_bug(X86_BUG_NULL_SEG)) { | |
352 | /* | |
353 | * We don't know the previous base and can't | |
354 | * find out without RDMSR. Forcibly clear it. | |
355 | */ | |
356 | loadsegment(fs, __USER_DS); | |
357 | loadsegment(fs, 0); | |
358 | } else { | |
359 | /* | |
360 | * If the previous index is zero and ARCH_SET_FS | |
361 | * didn't change the base, then the base is | |
362 | * also zero and we don't need to do anything. | |
363 | */ | |
296f781a | 364 | if (prev->fsbase || prev_fsindex) |
3e2b68d7 AL |
365 | loadsegment(fs, 0); |
366 | } | |
367 | } | |
1da177e4 | 368 | } |
3e2b68d7 AL |
369 | /* |
370 | * Save the old state and preserve the invariant. | |
371 | * NB: if prev_fsindex == 0, then we can't reliably learn the base | |
372 | * without RDMSR because Intel user code can zero it without telling | |
373 | * us and AMD user code can program any 32-bit value without telling | |
374 | * us. | |
375 | */ | |
376 | if (prev_fsindex) | |
296f781a | 377 | prev->fsbase = 0; |
3e2b68d7 | 378 | prev->fsindex = prev_fsindex; |
87b935a0 | 379 | |
3e2b68d7 AL |
380 | if (next->gsindex) { |
381 | /* Loading a nonzero value into GS sets the index and base. */ | |
87b935a0 | 382 | load_gs_index(next->gsindex); |
3e2b68d7 | 383 | } else { |
296f781a | 384 | if (next->gsbase) { |
3e2b68d7 AL |
385 | /* Next index is zero but next base is nonzero. */ |
386 | if (prev_gsindex) | |
387 | load_gs_index(0); | |
296f781a | 388 | wrmsrl(MSR_KERNEL_GS_BASE, next->gsbase); |
3e2b68d7 AL |
389 | } else { |
390 | /* Next base and index are both zero. */ | |
391 | if (static_cpu_has_bug(X86_BUG_NULL_SEG)) { | |
392 | /* | |
393 | * We don't know the previous base and can't | |
394 | * find out without RDMSR. Forcibly clear it. | |
395 | * | |
396 | * This contains a pointless SWAPGS pair. | |
397 | * Fixing it would involve an explicit check | |
398 | * for Xen or a new pvop. | |
399 | */ | |
400 | load_gs_index(__USER_DS); | |
401 | load_gs_index(0); | |
402 | } else { | |
403 | /* | |
404 | * If the previous index is zero and ARCH_SET_GS | |
405 | * didn't change the base, then the base is | |
406 | * also zero and we don't need to do anything. | |
407 | */ | |
296f781a | 408 | if (prev->gsbase || prev_gsindex) |
3e2b68d7 AL |
409 | load_gs_index(0); |
410 | } | |
411 | } | |
1da177e4 | 412 | } |
3e2b68d7 AL |
413 | /* |
414 | * Save the old state and preserve the invariant. | |
415 | * NB: if prev_gsindex == 0, then we can't reliably learn the base | |
416 | * without RDMSR because Intel user code can zero it without telling | |
417 | * us and AMD user code can program any 32-bit value without telling | |
418 | * us. | |
419 | */ | |
420 | if (prev_gsindex) | |
296f781a | 421 | prev->gsbase = 0; |
3e2b68d7 | 422 | prev->gsindex = prev_gsindex; |
1da177e4 | 423 | |
384a23f9 | 424 | switch_fpu_finish(next_fpu, fpu_switch); |
34ddc81a | 425 | |
7de08b4e | 426 | /* |
45948d77 | 427 | * Switch the PDA and FPU contexts. |
1da177e4 | 428 | */ |
c6ae41e7 | 429 | this_cpu_write(current_task, next_p); |
18bd057b | 430 | |
b27559a4 AL |
431 | /* Reload esp0 and ss1. This changes current_thread_info(). */ |
432 | load_sp0(tss, next); | |
433 | ||
1da177e4 | 434 | /* |
d3a4f48d | 435 | * Now maybe reload the debug registers and handle I/O bitmaps |
1da177e4 | 436 | */ |
eee3af4a MM |
437 | if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT || |
438 | task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV)) | |
d3a4f48d | 439 | __switch_to_xtra(prev_p, next_p, tss); |
1da177e4 | 440 | |
b7a58459 AL |
441 | #ifdef CONFIG_XEN |
442 | /* | |
443 | * On Xen PV, IOPL bits in pt_regs->flags have no effect, and | |
444 | * current_pt_regs()->flags may not match the current task's | |
445 | * intended IOPL. We need to switch it manually. | |
446 | */ | |
447 | if (unlikely(static_cpu_has(X86_FEATURE_XENPV) && | |
448 | prev->iopl != next->iopl)) | |
449 | xen_set_iopl_mask(next->iopl); | |
450 | #endif | |
451 | ||
61f01dd9 AL |
452 | if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) { |
453 | /* | |
454 | * AMD CPUs have a misfeature: SYSRET sets the SS selector but | |
455 | * does not update the cached descriptor. As a result, if we | |
456 | * do SYSRET while SS is NULL, we'll end up in user mode with | |
457 | * SS apparently equal to __USER_DS but actually unusable. | |
458 | * | |
459 | * The straightforward workaround would be to fix it up just | |
460 | * before SYSRET, but that would slow down the system call | |
461 | * fast paths. Instead, we ensure that SS is never NULL in | |
462 | * system call context. We do this by replacing NULL SS | |
463 | * selectors at every context switch. SYSCALL sets up a valid | |
464 | * SS, so the only way to get NULL is to re-enter the kernel | |
465 | * from CPL 3 through an interrupt. Since that can't happen | |
466 | * in the same task as a running syscall, we are guaranteed to | |
467 | * context switch between every interrupt vector entry and a | |
468 | * subsequent SYSRET. | |
469 | * | |
470 | * We read SS first because SS reads are much faster than | |
471 | * writes. Out of caution, we force SS to __KERNEL_DS even if | |
472 | * it previously had a different non-NULL value. | |
473 | */ | |
474 | unsigned short ss_sel; | |
475 | savesegment(ss, ss_sel); | |
476 | if (ss_sel != __KERNEL_DS) | |
477 | loadsegment(ss, __KERNEL_DS); | |
478 | } | |
479 | ||
1da177e4 LT |
480 | return prev_p; |
481 | } | |
482 | ||
1da177e4 LT |
483 | void set_personality_64bit(void) |
484 | { | |
485 | /* inherit personality from parent */ | |
486 | ||
487 | /* Make sure to be in 64bit mode */ | |
6612538c | 488 | clear_thread_flag(TIF_IA32); |
6bd33008 | 489 | clear_thread_flag(TIF_ADDR32); |
bb212724 | 490 | clear_thread_flag(TIF_X32); |
1da177e4 | 491 | |
375906f8 SW |
492 | /* Ensure the corresponding mm is not marked. */ |
493 | if (current->mm) | |
494 | current->mm->context.ia32_compat = 0; | |
495 | ||
1da177e4 LT |
496 | /* TBD: overwrites user setup. Should have two bits. |
497 | But 64bit processes have always behaved this way, | |
498 | so it's not too bad. The main problem is just that | |
6612538c | 499 | 32bit childs are affected again. */ |
1da177e4 LT |
500 | current->personality &= ~READ_IMPLIES_EXEC; |
501 | } | |
502 | ||
d1a797f3 | 503 | void set_personality_ia32(bool x32) |
05d43ed8 PA |
504 | { |
505 | /* inherit personality from parent */ | |
506 | ||
507 | /* Make sure to be in 32bit mode */ | |
6bd33008 | 508 | set_thread_flag(TIF_ADDR32); |
05d43ed8 | 509 | |
375906f8 | 510 | /* Mark the associated mm as containing 32-bit tasks. */ |
d1a797f3 PA |
511 | if (x32) { |
512 | clear_thread_flag(TIF_IA32); | |
513 | set_thread_flag(TIF_X32); | |
b24dc8da ON |
514 | if (current->mm) |
515 | current->mm->context.ia32_compat = TIF_X32; | |
d1a797f3 | 516 | current->personality &= ~READ_IMPLIES_EXEC; |
f970165b | 517 | /* in_compat_syscall() uses the presence of the x32 |
ce5f7a99 BP |
518 | syscall bit flag to determine compat status */ |
519 | current_thread_info()->status &= ~TS_COMPAT; | |
d1a797f3 PA |
520 | } else { |
521 | set_thread_flag(TIF_IA32); | |
522 | clear_thread_flag(TIF_X32); | |
b24dc8da ON |
523 | if (current->mm) |
524 | current->mm->context.ia32_compat = TIF_IA32; | |
d1a797f3 PA |
525 | current->personality |= force_personality32; |
526 | /* Prepare the first "return" to user space */ | |
527 | current_thread_info()->status |= TS_COMPAT; | |
528 | } | |
05d43ed8 | 529 | } |
febb72a6 | 530 | EXPORT_SYMBOL_GPL(set_personality_ia32); |
05d43ed8 | 531 | |
1da177e4 | 532 | long do_arch_prctl(struct task_struct *task, int code, unsigned long addr) |
7de08b4e GP |
533 | { |
534 | int ret = 0; | |
1da177e4 LT |
535 | int doit = task == current; |
536 | int cpu; | |
537 | ||
7de08b4e | 538 | switch (code) { |
1da177e4 | 539 | case ARCH_SET_GS: |
d696ca01 | 540 | if (addr >= TASK_SIZE_MAX) |
7de08b4e | 541 | return -EPERM; |
1da177e4 | 542 | cpu = get_cpu(); |
731e33e3 | 543 | task->thread.gsindex = 0; |
296f781a | 544 | task->thread.gsbase = addr; |
731e33e3 AL |
545 | if (doit) { |
546 | load_gs_index(0); | |
547 | ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr); | |
1da177e4 | 548 | } |
4afd0565 | 549 | put_cpu(); |
1da177e4 LT |
550 | break; |
551 | case ARCH_SET_FS: | |
552 | /* Not strictly needed for fs, but do it for symmetry | |
553 | with gs */ | |
d696ca01 | 554 | if (addr >= TASK_SIZE_MAX) |
6612538c | 555 | return -EPERM; |
1da177e4 | 556 | cpu = get_cpu(); |
731e33e3 | 557 | task->thread.fsindex = 0; |
296f781a | 558 | task->thread.fsbase = addr; |
731e33e3 AL |
559 | if (doit) { |
560 | /* set the selector to 0 to not confuse __switch_to */ | |
561 | loadsegment(fs, 0); | |
562 | ret = wrmsrl_safe(MSR_FS_BASE, addr); | |
1da177e4 LT |
563 | } |
564 | put_cpu(); | |
565 | break; | |
6612538c HS |
566 | case ARCH_GET_FS: { |
567 | unsigned long base; | |
d47b50e7 | 568 | if (doit) |
1da177e4 | 569 | rdmsrl(MSR_FS_BASE, base); |
a88cde13 | 570 | else |
296f781a | 571 | base = task->thread.fsbase; |
6612538c HS |
572 | ret = put_user(base, (unsigned long __user *)addr); |
573 | break; | |
1da177e4 | 574 | } |
6612538c | 575 | case ARCH_GET_GS: { |
1da177e4 | 576 | unsigned long base; |
d47b50e7 AL |
577 | if (doit) |
578 | rdmsrl(MSR_KERNEL_GS_BASE, base); | |
d47b50e7 | 579 | else |
296f781a | 580 | base = task->thread.gsbase; |
6612538c | 581 | ret = put_user(base, (unsigned long __user *)addr); |
1da177e4 LT |
582 | break; |
583 | } | |
584 | ||
585 | default: | |
586 | ret = -EINVAL; | |
587 | break; | |
6612538c | 588 | } |
1da177e4 | 589 | |
6612538c HS |
590 | return ret; |
591 | } | |
1da177e4 LT |
592 | |
593 | long sys_arch_prctl(int code, unsigned long addr) | |
594 | { | |
595 | return do_arch_prctl(current, code, addr); | |
1da177e4 LT |
596 | } |
597 | ||
89240ba0 SS |
598 | unsigned long KSTK_ESP(struct task_struct *task) |
599 | { | |
263042e4 | 600 | return task_pt_regs(task)->sp; |
89240ba0 | 601 | } |