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CommitLineData
1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6612538c 6 *
1da177e4
LT
7 * X86-64 port
8 * Andi Kleen.
76e4f660
AR
9 *
10 * CPU hotplug support - ashok.raj@intel.com
1da177e4
LT
11 */
12
13/*
14 * This file handles the architecture-dependent parts of process handling..
15 */
16
76e4f660 17#include <linux/cpu.h>
1da177e4
LT
18#include <linux/errno.h>
19#include <linux/sched.h>
6612538c 20#include <linux/fs.h>
1da177e4
LT
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/elfcore.h>
24#include <linux/smp.h>
25#include <linux/slab.h>
26#include <linux/user.h>
1da177e4
LT
27#include <linux/interrupt.h>
28#include <linux/delay.h>
6612538c 29#include <linux/module.h>
1da177e4 30#include <linux/ptrace.h>
95833c83 31#include <linux/notifier.h>
c6fd91f0 32#include <linux/kprobes.h>
1eeb66a1 33#include <linux/kdebug.h>
529e25f6 34#include <linux/prctl.h>
7de08b4e
GP
35#include <linux/uaccess.h>
36#include <linux/io.h>
8b96f011 37#include <linux/ftrace.h>
1da177e4 38
1da177e4 39#include <asm/pgtable.h>
1da177e4
LT
40#include <asm/processor.h>
41#include <asm/i387.h>
1361b83a 42#include <asm/fpu-internal.h>
1da177e4 43#include <asm/mmu_context.h>
1da177e4 44#include <asm/prctl.h>
1da177e4
LT
45#include <asm/desc.h>
46#include <asm/proto.h>
47#include <asm/ia32.h>
95833c83 48#include <asm/idle.h>
bbc1f698 49#include <asm/syscalls.h>
66cb5917 50#include <asm/debugreg.h>
f05e798a 51#include <asm/switch_to.h>
1da177e4
LT
52
53asmlinkage extern void ret_from_fork(void);
54
3d1e42a7 55DEFINE_PER_CPU(unsigned long, old_rsp);
1da177e4 56
6612538c 57/* Prints also some state that isn't saved in the pt_regs */
e2ce07c8 58void __show_regs(struct pt_regs *regs, int all)
1da177e4
LT
59{
60 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
bb1995d5 61 unsigned long d0, d1, d2, d3, d6, d7;
6612538c
HS
62 unsigned int fsindex, gsindex;
63 unsigned int ds, cs, es;
814e2c84
AI
64
65 show_regs_common();
d015a092 66 printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
aafbd7eb 67 printk_address(regs->ip, 1);
d015a092 68 printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss,
8092c654 69 regs->sp, regs->flags);
d015a092 70 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
65ea5b03 71 regs->ax, regs->bx, regs->cx);
d015a092 72 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
65ea5b03 73 regs->dx, regs->si, regs->di);
d015a092 74 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
65ea5b03 75 regs->bp, regs->r8, regs->r9);
d015a092 76 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
7de08b4e 77 regs->r10, regs->r11, regs->r12);
d015a092 78 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
7de08b4e 79 regs->r13, regs->r14, regs->r15);
1da177e4 80
7de08b4e
GP
81 asm("movl %%ds,%0" : "=r" (ds));
82 asm("movl %%cs,%0" : "=r" (cs));
83 asm("movl %%es,%0" : "=r" (es));
1da177e4
LT
84 asm("movl %%fs,%0" : "=r" (fsindex));
85 asm("movl %%gs,%0" : "=r" (gsindex));
86
87 rdmsrl(MSR_FS_BASE, fs);
7de08b4e
GP
88 rdmsrl(MSR_GS_BASE, gs);
89 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
1da177e4 90
e2ce07c8
PE
91 if (!all)
92 return;
1da177e4 93
f51c9452
GOC
94 cr0 = read_cr0();
95 cr2 = read_cr2();
96 cr3 = read_cr3();
97 cr4 = read_cr4();
1da177e4 98
d015a092 99 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
7de08b4e 100 fs, fsindex, gs, gsindex, shadowgs);
d015a092 101 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
8092c654 102 es, cr0);
d015a092 103 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
8092c654 104 cr4);
bb1995d5
AS
105
106 get_debugreg(d0, 0);
107 get_debugreg(d1, 1);
108 get_debugreg(d2, 2);
d015a092 109 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
bb1995d5
AS
110 get_debugreg(d3, 3);
111 get_debugreg(d6, 6);
112 get_debugreg(d7, 7);
d015a092 113 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
1da177e4
LT
114}
115
1da177e4
LT
116void release_thread(struct task_struct *dead_task)
117{
118 if (dead_task->mm) {
119 if (dead_task->mm->context.size) {
c767a54b
JP
120 pr_warn("WARNING: dead process %8s still has LDT? <%p/%d>\n",
121 dead_task->comm,
122 dead_task->mm->context.ldt,
123 dead_task->mm->context.size);
1da177e4
LT
124 BUG();
125 }
126 }
127}
128
129static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
130{
6612538c 131 struct user_desc ud = {
1da177e4
LT
132 .base_addr = addr,
133 .limit = 0xfffff,
134 .seg_32bit = 1,
135 .limit_in_pages = 1,
136 .useable = 1,
137 };
ade1af77 138 struct desc_struct *desc = t->thread.tls_array;
1da177e4 139 desc += tls;
80fbb69a 140 fill_ldt(desc, &ud);
1da177e4
LT
141}
142
143static inline u32 read_32bit_tls(struct task_struct *t, int tls)
144{
91394eb0 145 return get_desc_base(&t->thread.tls_array[tls]);
1da177e4
LT
146}
147
6f2c55b8 148int copy_thread(unsigned long clone_flags, unsigned long sp,
1da177e4 149 unsigned long unused,
7de08b4e 150 struct task_struct *p, struct pt_regs *regs)
1da177e4
LT
151{
152 int err;
7de08b4e 153 struct pt_regs *childregs;
1da177e4
LT
154 struct task_struct *me = current;
155
a88cde13 156 childregs = ((struct pt_regs *)
57eafdc2 157 (THREAD_SIZE + task_stack_page(p))) - 1;
1da177e4
LT
158 *childregs = *regs;
159
65ea5b03 160 childregs->ax = 0;
fa4b8f84
BG
161 if (user_mode(regs))
162 childregs->sp = sp;
163 else
65ea5b03 164 childregs->sp = (unsigned long)childregs;
1da177e4 165
faca6227
PA
166 p->thread.sp = (unsigned long) childregs;
167 p->thread.sp0 = (unsigned long) (childregs+1);
168 p->thread.usersp = me->thread.usersp;
1da177e4 169
e4f17c43 170 set_tsk_thread_flag(p, TIF_FORK);
1da177e4 171
cea20ca3 172 p->fpu_counter = 0;
66cb5917 173 p->thread.io_bitmap_ptr = NULL;
1da177e4 174
ada85708 175 savesegment(gs, p->thread.gsindex);
7ce5a2b9 176 p->thread.gs = p->thread.gsindex ? 0 : me->thread.gs;
ada85708 177 savesegment(fs, p->thread.fsindex);
7ce5a2b9 178 p->thread.fs = p->thread.fsindex ? 0 : me->thread.fs;
ada85708
JF
179 savesegment(es, p->thread.es);
180 savesegment(ds, p->thread.ds);
1da177e4 181
66cb5917 182 err = -ENOMEM;
24f1e32c 183 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
66cb5917 184
d3a4f48d 185 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
cced4022
TM
186 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
187 IO_BITMAP_BYTES, GFP_KERNEL);
1da177e4
LT
188 if (!p->thread.io_bitmap_ptr) {
189 p->thread.io_bitmap_max = 0;
190 return -ENOMEM;
191 }
d3a4f48d 192 set_tsk_thread_flag(p, TIF_IO_BITMAP);
6612538c 193 }
1da177e4
LT
194
195 /*
196 * Set a new TLS for the child thread?
197 */
198 if (clone_flags & CLONE_SETTLS) {
199#ifdef CONFIG_IA32_EMULATION
200 if (test_thread_flag(TIF_IA32))
efd1ca52 201 err = do_set_thread_area(p, -1,
65ea5b03 202 (struct user_desc __user *)childregs->si, 0);
7de08b4e
GP
203 else
204#endif
205 err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8);
206 if (err)
1da177e4
LT
207 goto out;
208 }
209 err = 0;
210out:
211 if (err && p->thread.io_bitmap_ptr) {
212 kfree(p->thread.io_bitmap_ptr);
213 p->thread.io_bitmap_max = 0;
214 }
66cb5917 215
1da177e4
LT
216 return err;
217}
218
e634d8fc
PA
219static void
220start_thread_common(struct pt_regs *regs, unsigned long new_ip,
221 unsigned long new_sp,
222 unsigned int _cs, unsigned int _ss, unsigned int _ds)
513ad84b 223{
ada85708 224 loadsegment(fs, 0);
e634d8fc
PA
225 loadsegment(es, _ds);
226 loadsegment(ds, _ds);
513ad84b 227 load_gs_index(0);
42dfc43e 228 current->thread.usersp = new_sp;
513ad84b
IM
229 regs->ip = new_ip;
230 regs->sp = new_sp;
c6ae41e7 231 this_cpu_write(old_rsp, new_sp);
e634d8fc
PA
232 regs->cs = _cs;
233 regs->ss = _ss;
a6f05a6a 234 regs->flags = X86_EFLAGS_IF;
aa283f49
SS
235 /*
236 * Free the old FP and other extended state
237 */
238 free_thread_xstate(current);
513ad84b 239}
e634d8fc
PA
240
241void
242start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
243{
244 start_thread_common(regs, new_ip, new_sp,
245 __USER_CS, __USER_DS, 0);
246}
513ad84b 247
a6f05a6a
PA
248#ifdef CONFIG_IA32_EMULATION
249void start_thread_ia32(struct pt_regs *regs, u32 new_ip, u32 new_sp)
250{
e634d8fc 251 start_thread_common(regs, new_ip, new_sp,
d1a797f3
PA
252 test_thread_flag(TIF_X32)
253 ? __USER_CS : __USER32_CS,
254 __USER_DS, __USER_DS);
a6f05a6a
PA
255}
256#endif
513ad84b 257
1da177e4
LT
258/*
259 * switch_to(x,y) should switch tasks from x to y.
260 *
6612538c 261 * This could still be optimized:
1da177e4
LT
262 * - fold all the options into a flag word and test it with a single test.
263 * - could test fs/gs bitsliced
099f318b
AK
264 *
265 * Kprobes not supported here. Set the probe on schedule instead.
8b96f011 266 * Function graph tracer not supported too.
1da177e4 267 */
8b96f011 268__notrace_funcgraph struct task_struct *
a88cde13 269__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
1da177e4 270{
87b935a0
JF
271 struct thread_struct *prev = &prev_p->thread;
272 struct thread_struct *next = &next_p->thread;
6612538c 273 int cpu = smp_processor_id();
1da177e4 274 struct tss_struct *tss = &per_cpu(init_tss, cpu);
478de5a9 275 unsigned fsindex, gsindex;
34ddc81a 276 fpu_switch_t fpu;
e07e23e1 277
7e16838d 278 fpu = switch_fpu_prepare(prev_p, next_p, cpu);
4903062b 279
1da177e4
LT
280 /*
281 * Reload esp0, LDT and the page table pointer:
282 */
7818a1e0 283 load_sp0(tss, next);
1da177e4 284
7de08b4e 285 /*
1da177e4
LT
286 * Switch DS and ES.
287 * This won't pick up thread selector changes, but I guess that is ok.
288 */
ada85708 289 savesegment(es, prev->es);
1da177e4 290 if (unlikely(next->es | prev->es))
7de08b4e 291 loadsegment(es, next->es);
ada85708
JF
292
293 savesegment(ds, prev->ds);
1da177e4
LT
294 if (unlikely(next->ds | prev->ds))
295 loadsegment(ds, next->ds);
296
478de5a9
JF
297
298 /* We must save %fs and %gs before load_TLS() because
299 * %fs and %gs may be cleared by load_TLS().
300 *
301 * (e.g. xen_load_tls())
302 */
303 savesegment(fs, fsindex);
304 savesegment(gs, gsindex);
305
1da177e4
LT
306 load_TLS(next, cpu);
307
3fe0a63e
JF
308 /*
309 * Leave lazy mode, flushing any hypercalls made here.
310 * This must be done before restoring TLS segments so
311 * the GDT and LDT are properly updated, and must be
312 * done before math_state_restore, so the TS bit is up
313 * to date.
314 */
224101ed 315 arch_end_context_switch(next_p);
3fe0a63e 316
7de08b4e 317 /*
1da177e4 318 * Switch FS and GS.
87b935a0
JF
319 *
320 * Segment register != 0 always requires a reload. Also
321 * reload when it has changed. When prev process used 64bit
322 * base always reload to avoid an information leak.
1da177e4 323 */
87b935a0
JF
324 if (unlikely(fsindex | next->fsindex | prev->fs)) {
325 loadsegment(fs, next->fsindex);
7de08b4e 326 /*
87b935a0
JF
327 * Check if the user used a selector != 0; if yes
328 * clear 64bit base, since overloaded base is always
329 * mapped to the Null selector
330 */
331 if (fsindex)
7de08b4e 332 prev->fs = 0;
1da177e4 333 }
87b935a0
JF
334 /* when next process has a 64bit base use it */
335 if (next->fs)
336 wrmsrl(MSR_FS_BASE, next->fs);
337 prev->fsindex = fsindex;
338
339 if (unlikely(gsindex | next->gsindex | prev->gs)) {
340 load_gs_index(next->gsindex);
341 if (gsindex)
7de08b4e 342 prev->gs = 0;
1da177e4 343 }
87b935a0
JF
344 if (next->gs)
345 wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
346 prev->gsindex = gsindex;
1da177e4 347
34ddc81a
LT
348 switch_fpu_finish(next_p, fpu);
349
7de08b4e 350 /*
45948d77 351 * Switch the PDA and FPU contexts.
1da177e4 352 */
c6ae41e7
AS
353 prev->usersp = this_cpu_read(old_rsp);
354 this_cpu_write(old_rsp, next->usersp);
355 this_cpu_write(current_task, next_p);
18bd057b 356
c6ae41e7 357 this_cpu_write(kernel_stack,
87b935a0 358 (unsigned long)task_stack_page(next_p) +
9af45651 359 THREAD_SIZE - KERNEL_STACK_OFFSET);
1da177e4
LT
360
361 /*
d3a4f48d 362 * Now maybe reload the debug registers and handle I/O bitmaps
1da177e4 363 */
eee3af4a
MM
364 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
365 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
d3a4f48d 366 __switch_to_xtra(prev_p, next_p, tss);
1da177e4
LT
367
368 return prev_p;
369}
370
1da177e4
LT
371void set_personality_64bit(void)
372{
373 /* inherit personality from parent */
374
375 /* Make sure to be in 64bit mode */
6612538c 376 clear_thread_flag(TIF_IA32);
6bd33008 377 clear_thread_flag(TIF_ADDR32);
bb212724 378 clear_thread_flag(TIF_X32);
1da177e4 379
375906f8
SW
380 /* Ensure the corresponding mm is not marked. */
381 if (current->mm)
382 current->mm->context.ia32_compat = 0;
383
1da177e4
LT
384 /* TBD: overwrites user setup. Should have two bits.
385 But 64bit processes have always behaved this way,
386 so it's not too bad. The main problem is just that
6612538c 387 32bit childs are affected again. */
1da177e4
LT
388 current->personality &= ~READ_IMPLIES_EXEC;
389}
390
d1a797f3 391void set_personality_ia32(bool x32)
05d43ed8
PA
392{
393 /* inherit personality from parent */
394
395 /* Make sure to be in 32bit mode */
6bd33008 396 set_thread_flag(TIF_ADDR32);
05d43ed8 397
375906f8
SW
398 /* Mark the associated mm as containing 32-bit tasks. */
399 if (current->mm)
400 current->mm->context.ia32_compat = 1;
401
d1a797f3
PA
402 if (x32) {
403 clear_thread_flag(TIF_IA32);
404 set_thread_flag(TIF_X32);
405 current->personality &= ~READ_IMPLIES_EXEC;
ce5f7a99
BP
406 /* is_compat_task() uses the presence of the x32
407 syscall bit flag to determine compat status */
408 current_thread_info()->status &= ~TS_COMPAT;
d1a797f3
PA
409 } else {
410 set_thread_flag(TIF_IA32);
411 clear_thread_flag(TIF_X32);
412 current->personality |= force_personality32;
413 /* Prepare the first "return" to user space */
414 current_thread_info()->status |= TS_COMPAT;
415 }
05d43ed8 416}
febb72a6 417EXPORT_SYMBOL_GPL(set_personality_ia32);
05d43ed8 418
1da177e4
LT
419unsigned long get_wchan(struct task_struct *p)
420{
421 unsigned long stack;
7de08b4e 422 u64 fp, ip;
1da177e4
LT
423 int count = 0;
424
7de08b4e
GP
425 if (!p || p == current || p->state == TASK_RUNNING)
426 return 0;
57eafdc2 427 stack = (unsigned long)task_stack_page(p);
e1e23bb0 428 if (p->thread.sp < stack || p->thread.sp >= stack+THREAD_SIZE)
1da177e4 429 return 0;
faca6227 430 fp = *(u64 *)(p->thread.sp);
7de08b4e 431 do {
a88cde13 432 if (fp < (unsigned long)stack ||
e1e23bb0 433 fp >= (unsigned long)stack+THREAD_SIZE)
7de08b4e 434 return 0;
65ea5b03
PA
435 ip = *(u64 *)(fp+8);
436 if (!in_sched_functions(ip))
437 return ip;
7de08b4e
GP
438 fp = *(u64 *)fp;
439 } while (count++ < 16);
1da177e4
LT
440 return 0;
441}
442
443long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
7de08b4e
GP
444{
445 int ret = 0;
1da177e4
LT
446 int doit = task == current;
447 int cpu;
448
7de08b4e 449 switch (code) {
1da177e4 450 case ARCH_SET_GS:
84929801 451 if (addr >= TASK_SIZE_OF(task))
7de08b4e 452 return -EPERM;
1da177e4 453 cpu = get_cpu();
7de08b4e 454 /* handle small bases via the GDT because that's faster to
1da177e4 455 switch. */
7de08b4e
GP
456 if (addr <= 0xffffffff) {
457 set_32bit_tls(task, GS_TLS, addr);
458 if (doit) {
1da177e4 459 load_TLS(&task->thread, cpu);
7de08b4e 460 load_gs_index(GS_TLS_SEL);
1da177e4 461 }
7de08b4e 462 task->thread.gsindex = GS_TLS_SEL;
1da177e4 463 task->thread.gs = 0;
7de08b4e 464 } else {
1da177e4
LT
465 task->thread.gsindex = 0;
466 task->thread.gs = addr;
467 if (doit) {
a88cde13 468 load_gs_index(0);
715c85b1 469 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
7de08b4e 470 }
1da177e4
LT
471 }
472 put_cpu();
473 break;
474 case ARCH_SET_FS:
475 /* Not strictly needed for fs, but do it for symmetry
476 with gs */
84929801 477 if (addr >= TASK_SIZE_OF(task))
6612538c 478 return -EPERM;
1da177e4 479 cpu = get_cpu();
6612538c 480 /* handle small bases via the GDT because that's faster to
1da177e4 481 switch. */
6612538c 482 if (addr <= 0xffffffff) {
1da177e4 483 set_32bit_tls(task, FS_TLS, addr);
6612538c
HS
484 if (doit) {
485 load_TLS(&task->thread, cpu);
ada85708 486 loadsegment(fs, FS_TLS_SEL);
1da177e4
LT
487 }
488 task->thread.fsindex = FS_TLS_SEL;
489 task->thread.fs = 0;
6612538c 490 } else {
1da177e4
LT
491 task->thread.fsindex = 0;
492 task->thread.fs = addr;
493 if (doit) {
494 /* set the selector to 0 to not confuse
495 __switch_to */
ada85708 496 loadsegment(fs, 0);
715c85b1 497 ret = wrmsrl_safe(MSR_FS_BASE, addr);
1da177e4
LT
498 }
499 }
500 put_cpu();
501 break;
6612538c
HS
502 case ARCH_GET_FS: {
503 unsigned long base;
1da177e4
LT
504 if (task->thread.fsindex == FS_TLS_SEL)
505 base = read_32bit_tls(task, FS_TLS);
a88cde13 506 else if (doit)
1da177e4 507 rdmsrl(MSR_FS_BASE, base);
a88cde13 508 else
1da177e4 509 base = task->thread.fs;
6612538c
HS
510 ret = put_user(base, (unsigned long __user *)addr);
511 break;
1da177e4 512 }
6612538c 513 case ARCH_GET_GS: {
1da177e4 514 unsigned long base;
97c2803c 515 unsigned gsindex;
1da177e4
LT
516 if (task->thread.gsindex == GS_TLS_SEL)
517 base = read_32bit_tls(task, GS_TLS);
97c2803c 518 else if (doit) {
ada85708 519 savesegment(gs, gsindex);
97c2803c
JB
520 if (gsindex)
521 rdmsrl(MSR_KERNEL_GS_BASE, base);
522 else
523 base = task->thread.gs;
7de08b4e 524 } else
1da177e4 525 base = task->thread.gs;
6612538c 526 ret = put_user(base, (unsigned long __user *)addr);
1da177e4
LT
527 break;
528 }
529
530 default:
531 ret = -EINVAL;
532 break;
6612538c 533 }
1da177e4 534
6612538c
HS
535 return ret;
536}
1da177e4
LT
537
538long sys_arch_prctl(int code, unsigned long addr)
539{
540 return do_arch_prctl(current, code, addr);
1da177e4
LT
541}
542
89240ba0
SS
543unsigned long KSTK_ESP(struct task_struct *task)
544{
545 return (test_tsk_thread_flag(task, TIF_IA32)) ?
546 (task_pt_regs(task)->sp) : ((task)->thread.usersp);
547}