[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / smp.c

/*
 *	Intel SMP support routines.
 *
 *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
 *	(c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
 *      (c) 2002,2003 Andi Kleen, SuSE Labs.
 *
 *	i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
 *
 *	This code is released under the GNU General Public License version 2 or
 *	later.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/export.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/gfp.h>

#include <asm/mtrr.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/proto.h>
#include <asm/apic.h>
#include <asm/nmi.h>
#include <asm/trace/irq_vectors.h>
/*
 *	Some notes on x86 processor bugs affecting SMP operation:
 *
 *	Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
 *	The Linux implications for SMP are handled as follows:
 *
 *	Pentium III / [Xeon]
 *		None of the E1AP-E3AP errata are visible to the user.
 *
 *	E1AP.	see PII A1AP
 *	E2AP.	see PII A2AP
 *	E3AP.	see PII A3AP
 *
 *	Pentium II / [Xeon]
 *		None of the A1AP-A3AP errata are visible to the user.
 *
 *	A1AP.	see PPro 1AP
 *	A2AP.	see PPro 2AP
 *	A3AP.	see PPro 7AP
 *
 *	Pentium Pro
 *		None of 1AP-9AP errata are visible to the normal user,
 *	except occasional delivery of 'spurious interrupt' as trap #15.
 *	This is very rare and a non-problem.
 *
 *	1AP.	Linux maps APIC as non-cacheable
 *	2AP.	worked around in hardware
 *	3AP.	fixed in C0 and above steppings microcode update.
 *		Linux does not use excessive STARTUP_IPIs.
 *	4AP.	worked around in hardware
 *	5AP.	symmetric IO mode (normal Linux operation) not affected.
 *		'noapic' mode has vector 0xf filled out properly.
 *	6AP.	'noapic' mode might be affected - fixed in later steppings
 *	7AP.	We do not assume writes to the LVT deassering IRQs
 *	8AP.	We do not enable low power mode (deep sleep) during MP bootup
 *	9AP.	We do not use mixed mode
 *
 *	Pentium
 *		There is a marginal case where REP MOVS on 100MHz SMP
 *	machines with B stepping processors can fail. XXX should provide
 *	an L1cache=Writethrough or L1cache=off option.
 *
 *		B stepping CPUs may hang. There are hardware work arounds
 *	for this. We warn about it in case your board doesn't have the work
 *	arounds. Basically that's so I can tell anyone with a B stepping
 *	CPU and SMP problems "tough".
 *
 *	Specific items [From Pentium Processor Specification Update]
 *
 *	1AP.	Linux doesn't use remote read
 *	2AP.	Linux doesn't trust APIC errors
 *	3AP.	We work around this
 *	4AP.	Linux never generated 3 interrupts of the same priority
 *		to cause a lost local interrupt.
 *	5AP.	Remote read is never used
 *	6AP.	not affected - worked around in hardware
 *	7AP.	not affected - worked around in hardware
 *	8AP.	worked around in hardware - we get explicit CS errors if not
 *	9AP.	only 'noapic' mode affected. Might generate spurious
 *		interrupts, we log only the first one and count the
 *		rest silently.
 *	10AP.	not affected - worked around in hardware
 *	11AP.	Linux reads the APIC between writes to avoid this, as per
 *		the documentation. Make sure you preserve this as it affects
 *		the C stepping chips too.
 *	12AP.	not affected - worked around in hardware
 *	13AP.	not affected - worked around in hardware
 *	14AP.	we always deassert INIT during bootup
 *	15AP.	not affected - worked around in hardware
 *	16AP.	not affected - worked around in hardware
 *	17AP.	not affected - worked around in hardware
 *	18AP.	not affected - worked around in hardware
 *	19AP.	not affected - worked around in BIOS
 *
 *	If this sounds worrying believe me these bugs are either ___RARE___,
 *	or are signal timing bugs worked around in hardware and there's
 *	about nothing of note with C stepping upwards.
 */

static atomic_t stopping_cpu = ATOMIC_INIT(-1);
static bool smp_no_nmi_ipi = false;

/*
 * this function sends a 'reschedule' IPI to another CPU.
 * it goes straight through and wastes no time serializing
 * anything. Worst case is that we lose a reschedule ...
 */
static void native_smp_send_reschedule(int cpu)
{
	if (unlikely(cpu_is_offline(cpu))) {
		WARN_ON(1);
		return;
	}
	apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
}

void native_send_call_func_single_ipi(int cpu)
{
	apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
}

void native_send_call_func_ipi(const struct cpumask *mask)
{
	cpumask_var_t allbutself;

	if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
		apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
		return;
	}

	cpumask_copy(allbutself, cpu_online_mask);
	cpumask_clear_cpu(smp_processor_id(), allbutself);

	if (cpumask_equal(mask, allbutself) &&
	    cpumask_equal(cpu_online_mask, cpu_callout_mask))
		apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
	else
		apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);

	free_cpumask_var(allbutself);
}

static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
{
	/* We are registered on stopping cpu too, avoid spurious NMI */
	if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
		return NMI_HANDLED;

	stop_this_cpu(NULL);

	return NMI_HANDLED;
}

/*
 * this function calls the 'stop' function on all other CPUs in the system.
 */

asmlinkage __visible void smp_reboot_interrupt(void)
{
	ack_APIC_irq();
	irq_enter();
	stop_this_cpu(NULL);
	irq_exit();
}

static void native_stop_other_cpus(int wait)
{
	unsigned long flags;
	unsigned long timeout;

	if (reboot_force)
		return;

	/*
	 * Use an own vector here because smp_call_function
	 * does lots of things not suitable in a panic situation.
	 */

	/*
	 * We start by using the REBOOT_VECTOR irq.
	 * The irq is treated as a sync point to allow critical
	 * regions of code on other cpus to release their spin locks
	 * and re-enable irqs.  Jumping straight to an NMI might
	 * accidentally cause deadlocks with further shutdown/panic
	 * code.  By syncing, we give the cpus up to one second to
	 * finish their work before we force them off with the NMI.
	 */
	if (num_online_cpus() > 1) {
		/* did someone beat us here? */
		if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
			return;

		/* sync above data before sending IRQ */
		wmb();

		apic->send_IPI_allbutself(REBOOT_VECTOR);

		/*
		 * Don't wait longer than a second if the caller
		 * didn't ask us to wait.
		 */
		timeout = USEC_PER_SEC;
		while (num_online_cpus() > 1 && (wait || timeout--))
			udelay(1);
	}
	
	/* if the REBOOT_VECTOR didn't work, try with the NMI */
	if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi))  {
		if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
					 NMI_FLAG_FIRST, "smp_stop"))
			/* Note: we ignore failures here */
			/* Hope the REBOOT_IRQ is good enough */
			goto finish;

		/* sync above data before sending IRQ */
		wmb();

		pr_emerg("Shutting down cpus with NMI\n");

		apic->send_IPI_allbutself(NMI_VECTOR);

		/*
		 * Don't wait longer than a 10 ms if the caller
		 * didn't ask us to wait.
		 */
		timeout = USEC_PER_MSEC * 10;
		while (num_online_cpus() > 1 && (wait || timeout--))
			udelay(1);
	}

finish:
	local_irq_save(flags);
	disable_local_APIC();
	local_irq_restore(flags);
}

/*
 * Reschedule call back.
 */
static inline void __smp_reschedule_interrupt(void)
{
	inc_irq_stat(irq_resched_count);
	scheduler_ipi();
}

__visible void smp_reschedule_interrupt(struct pt_regs *regs)
{
	ack_APIC_irq();
	__smp_reschedule_interrupt();
	/*
	 * KVM uses this interrupt to force a cpu out of guest mode
	 */
}

static inline void smp_entering_irq(void)
{
	ack_APIC_irq();
	irq_enter();
}

__visible void smp_trace_reschedule_interrupt(struct pt_regs *regs)
{
	/*
	 * Need to call irq_enter() before calling the trace point.
	 * __smp_reschedule_interrupt() calls irq_enter/exit() too (in
	 * scheduler_ipi(). This is OK, since those functions are allowed
	 * to nest.
	 */
	smp_entering_irq();
	trace_reschedule_entry(RESCHEDULE_VECTOR);
	__smp_reschedule_interrupt();
	trace_reschedule_exit(RESCHEDULE_VECTOR);
	exiting_irq();
	/*
	 * KVM uses this interrupt to force a cpu out of guest mode
	 */
}

static inline void __smp_call_function_interrupt(void)
{
	generic_smp_call_function_interrupt();
	inc_irq_stat(irq_call_count);
}

__visible void smp_call_function_interrupt(struct pt_regs *regs)
{
	smp_entering_irq();
	__smp_call_function_interrupt();
	exiting_irq();
}

__visible void smp_trace_call_function_interrupt(struct pt_regs *regs)
{
	smp_entering_irq();
	trace_call_function_entry(CALL_FUNCTION_VECTOR);
	__smp_call_function_interrupt();
	trace_call_function_exit(CALL_FUNCTION_VECTOR);
	exiting_irq();
}

static inline void __smp_call_function_single_interrupt(void)
{
	generic_smp_call_function_single_interrupt();
	inc_irq_stat(irq_call_count);
}

__visible void smp_call_function_single_interrupt(struct pt_regs *regs)
{
	smp_entering_irq();
	__smp_call_function_single_interrupt();
	exiting_irq();
}

__visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs)
{
	smp_entering_irq();
	trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
	__smp_call_function_single_interrupt();
	trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
	exiting_irq();
}

static int __init nonmi_ipi_setup(char *str)
{
	smp_no_nmi_ipi = true;
	return 1;
}

__setup("nonmi_ipi", nonmi_ipi_setup);

struct smp_ops smp_ops = {
	.smp_prepare_boot_cpu	= native_smp_prepare_boot_cpu,
	.smp_prepare_cpus	= native_smp_prepare_cpus,
	.smp_cpus_done		= native_smp_cpus_done,

	.stop_other_cpus	= native_stop_other_cpus,
	.smp_send_reschedule	= native_smp_send_reschedule,

	.cpu_up			= native_cpu_up,
	.cpu_die		= native_cpu_die,
	.cpu_disable		= native_cpu_disable,
	.play_dead		= native_play_dead,

	.send_call_func_ipi	= native_send_call_func_ipi,
	.send_call_func_single_ipi = native_send_call_func_single_ipi,
};
EXPORT_SYMBOL_GPL(smp_ops);
Commit	Line	Data
0941ecb5 GC	1	/*
	2	* Intel SMP support routines.
	3	*
87c6fe26	4	* (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
8f47e163	5	* (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
0941ecb5 GC	6	* (c) 2002,2003 Andi Kleen, SuSE Labs.
	7	*
	8	* i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
	9	*
	10	* This code is released under the GNU General Public License version 2 or
	11	* later.
	12	*/
	13
f9e47a12 GC	14	#include <linux/init.h>
	15
	16	#include <linux/mm.h>
	17	#include <linux/delay.h>
	18	#include <linux/spinlock.h>
69c60c88	19	#include <linux/export.h>
f9e47a12 GC	20	#include <linux/kernel_stat.h>
	21	#include <linux/mc146818rtc.h>
	22	#include <linux/cache.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/cpu.h>
5a0e3ad6	25	#include <linux/gfp.h>
f9e47a12 GC	26
	27	#include <asm/mtrr.h>
	28	#include <asm/tlbflush.h>
	29	#include <asm/mmu_context.h>
	30	#include <asm/proto.h>
7b6aa335	31	#include <asm/apic.h>
7d007d21	32	#include <asm/nmi.h>
cf910e83	33	#include <asm/trace/irq_vectors.h>
0941ecb5 GC	34	/*
	35	* Some notes on x86 processor bugs affecting SMP operation:
	36	*
	37	* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
	38	* The Linux implications for SMP are handled as follows:
	39	*
	40	* Pentium III / [Xeon]
	41	* None of the E1AP-E3AP errata are visible to the user.
	42	*
	43	* E1AP. see PII A1AP
	44	* E2AP. see PII A2AP
	45	* E3AP. see PII A3AP
	46	*
	47	* Pentium II / [Xeon]
	48	* None of the A1AP-A3AP errata are visible to the user.
	49	*
	50	* A1AP. see PPro 1AP
	51	* A2AP. see PPro 2AP
	52	* A3AP. see PPro 7AP
	53	*
	54	* Pentium Pro
	55	* None of 1AP-9AP errata are visible to the normal user,
	56	* except occasional delivery of 'spurious interrupt' as trap #15.
	57	* This is very rare and a non-problem.
	58	*
	59	* 1AP. Linux maps APIC as non-cacheable
	60	* 2AP. worked around in hardware
	61	* 3AP. fixed in C0 and above steppings microcode update.
	62	* Linux does not use excessive STARTUP_IPIs.
	63	* 4AP. worked around in hardware
	64	* 5AP. symmetric IO mode (normal Linux operation) not affected.
	65	* 'noapic' mode has vector 0xf filled out properly.
	66	* 6AP. 'noapic' mode might be affected - fixed in later steppings
	67	* 7AP. We do not assume writes to the LVT deassering IRQs
	68	* 8AP. We do not enable low power mode (deep sleep) during MP bootup
	69	* 9AP. We do not use mixed mode
	70	*
	71	* Pentium
	72	* There is a marginal case where REP MOVS on 100MHz SMP
	73	* machines with B stepping processors can fail. XXX should provide
	74	* an L1cache=Writethrough or L1cache=off option.
	75	*
	76	* B stepping CPUs may hang. There are hardware work arounds
	77	* for this. We warn about it in case your board doesn't have the work
	78	* arounds. Basically that's so I can tell anyone with a B stepping
	79	* CPU and SMP problems "tough".
	80	*
	81	* Specific items [From Pentium Processor Specification Update]
	82	*
	83	* 1AP. Linux doesn't use remote read
	84	* 2AP. Linux doesn't trust APIC errors
	85	* 3AP. We work around this
	86	* 4AP. Linux never generated 3 interrupts of the same priority
	87	* to cause a lost local interrupt.
	88	* 5AP. Remote read is never used
	89	* 6AP. not affected - worked around in hardware
	90	* 7AP. not affected - worked around in hardware
	91	* 8AP. worked around in hardware - we get explicit CS errors if not
	92	* 9AP. only 'noapic' mode affected. Might generate spurious
	93	* interrupts, we log only the first one and count the
	94	* rest silently.
	95	* 10AP. not affected - worked around in hardware
	96	* 11AP. Linux reads the APIC between writes to avoid this, as per
	97	* the documentation. Make sure you preserve this as it affects
98	* the C stepping chips too.
99	* 12AP. not affected - worked around in hardware
100	* 13AP. not affected - worked around in hardware
101	* 14AP. we always deassert INIT during bootup
102	* 15AP. not affected - worked around in hardware
103	* 16AP. not affected - worked around in hardware
104	* 17AP. not affected - worked around in hardware
105	* 18AP. not affected - worked around in hardware
106	* 19AP. not affected - worked around in BIOS
107	*
108	* If this sounds worrying believe me these bugs are either ___RARE___,
109	* or are signal timing bugs worked around in hardware and there's
110	* about nothing of note with C stepping upwards.
111	*/
f9e47a12	112
7d007d21	113	static atomic_t stopping_cpu = ATOMIC_INIT(-1);
3aac27ab	114	static bool smp_no_nmi_ipi = false;
7d007d21	115
f9e47a12 GC	116	/*
	117	* this function sends a 'reschedule' IPI to another CPU.
	118	* it goes straight through and wastes no time serializing
	119	* anything. Worst case is that we lose a reschedule ...
	120	*/
	121	static void native_smp_send_reschedule(int cpu)
	122	{
f6940101 GS	123	if (unlikely(cpu_is_offline(cpu))) {
	124	WARN_ON(1);
	125	return;
	126	}
dac5f412	127	apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
f9e47a12 GC	128	}
f9e47a12 GC	129
3b16cf87	130	void native_send_call_func_single_ipi(int cpu)
f9e47a12	131	{
dac5f412	132	apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
f9e47a12 GC	133	}
f9e47a12 GC	134
bcda016e	135	void native_send_call_func_ipi(const struct cpumask *mask)
f9e47a12	136	{
c2d1cec1	137	cpumask_var_t allbutself;
f9e47a12	138
c2d1cec1	139	if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
dac5f412	140	apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
c2d1cec1 MT	141	return;
c2d1cec1 MT	142	}
f9e47a12	143
c2d1cec1 MT	144	cpumask_copy(allbutself, cpu_online_mask);
	145	cpumask_clear_cpu(smp_processor_id(), allbutself);
	146
	147	if (cpumask_equal(mask, allbutself) &&
	148	cpumask_equal(cpu_online_mask, cpu_callout_mask))
dac5f412	149	apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
f9e47a12	150	else
dac5f412	151	apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
c2d1cec1 MT	152
c2d1cec1 MT	153	free_cpumask_var(allbutself);
f9e47a12 GC	154	}
f9e47a12 GC	155
7d007d21 DZ	156	static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
	157	{
	158	/* We are registered on stopping cpu too, avoid spurious NMI */
	159	if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
	160	return NMI_HANDLED;
	161
	162	stop_this_cpu(NULL);
	163
	164	return NMI_HANDLED;
	165	}
	166
f9e47a12 GC	167	/*
	168	* this function calls the 'stop' function on all other CPUs in the system.
	169	*/
	170
2605fc21	171	asmlinkage __visible void smp_reboot_interrupt(void)
4ef702c1 AK	172	{
	173	ack_APIC_irq();
	174	irq_enter();
	175	stop_this_cpu(NULL);
	176	irq_exit();
	177	}
	178
5d2b86d9	179	static void native_stop_other_cpus(int wait)
f9e47a12	180	{
f9e47a12	181	unsigned long flags;
76fac077	182	unsigned long timeout;
f9e47a12 GC	183
	184	if (reboot_force)
	185	return;
	186
4ef702c1 AK	187	/*
	188	* Use an own vector here because smp_call_function
	189	* does lots of things not suitable in a panic situation.
7d007d21 DZ	190	*/
	191
	192	/*
	193	* We start by using the REBOOT_VECTOR irq.
	194	* The irq is treated as a sync point to allow critical
	195	* regions of code on other cpus to release their spin locks
	196	* and re-enable irqs. Jumping straight to an NMI might
	197	* accidentally cause deadlocks with further shutdown/panic
	198	* code. By syncing, we give the cpus up to one second to
	199	* finish their work before we force them off with the NMI.
4ef702c1 AK	200	*/
4ef702c1 AK	201	if (num_online_cpus() > 1) {
7d007d21 DZ	202	/* did someone beat us here? */
	203	if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
	204	return;
	205
	206	/* sync above data before sending IRQ */
	207	wmb();
	208
4ef702c1 AK	209	apic->send_IPI_allbutself(REBOOT_VECTOR);
4ef702c1 AK	210
76fac077 AK	211	/*
	212	* Don't wait longer than a second if the caller
	213	* didn't ask us to wait.
	214	*/
	215	timeout = USEC_PER_SEC;
	216	while (num_online_cpus() > 1 && (wait \|\| timeout--))
4ef702c1 AK	217	udelay(1);
4ef702c1 AK	218	}
7d007d21 DZ	219
7d007d21 DZ	220	/* if the REBOOT_VECTOR didn't work, try with the NMI */
3aac27ab	221	if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi)) {
7d007d21 DZ	222	if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
	223	NMI_FLAG_FIRST, "smp_stop"))
	224	/* Note: we ignore failures here */
	225	/* Hope the REBOOT_IRQ is good enough */
	226	goto finish;
	227
	228	/* sync above data before sending IRQ */
	229	wmb();
	230
	231	pr_emerg("Shutting down cpus with NMI\n");
	232
	233	apic->send_IPI_allbutself(NMI_VECTOR);
	234
	235	/*
	236	* Don't wait longer than a 10 ms if the caller
	237	* didn't ask us to wait.
	238	*/
	239	timeout = USEC_PER_MSEC * 10;
	240	while (num_online_cpus() > 1 && (wait \|\| timeout--))
	241	udelay(1);
	242	}
4ef702c1	243
7d007d21	244	finish:
f9e47a12	245	local_irq_save(flags);
f9e47a12 GC	246	disable_local_APIC();
	247	local_irq_restore(flags);
	248	}
	249
	250	/*
184748cc	251	* Reschedule call back.
f9e47a12	252	*/
eddc0e92	253	static inline void __smp_reschedule_interrupt(void)
f9e47a12	254	{
915b0d01	255	inc_irq_stat(irq_resched_count);
184748cc	256	scheduler_ipi();
eddc0e92 SA	257	}
eddc0e92 SA	258
1d9090e2	259	__visible void smp_reschedule_interrupt(struct pt_regs *regs)
eddc0e92 SA	260	{
	261	ack_APIC_irq();
	262	__smp_reschedule_interrupt();
32f88400 MT	263	/*
	264	* KVM uses this interrupt to force a cpu out of guest mode
	265	*/
f9e47a12 GC	266	}
f9e47a12 GC	267
4787c368	268	static inline void smp_entering_irq(void)
cf910e83 SA	269	{
cf910e83 SA	270	ack_APIC_irq();
4787c368 SA	271	irq_enter();
	272	}
	273
1d9090e2	274	__visible void smp_trace_reschedule_interrupt(struct pt_regs *regs)
4787c368 SA	275	{
	276	/*
	277	* Need to call irq_enter() before calling the trace point.
	278	* __smp_reschedule_interrupt() calls irq_enter/exit() too (in
	279	* scheduler_ipi(). This is OK, since those functions are allowed
	280	* to nest.
	281	*/
	282	smp_entering_irq();
cf910e83 SA	283	trace_reschedule_entry(RESCHEDULE_VECTOR);
	284	__smp_reschedule_interrupt();
	285	trace_reschedule_exit(RESCHEDULE_VECTOR);
4787c368	286	exiting_irq();
cf910e83 SA	287	/*
	288	* KVM uses this interrupt to force a cpu out of guest mode
	289	*/
	290	}
	291
eddc0e92 SA	292	static inline void __smp_call_function_interrupt(void)
eddc0e92 SA	293	{
3b16cf87	294	generic_smp_call_function_interrupt();
915b0d01	295	inc_irq_stat(irq_call_count);
3b16cf87	296	}
f9e47a12	297
1d9090e2	298	__visible void smp_call_function_interrupt(struct pt_regs *regs)
eddc0e92	299	{
4787c368	300	smp_entering_irq();
eddc0e92 SA	301	__smp_call_function_interrupt();
	302	exiting_irq();
	303	}
	304
1d9090e2	305	__visible void smp_trace_call_function_interrupt(struct pt_regs *regs)
cf910e83	306	{
4787c368	307	smp_entering_irq();
cf910e83 SA	308	trace_call_function_entry(CALL_FUNCTION_VECTOR);
	309	__smp_call_function_interrupt();
	310	trace_call_function_exit(CALL_FUNCTION_VECTOR);
	311	exiting_irq();
	312	}
	313
eddc0e92	314	static inline void __smp_call_function_single_interrupt(void)
3b16cf87	315	{
3b16cf87	316	generic_smp_call_function_single_interrupt();
915b0d01	317	inc_irq_stat(irq_call_count);
eddc0e92 SA	318	}
eddc0e92 SA	319
1d9090e2	320	__visible void smp_call_function_single_interrupt(struct pt_regs *regs)
eddc0e92	321	{
4787c368	322	smp_entering_irq();
eddc0e92 SA	323	__smp_call_function_single_interrupt();
eddc0e92 SA	324	exiting_irq();
f9e47a12 GC	325	}
f9e47a12 GC	326
1d9090e2	327	__visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs)
cf910e83	328	{
4787c368	329	smp_entering_irq();
cf910e83 SA	330	trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
	331	__smp_call_function_single_interrupt();
	332	trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
	333	exiting_irq();
	334	}
	335
bda62633 DZ	336	static int __init nonmi_ipi_setup(char *str)
bda62633 DZ	337	{
3aac27ab DZ	338	smp_no_nmi_ipi = true;
3aac27ab DZ	339	return 1;
bda62633 DZ	340	}
	341
	342	__setup("nonmi_ipi", nonmi_ipi_setup);
	343
f9e47a12	344	struct smp_ops smp_ops = {
b9b34f24 CG	345	.smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
	346	.smp_prepare_cpus = native_smp_prepare_cpus,
	347	.smp_cpus_done = native_smp_cpus_done,
f9e47a12	348
5d2b86d9	349	.stop_other_cpus = native_stop_other_cpus,
b9b34f24	350	.smp_send_reschedule = native_smp_send_reschedule,
3b16cf87	351
b9b34f24 CG	352	.cpu_up = native_cpu_up,
	353	.cpu_die = native_cpu_die,
	354	.cpu_disable = native_cpu_disable,
	355	.play_dead = native_play_dead,
93be71b6	356
b9b34f24	357	.send_call_func_ipi = native_send_call_func_ipi,
3b16cf87	358	.send_call_func_single_ipi = native_send_call_func_single_ipi,
f9e47a12 GC	359	};
f9e47a12 GC	360	EXPORT_SYMBOL_GPL(smp_ops);