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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
186f4360 | 46 | #include <linux/export.h> |
70708a18 | 47 | #include <linux/sched.h> |
105ab3d8 | 48 | #include <linux/sched/topology.h> |
ef8bd77f | 49 | #include <linux/sched/hotplug.h> |
68db0cf1 | 50 | #include <linux/sched/task_stack.h> |
69c18c15 | 51 | #include <linux/percpu.h> |
91718e8d | 52 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
53 | #include <linux/err.h> |
54 | #include <linux/nmi.h> | |
69575d38 | 55 | #include <linux/tboot.h> |
35f720c5 | 56 | #include <linux/stackprotector.h> |
5a0e3ad6 | 57 | #include <linux/gfp.h> |
1a022e3f | 58 | #include <linux/cpuidle.h> |
69c18c15 | 59 | |
8aef135c | 60 | #include <asm/acpi.h> |
cb3c8b90 | 61 | #include <asm/desc.h> |
69c18c15 GC |
62 | #include <asm/nmi.h> |
63 | #include <asm/irq.h> | |
48927bbb | 64 | #include <asm/realmode.h> |
69c18c15 GC |
65 | #include <asm/cpu.h> |
66 | #include <asm/numa.h> | |
cb3c8b90 GOC |
67 | #include <asm/pgtable.h> |
68 | #include <asm/tlbflush.h> | |
69 | #include <asm/mtrr.h> | |
ea530692 | 70 | #include <asm/mwait.h> |
7b6aa335 | 71 | #include <asm/apic.h> |
7167d08e | 72 | #include <asm/io_apic.h> |
78f7f1e5 | 73 | #include <asm/fpu/internal.h> |
569712b2 | 74 | #include <asm/setup.h> |
bdbcdd48 | 75 | #include <asm/uv/uv.h> |
cb3c8b90 | 76 | #include <linux/mc146818rtc.h> |
b81bb373 | 77 | #include <asm/i8259.h> |
48927bbb | 78 | #include <asm/realmode.h> |
646e29a1 | 79 | #include <asm/misc.h> |
704cf01d | 80 | #include <asm/microcode.h> |
48927bbb | 81 | |
a355352b GC |
82 | /* Number of siblings per CPU package */ |
83 | int smp_num_siblings = 1; | |
84 | EXPORT_SYMBOL(smp_num_siblings); | |
85 | ||
86 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 87 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 88 | |
a355352b | 89 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 90 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
91 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
92 | ||
93 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
95 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
96 | ||
0816b0f0 | 97 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 98 | |
a355352b | 99 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 100 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 101 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 102 | |
1f12e32f TG |
103 | /* Logical package management. We might want to allocate that dynamically */ |
104 | static int *physical_to_logical_pkg __read_mostly; | |
105 | static unsigned long *physical_package_map __read_mostly;; | |
1f12e32f TG |
106 | static unsigned int max_physical_pkg_id __read_mostly; |
107 | unsigned int __max_logical_packages __read_mostly; | |
108 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 109 | static unsigned int logical_packages __read_mostly; |
1f12e32f | 110 | |
70b8301f AK |
111 | /* Maximum number of SMT threads on any online core */ |
112 | int __max_smt_threads __read_mostly; | |
113 | ||
7d25127c TC |
114 | /* Flag to indicate if a complete sched domain rebuild is required */ |
115 | bool x86_topology_update; | |
116 | ||
117 | int arch_update_cpu_topology(void) | |
118 | { | |
119 | int retval = x86_topology_update; | |
120 | ||
121 | x86_topology_update = false; | |
122 | return retval; | |
123 | } | |
124 | ||
f77aa308 TG |
125 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
126 | { | |
127 | unsigned long flags; | |
128 | ||
129 | spin_lock_irqsave(&rtc_lock, flags); | |
130 | CMOS_WRITE(0xa, 0xf); | |
131 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
132 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
133 | start_eip >> 4; | |
f77aa308 TG |
134 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
135 | start_eip & 0xf; | |
f77aa308 TG |
136 | } |
137 | ||
138 | static inline void smpboot_restore_warm_reset_vector(void) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
f77aa308 TG |
142 | /* |
143 | * Paranoid: Set warm reset code and vector here back | |
144 | * to default values. | |
145 | */ | |
146 | spin_lock_irqsave(&rtc_lock, flags); | |
147 | CMOS_WRITE(0, 0xf); | |
148 | spin_unlock_irqrestore(&rtc_lock, flags); | |
149 | ||
150 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
151 | } | |
152 | ||
cb3c8b90 | 153 | /* |
30106c17 FY |
154 | * Report back to the Boot Processor during boot time or to the caller processor |
155 | * during CPU online. | |
cb3c8b90 | 156 | */ |
148f9bb8 | 157 | static void smp_callin(void) |
cb3c8b90 GOC |
158 | { |
159 | int cpuid, phys_id; | |
cb3c8b90 GOC |
160 | |
161 | /* | |
162 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
163 | * cpu_callout_mask guarantees we don't get here before |
164 | * an INIT_deassert IPI reaches our local APIC, so it is | |
165 | * now safe to touch our local APIC. | |
cb3c8b90 | 166 | */ |
e1c467e6 | 167 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
168 | |
169 | /* | |
170 | * (This works even if the APIC is not enabled.) | |
171 | */ | |
4c9961d5 | 172 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
173 | |
174 | /* | |
175 | * the boot CPU has finished the init stage and is spinning | |
176 | * on callin_map until we finish. We are free to set up this | |
177 | * CPU, first the APIC. (this is probably redundant on most | |
178 | * boards) | |
179 | */ | |
05f7e46d | 180 | apic_ap_setup(); |
cb3c8b90 | 181 | |
b565201c JS |
182 | /* |
183 | * Save our processor parameters. Note: this information | |
184 | * is needed for clock calibration. | |
185 | */ | |
186 | smp_store_cpu_info(cpuid); | |
187 | ||
a55b5204 PT |
188 | /* |
189 | * The topology information must be up to date before | |
190 | * calibrate_delay() and notify_cpu_starting(). | |
191 | */ | |
192 | set_cpu_sibling_map(raw_smp_processor_id()); | |
193 | ||
cb3c8b90 GOC |
194 | /* |
195 | * Get our bogomips. | |
b565201c JS |
196 | * Update loops_per_jiffy in cpu_data. Previous call to |
197 | * smp_store_cpu_info() stored a value that is close but not as | |
198 | * accurate as the value just calculated. | |
cb3c8b90 | 199 | */ |
cb3c8b90 | 200 | calibrate_delay(); |
b565201c | 201 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 202 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 203 | |
5ef428c4 AK |
204 | wmb(); |
205 | ||
85257024 PZ |
206 | notify_cpu_starting(cpuid); |
207 | ||
cb3c8b90 GOC |
208 | /* |
209 | * Allow the master to continue. | |
210 | */ | |
c2d1cec1 | 211 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
212 | } |
213 | ||
e1c467e6 FY |
214 | static int cpu0_logical_apicid; |
215 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
216 | /* |
217 | * Activate a secondary processor. | |
218 | */ | |
148f9bb8 | 219 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
220 | { |
221 | /* | |
0e6a37a4 AL |
222 | * Don't put *anything* except direct CPU state initialization |
223 | * before cpu_init(), SMP booting is too fragile that we want to | |
224 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 225 | */ |
babace1d | 226 | if (IS_ENABLED(CONFIG_X86_64) && boot_cpu_has(X86_FEATURE_PCID)) |
0e6a37a4 | 227 | __write_cr4(__read_cr4() | X86_CR4_PCIDE); |
b40827fa | 228 | cpu_init(); |
df156f90 | 229 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
230 | preempt_disable(); |
231 | smp_callin(); | |
fd89a137 | 232 | |
e1c467e6 FY |
233 | enable_start_cpu0 = 0; |
234 | ||
fd89a137 | 235 | #ifdef CONFIG_X86_32 |
b40827fa | 236 | /* switch away from the initial page table */ |
fd89a137 JR |
237 | load_cr3(swapper_pg_dir); |
238 | __flush_tlb_all(); | |
239 | #endif | |
240 | ||
bbc2ff6a GOC |
241 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
242 | barrier(); | |
243 | /* | |
244 | * Check TSC synchronization with the BP: | |
245 | */ | |
246 | check_tsc_sync_target(); | |
247 | ||
bbc2ff6a | 248 | /* |
5a3f75e3 TG |
249 | * Lock vector_lock and initialize the vectors on this cpu |
250 | * before setting the cpu online. We must set it online with | |
251 | * vector_lock held to prevent a concurrent setup/teardown | |
252 | * from seeing a half valid vector space. | |
bbc2ff6a | 253 | */ |
d388e5fd | 254 | lock_vector_lock(); |
5a3f75e3 | 255 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 256 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 257 | unlock_vector_lock(); |
2a442c9c | 258 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 259 | x86_platform.nmi_init(); |
bbc2ff6a | 260 | |
0cefa5b9 MS |
261 | /* enable local interrupts */ |
262 | local_irq_enable(); | |
263 | ||
35f720c5 JP |
264 | /* to prevent fake stack check failure in clock setup */ |
265 | boot_init_stack_canary(); | |
0cefa5b9 | 266 | |
736decac | 267 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
268 | |
269 | wmb(); | |
fc6d73d6 | 270 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
271 | } |
272 | ||
9d85eb91 TG |
273 | /** |
274 | * topology_update_package_map - Update the physical to logical package map | |
275 | * @pkg: The physical package id as retrieved via CPUID | |
276 | * @cpu: The cpu for which this is updated | |
277 | */ | |
278 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 279 | { |
9d85eb91 | 280 | unsigned int new; |
1f12e32f TG |
281 | |
282 | /* Called from early boot ? */ | |
283 | if (!physical_package_map) | |
284 | return 0; | |
285 | ||
286 | if (pkg >= max_physical_pkg_id) | |
287 | return -EINVAL; | |
288 | ||
289 | /* Set the logical package id */ | |
290 | if (test_and_set_bit(pkg, physical_package_map)) | |
291 | goto found; | |
292 | ||
9d85eb91 TG |
293 | if (logical_packages >= __max_logical_packages) { |
294 | pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", | |
295 | logical_packages, cpu, __max_logical_packages); | |
1f12e32f TG |
296 | return -ENOSPC; |
297 | } | |
7b0501b1 JO |
298 | |
299 | new = logical_packages++; | |
9d85eb91 TG |
300 | if (new != pkg) { |
301 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
302 | cpu, pkg, new); | |
303 | } | |
1f12e32f TG |
304 | physical_to_logical_pkg[pkg] = new; |
305 | ||
306 | found: | |
307 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; | |
308 | return 0; | |
309 | } | |
310 | ||
311 | /** | |
312 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
313 | * | |
314 | * Returns logical package id or -1 if not found | |
315 | */ | |
316 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
317 | { | |
318 | if (phys_pkg >= max_physical_pkg_id) | |
319 | return -1; | |
320 | return physical_to_logical_pkg[phys_pkg]; | |
321 | } | |
322 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
323 | ||
9d85eb91 | 324 | static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) |
1f12e32f | 325 | { |
9d85eb91 | 326 | unsigned int ncpus; |
1f12e32f TG |
327 | size_t size; |
328 | ||
329 | /* | |
330 | * Today neither Intel nor AMD support heterogenous systems. That | |
331 | * might change in the future.... | |
63d1e995 PZ |
332 | * |
333 | * While ideally we'd want '* smp_num_siblings' in the below @ncpus | |
334 | * computation, this won't actually work since some Intel BIOSes | |
335 | * report inconsistent HT data when they disable HT. | |
336 | * | |
337 | * In particular, they reduce the APIC-IDs to only include the cores, | |
338 | * but leave the CPUID topology to say there are (2) siblings. | |
339 | * This means we don't know how many threads there will be until | |
340 | * after the APIC enumeration. | |
341 | * | |
342 | * By not including this we'll sometimes over-estimate the number of | |
343 | * logical packages by the amount of !present siblings, but this is | |
344 | * still better than MAX_LOCAL_APIC. | |
3e8db224 TG |
345 | * |
346 | * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited | |
347 | * on the command line leading to a similar issue as the HT disable | |
348 | * problem because the hyperthreads are usually enumerated after the | |
349 | * primary cores. | |
1f12e32f | 350 | */ |
63d1e995 | 351 | ncpus = boot_cpu_data.x86_max_cores; |
56402d63 TG |
352 | if (!ncpus) { |
353 | pr_warn("x86_max_cores == zero !?!?"); | |
354 | ncpus = 1; | |
355 | } | |
356 | ||
3e8db224 | 357 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
7b0501b1 | 358 | logical_packages = 0; |
1f12e32f TG |
359 | |
360 | /* | |
361 | * Possibly larger than what we need as the number of apic ids per | |
362 | * package can be smaller than the actual used apic ids. | |
363 | */ | |
364 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); | |
365 | size = max_physical_pkg_id * sizeof(unsigned int); | |
366 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); | |
367 | memset(physical_to_logical_pkg, 0xff, size); | |
368 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); | |
369 | physical_package_map = kzalloc(size, GFP_KERNEL); | |
1f12e32f | 370 | |
7b0501b1 | 371 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
9d85eb91 TG |
372 | |
373 | topology_update_package_map(c->phys_proc_id, cpu); | |
1f12e32f TG |
374 | } |
375 | ||
30106c17 FY |
376 | void __init smp_store_boot_cpu_info(void) |
377 | { | |
378 | int id = 0; /* CPU 0 */ | |
379 | struct cpuinfo_x86 *c = &cpu_data(id); | |
380 | ||
381 | *c = boot_cpu_data; | |
382 | c->cpu_index = id; | |
9d85eb91 | 383 | smp_init_package_map(c, id); |
30106c17 FY |
384 | } |
385 | ||
1d89a7f0 GOC |
386 | /* |
387 | * The bootstrap kernel entry code has set these up. Save them for | |
388 | * a given CPU | |
389 | */ | |
148f9bb8 | 390 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
391 | { |
392 | struct cpuinfo_x86 *c = &cpu_data(id); | |
393 | ||
b3d7336d | 394 | *c = boot_cpu_data; |
1d89a7f0 | 395 | c->cpu_index = id; |
30106c17 FY |
396 | /* |
397 | * During boot time, CPU0 has this setup already. Save the info when | |
398 | * bringing up AP or offlined CPU0. | |
399 | */ | |
400 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
401 | } |
402 | ||
cebf15eb DH |
403 | static bool |
404 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
405 | { | |
406 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
407 | ||
408 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
409 | } | |
410 | ||
148f9bb8 | 411 | static bool |
316ad248 | 412 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 413 | { |
316ad248 PZ |
414 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
415 | ||
cebf15eb | 416 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
417 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
418 | "[node: %d != %d]. Ignoring dependency.\n", | |
419 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
420 | } | |
421 | ||
7d79a7bd | 422 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 423 | do { \ |
7d79a7bd BG |
424 | cpumask_set_cpu((c1), mfunc(c2)); \ |
425 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
426 | } while (0) |
427 | ||
148f9bb8 | 428 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 429 | { |
362f924b | 430 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
431 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
432 | ||
433 | if (c->phys_proc_id == o->phys_proc_id && | |
79a8b9aa BP |
434 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
435 | if (c->cpu_core_id == o->cpu_core_id) | |
436 | return topology_sane(c, o, "smt"); | |
437 | ||
438 | if ((c->cu_id != 0xff) && | |
439 | (o->cu_id != 0xff) && | |
440 | (c->cu_id == o->cu_id)) | |
441 | return topology_sane(c, o, "smt"); | |
442 | } | |
316ad248 PZ |
443 | |
444 | } else if (c->phys_proc_id == o->phys_proc_id && | |
445 | c->cpu_core_id == o->cpu_core_id) { | |
446 | return topology_sane(c, o, "smt"); | |
447 | } | |
448 | ||
449 | return false; | |
450 | } | |
451 | ||
148f9bb8 | 452 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
453 | { |
454 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
455 | ||
456 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
457 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
458 | return topology_sane(c, o, "llc"); | |
459 | ||
460 | return false; | |
d4fbe4f0 AH |
461 | } |
462 | ||
cebf15eb DH |
463 | /* |
464 | * Unlike the other levels, we do not enforce keeping a | |
465 | * multicore group inside a NUMA node. If this happens, we will | |
466 | * discard the MC level of the topology later. | |
467 | */ | |
468 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 469 | { |
cebf15eb DH |
470 | if (c->phys_proc_id == o->phys_proc_id) |
471 | return true; | |
316ad248 PZ |
472 | return false; |
473 | } | |
1d89a7f0 | 474 | |
d3d37d85 TC |
475 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
476 | static inline int x86_sched_itmt_flags(void) | |
477 | { | |
478 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
479 | } | |
480 | ||
481 | #ifdef CONFIG_SCHED_MC | |
482 | static int x86_core_flags(void) | |
483 | { | |
484 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
485 | } | |
486 | #endif | |
487 | #ifdef CONFIG_SCHED_SMT | |
488 | static int x86_smt_flags(void) | |
489 | { | |
490 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
491 | } | |
492 | #endif | |
493 | #endif | |
494 | ||
8f37961c | 495 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 496 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 497 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
498 | #endif |
499 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 500 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
501 | #endif |
502 | { NULL, }, | |
503 | }; | |
8f37961c TC |
504 | |
505 | static struct sched_domain_topology_level x86_topology[] = { | |
506 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 507 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
508 | #endif |
509 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 510 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
511 | #endif |
512 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
513 | { NULL, }, | |
514 | }; | |
515 | ||
cebf15eb | 516 | /* |
8f37961c TC |
517 | * Set if a package/die has multiple NUMA nodes inside. |
518 | * AMD Magny-Cours and Intel Cluster-on-Die have this. | |
cebf15eb | 519 | */ |
8f37961c | 520 | static bool x86_has_numa_in_package; |
cebf15eb | 521 | |
148f9bb8 | 522 | void set_cpu_sibling_map(int cpu) |
768d9505 | 523 | { |
316ad248 | 524 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 525 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 526 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 527 | struct cpuinfo_x86 *o; |
70b8301f | 528 | int i, threads; |
768d9505 | 529 | |
c2d1cec1 | 530 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 531 | |
b0bc225d | 532 | if (!has_mp) { |
7d79a7bd | 533 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 534 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 535 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
536 | c->booted_cores = 1; |
537 | return; | |
538 | } | |
539 | ||
c2d1cec1 | 540 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
541 | o = &cpu_data(i); |
542 | ||
543 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 544 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 545 | |
b0bc225d | 546 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 547 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 548 | |
ceb1cbac KB |
549 | } |
550 | ||
551 | /* | |
552 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 553 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
554 | */ |
555 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
556 | o = &cpu_data(i); | |
557 | ||
cebf15eb | 558 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 559 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 560 | |
768d9505 GC |
561 | /* |
562 | * Does this new cpu bringup a new core? | |
563 | */ | |
7d79a7bd BG |
564 | if (cpumask_weight( |
565 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
566 | /* |
567 | * for each core in package, increment | |
568 | * the booted_cores for this new cpu | |
569 | */ | |
7d79a7bd BG |
570 | if (cpumask_first( |
571 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
572 | c->booted_cores++; |
573 | /* | |
574 | * increment the core count for all | |
575 | * the other cpus in this package | |
576 | */ | |
577 | if (i != cpu) | |
578 | cpu_data(i).booted_cores++; | |
579 | } else if (i != cpu && !c->booted_cores) | |
580 | c->booted_cores = cpu_data(i).booted_cores; | |
581 | } | |
728e5653 | 582 | if (match_die(c, o) && !topology_same_node(c, o)) |
8f37961c | 583 | x86_has_numa_in_package = true; |
768d9505 | 584 | } |
70b8301f AK |
585 | |
586 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
587 | if (threads > __max_smt_threads) | |
588 | __max_smt_threads = threads; | |
768d9505 GC |
589 | } |
590 | ||
70708a18 | 591 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 592 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 593 | { |
9f646389 | 594 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
595 | } |
596 | ||
a4928cff | 597 | static void impress_friends(void) |
904541e2 GOC |
598 | { |
599 | int cpu; | |
600 | unsigned long bogosum = 0; | |
601 | /* | |
602 | * Allow the user to impress friends. | |
603 | */ | |
c767a54b | 604 | pr_debug("Before bogomips\n"); |
904541e2 | 605 | for_each_possible_cpu(cpu) |
c2d1cec1 | 606 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 607 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 608 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 609 | num_online_cpus(), |
904541e2 GOC |
610 | bogosum/(500000/HZ), |
611 | (bogosum/(5000/HZ))%100); | |
612 | ||
c767a54b | 613 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
614 | } |
615 | ||
569712b2 | 616 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
617 | { |
618 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 619 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
620 | int timeout; |
621 | u32 status; | |
622 | ||
c767a54b | 623 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
624 | |
625 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 626 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
627 | |
628 | /* | |
629 | * Wait for idle. | |
630 | */ | |
631 | status = safe_apic_wait_icr_idle(); | |
632 | if (status) | |
c767a54b | 633 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 634 | |
1b374e4d | 635 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
636 | |
637 | timeout = 0; | |
638 | do { | |
639 | udelay(100); | |
640 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
641 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
642 | ||
643 | switch (status) { | |
644 | case APIC_ICR_RR_VALID: | |
645 | status = apic_read(APIC_RRR); | |
c767a54b | 646 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
647 | break; |
648 | default: | |
c767a54b | 649 | pr_cont("failed\n"); |
cb3c8b90 GOC |
650 | } |
651 | } | |
652 | } | |
653 | ||
d68921f9 LB |
654 | /* |
655 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
656 | * that there should be a 10ms delay between the BSP asserting INIT | |
657 | * and de-asserting INIT, when starting a remote processor. | |
658 | * But that slows boot and resume on modern processors, which include | |
659 | * many cores and don't require that delay. | |
660 | * | |
661 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 662 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
663 | */ |
664 | #define UDELAY_10MS_DEFAULT 10000 | |
665 | ||
656279a1 | 666 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
667 | |
668 | static int __init cpu_init_udelay(char *str) | |
669 | { | |
670 | get_option(&str, &init_udelay); | |
671 | ||
672 | return 0; | |
673 | } | |
674 | early_param("cpu_init_udelay", cpu_init_udelay); | |
675 | ||
1a744cb3 LB |
676 | static void __init smp_quirk_init_udelay(void) |
677 | { | |
678 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 679 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
680 | return; |
681 | ||
682 | /* if modern processor, use no delay */ | |
683 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 684 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 685 | init_udelay = 0; |
656279a1 LB |
686 | return; |
687 | } | |
f1ccd249 LB |
688 | /* else, use legacy delay */ |
689 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
690 | } |
691 | ||
cb3c8b90 GOC |
692 | /* |
693 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
694 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
695 | * won't ... remember to clear down the APIC, etc later. | |
696 | */ | |
148f9bb8 | 697 | int |
e1c467e6 | 698 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
699 | { |
700 | unsigned long send_status, accept_status = 0; | |
701 | int maxlvt; | |
702 | ||
703 | /* Target chip */ | |
cb3c8b90 GOC |
704 | /* Boot on the stack */ |
705 | /* Kick the second */ | |
e1c467e6 | 706 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 707 | |
cfc1b9a6 | 708 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
709 | send_status = safe_apic_wait_icr_idle(); |
710 | ||
711 | /* | |
712 | * Give the other CPU some time to accept the IPI. | |
713 | */ | |
714 | udelay(200); | |
cff9ab2b | 715 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
716 | maxlvt = lapic_get_maxlvt(); |
717 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
718 | apic_write(APIC_ESR, 0); | |
719 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
720 | } | |
c767a54b | 721 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
722 | |
723 | if (send_status) | |
c767a54b | 724 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 725 | if (accept_status) |
c767a54b | 726 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
727 | |
728 | return (send_status | accept_status); | |
729 | } | |
cb3c8b90 | 730 | |
148f9bb8 | 731 | static int |
569712b2 | 732 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 733 | { |
f5d6a52f | 734 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
735 | int maxlvt, num_starts, j; |
736 | ||
593f4a78 MR |
737 | maxlvt = lapic_get_maxlvt(); |
738 | ||
cb3c8b90 GOC |
739 | /* |
740 | * Be paranoid about clearing APIC errors. | |
741 | */ | |
cff9ab2b | 742 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
743 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
744 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
745 | apic_read(APIC_ESR); |
746 | } | |
747 | ||
c767a54b | 748 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
749 | |
750 | /* | |
751 | * Turn INIT on target chip | |
752 | */ | |
cb3c8b90 GOC |
753 | /* |
754 | * Send IPI | |
755 | */ | |
1b374e4d SS |
756 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
757 | phys_apicid); | |
cb3c8b90 | 758 | |
cfc1b9a6 | 759 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
760 | send_status = safe_apic_wait_icr_idle(); |
761 | ||
7cb68598 | 762 | udelay(init_udelay); |
cb3c8b90 | 763 | |
c767a54b | 764 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
765 | |
766 | /* Target chip */ | |
cb3c8b90 | 767 | /* Send IPI */ |
1b374e4d | 768 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 769 | |
cfc1b9a6 | 770 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
771 | send_status = safe_apic_wait_icr_idle(); |
772 | ||
773 | mb(); | |
cb3c8b90 GOC |
774 | |
775 | /* | |
776 | * Should we send STARTUP IPIs ? | |
777 | * | |
778 | * Determine this based on the APIC version. | |
779 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
780 | */ | |
cff9ab2b | 781 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
782 | num_starts = 2; |
783 | else | |
784 | num_starts = 0; | |
785 | ||
cb3c8b90 GOC |
786 | /* |
787 | * Run STARTUP IPI loop. | |
788 | */ | |
c767a54b | 789 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 790 | |
cb3c8b90 | 791 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 792 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
793 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
794 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 795 | apic_read(APIC_ESR); |
c767a54b | 796 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
797 | |
798 | /* | |
799 | * STARTUP IPI | |
800 | */ | |
801 | ||
802 | /* Target chip */ | |
cb3c8b90 GOC |
803 | /* Boot on the stack */ |
804 | /* Kick the second */ | |
1b374e4d SS |
805 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
806 | phys_apicid); | |
cb3c8b90 GOC |
807 | |
808 | /* | |
809 | * Give the other CPU some time to accept the IPI. | |
810 | */ | |
fcafddec LB |
811 | if (init_udelay == 0) |
812 | udelay(10); | |
813 | else | |
a9bcaa02 | 814 | udelay(300); |
cb3c8b90 | 815 | |
c767a54b | 816 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 817 | |
cfc1b9a6 | 818 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
819 | send_status = safe_apic_wait_icr_idle(); |
820 | ||
821 | /* | |
822 | * Give the other CPU some time to accept the IPI. | |
823 | */ | |
fcafddec LB |
824 | if (init_udelay == 0) |
825 | udelay(10); | |
826 | else | |
a9bcaa02 | 827 | udelay(200); |
cb3c8b90 | 828 | |
593f4a78 | 829 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 830 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
831 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
832 | if (send_status || accept_status) | |
833 | break; | |
834 | } | |
c767a54b | 835 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
836 | |
837 | if (send_status) | |
c767a54b | 838 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 839 | if (accept_status) |
c767a54b | 840 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
841 | |
842 | return (send_status | accept_status); | |
843 | } | |
cb3c8b90 | 844 | |
2eaad1fd | 845 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 846 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
847 | { |
848 | static int current_node = -1; | |
4adc8b71 | 849 | int node = early_cpu_to_node(cpu); |
a17bce4d | 850 | static int width, node_width; |
646e29a1 BP |
851 | |
852 | if (!width) | |
853 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 854 | |
a17bce4d BP |
855 | if (!node_width) |
856 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
857 | ||
858 | if (cpu == 1) | |
859 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
860 | ||
719b3680 | 861 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
862 | if (node != current_node) { |
863 | if (current_node > (-1)) | |
a17bce4d | 864 | pr_cont("\n"); |
2eaad1fd | 865 | current_node = node; |
a17bce4d BP |
866 | |
867 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
868 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 869 | } |
646e29a1 BP |
870 | |
871 | /* Add padding for the BSP */ | |
872 | if (cpu == 1) | |
873 | pr_cont("%*s", width + 1, " "); | |
874 | ||
875 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
876 | ||
2eaad1fd MT |
877 | } else |
878 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
879 | node, cpu, apicid); | |
880 | } | |
881 | ||
e1c467e6 FY |
882 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
883 | { | |
884 | int cpu; | |
885 | ||
886 | cpu = smp_processor_id(); | |
887 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
888 | return NMI_HANDLED; | |
889 | ||
890 | return NMI_DONE; | |
891 | } | |
892 | ||
893 | /* | |
894 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
895 | * | |
896 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
897 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
898 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
899 | * | |
900 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
901 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
902 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
903 | * real platform and request are available. | |
904 | */ | |
148f9bb8 | 905 | static int |
e1c467e6 FY |
906 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
907 | int *cpu0_nmi_registered) | |
908 | { | |
909 | int id; | |
910 | int boot_error; | |
911 | ||
ea7bdc65 JK |
912 | preempt_disable(); |
913 | ||
e1c467e6 FY |
914 | /* |
915 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
916 | */ | |
ea7bdc65 JK |
917 | if (cpu) { |
918 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
919 | goto out; | |
920 | } | |
e1c467e6 FY |
921 | |
922 | /* | |
923 | * Wake up BSP by nmi. | |
924 | * | |
925 | * Register a NMI handler to help wake up CPU0. | |
926 | */ | |
927 | boot_error = register_nmi_handler(NMI_LOCAL, | |
928 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
929 | ||
930 | if (!boot_error) { | |
931 | enable_start_cpu0 = 1; | |
932 | *cpu0_nmi_registered = 1; | |
933 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
934 | id = cpu0_logical_apicid; | |
935 | else | |
936 | id = apicid; | |
937 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
938 | } | |
ea7bdc65 JK |
939 | |
940 | out: | |
941 | preempt_enable(); | |
e1c467e6 FY |
942 | |
943 | return boot_error; | |
944 | } | |
945 | ||
3f85483b BO |
946 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
947 | { | |
948 | /* Just in case we booted with a single CPU. */ | |
949 | alternatives_enable_smp(); | |
950 | ||
951 | per_cpu(current_task, cpu) = idle; | |
952 | ||
953 | #ifdef CONFIG_X86_32 | |
954 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
955 | irq_ctx_init(cpu); | |
258c98e7 | 956 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 957 | #else |
3f85483b BO |
958 | initial_gs = per_cpu_offset(cpu); |
959 | #endif | |
3f85483b BO |
960 | } |
961 | ||
cb3c8b90 GOC |
962 | /* |
963 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
964 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
965 | * Returns zero if CPU booted OK, else error code from |
966 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 967 | */ |
10e66760 VK |
968 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
969 | int *cpu0_nmi_registered) | |
cb3c8b90 | 970 | { |
48927bbb | 971 | volatile u32 *trampoline_status = |
b429dbf6 | 972 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 973 | /* start_ip had better be page-aligned! */ |
f37240f1 | 974 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 975 | |
cb3c8b90 | 976 | unsigned long boot_error = 0; |
ce4b1b16 | 977 | unsigned long timeout; |
cb3c8b90 | 978 | |
b9b1a9c3 | 979 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 980 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 981 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 982 | initial_stack = idle->thread.sp; |
cb3c8b90 | 983 | |
a187e1a3 | 984 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 985 | init_espfix_ap(cpu); |
20d5e4a9 | 986 | |
2eaad1fd MT |
987 | /* So we see what's up */ |
988 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
989 | |
990 | /* | |
991 | * This grunge runs the startup process for | |
992 | * the targeted processor. | |
993 | */ | |
994 | ||
34d05591 | 995 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 996 | |
cfc1b9a6 | 997 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 998 | |
34d05591 JS |
999 | smpboot_setup_warm_reset_vector(start_ip); |
1000 | /* | |
1001 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1002 | */ |
cff9ab2b | 1003 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1004 | apic_write(APIC_ESR, 0); |
1005 | apic_read(APIC_ESR); | |
1006 | } | |
34d05591 | 1007 | } |
cb3c8b90 | 1008 | |
ce4b1b16 IM |
1009 | /* |
1010 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1011 | * cpu_initialized_mask set if previous attempt to online | |
1012 | * it timed-out. Clear cpu_initialized_mask so that after | |
1013 | * INIT/SIPI it could start with a clean state. | |
1014 | */ | |
1015 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1016 | smp_mb(); | |
1017 | ||
cb3c8b90 | 1018 | /* |
e1c467e6 FY |
1019 | * Wake up a CPU in difference cases: |
1020 | * - Use the method in the APIC driver if it's defined | |
1021 | * Otherwise, | |
1022 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1023 | */ |
1f5bcabf IM |
1024 | if (apic->wakeup_secondary_cpu) |
1025 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1026 | else | |
e1c467e6 | 1027 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 1028 | cpu0_nmi_registered); |
cb3c8b90 GOC |
1029 | |
1030 | if (!boot_error) { | |
1031 | /* | |
6e38f1e7 | 1032 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1033 | */ |
ce4b1b16 IM |
1034 | boot_error = -1; |
1035 | timeout = jiffies + 10*HZ; | |
1036 | while (time_before(jiffies, timeout)) { | |
1037 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1038 | /* | |
1039 | * Tell AP to proceed with initialization | |
1040 | */ | |
1041 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1042 | boot_error = 0; | |
1043 | break; | |
1044 | } | |
ce4b1b16 IM |
1045 | schedule(); |
1046 | } | |
1047 | } | |
cb3c8b90 | 1048 | |
ce4b1b16 | 1049 | if (!boot_error) { |
cb3c8b90 | 1050 | /* |
ce4b1b16 | 1051 | * Wait till AP completes initial initialization |
cb3c8b90 | 1052 | */ |
ce4b1b16 | 1053 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1054 | /* |
1055 | * Allow other tasks to run while we wait for the | |
1056 | * AP to come online. This also gives a chance | |
1057 | * for the MTRR work(triggered by the AP coming online) | |
1058 | * to be completed in the stop machine context. | |
1059 | */ | |
1060 | schedule(); | |
cb3c8b90 | 1061 | } |
cb3c8b90 GOC |
1062 | } |
1063 | ||
1064 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1065 | *trampoline_status = 0; |
cb3c8b90 | 1066 | |
02421f98 YL |
1067 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1068 | /* | |
1069 | * Cleanup possible dangling ends... | |
1070 | */ | |
1071 | smpboot_restore_warm_reset_vector(); | |
1072 | } | |
e1c467e6 | 1073 | |
cb3c8b90 GOC |
1074 | return boot_error; |
1075 | } | |
1076 | ||
148f9bb8 | 1077 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1078 | { |
a21769a4 | 1079 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1080 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1081 | unsigned long flags; |
10e66760 | 1082 | int err, ret = 0; |
cb3c8b90 GOC |
1083 | |
1084 | WARN_ON(irqs_disabled()); | |
1085 | ||
cfc1b9a6 | 1086 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1087 | |
30106c17 | 1088 | if (apicid == BAD_APICID || |
c284b42a | 1089 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1090 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1091 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1092 | return -EINVAL; |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * Already booted CPU? | |
1097 | */ | |
c2d1cec1 | 1098 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1099 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1100 | return -ENOSYS; |
1101 | } | |
1102 | ||
1103 | /* | |
1104 | * Save current MTRR state in case it was changed since early boot | |
1105 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1106 | */ | |
1107 | mtrr_save_state(); | |
1108 | ||
2a442c9c PM |
1109 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1110 | err = cpu_check_up_prepare(cpu); | |
1111 | if (err && err != -EBUSY) | |
1112 | return err; | |
cb3c8b90 | 1113 | |
644c1541 | 1114 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1115 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1116 | |
3f85483b BO |
1117 | common_cpu_up(cpu, tidle); |
1118 | ||
10e66760 | 1119 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1120 | if (err) { |
feef1e8e | 1121 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1122 | ret = -EIO; |
1123 | goto unreg_nmi; | |
cb3c8b90 GOC |
1124 | } |
1125 | ||
1126 | /* | |
1127 | * Check TSC synchronization with the AP (keep irqs disabled | |
1128 | * while doing so): | |
1129 | */ | |
1130 | local_irq_save(flags); | |
1131 | check_tsc_sync_source(cpu); | |
1132 | local_irq_restore(flags); | |
1133 | ||
7c04e64a | 1134 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1135 | cpu_relax(); |
1136 | touch_nmi_watchdog(); | |
1137 | } | |
1138 | ||
10e66760 VK |
1139 | unreg_nmi: |
1140 | /* | |
1141 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1142 | * to avoid impact of possible long unregister time. | |
1143 | */ | |
1144 | if (cpu0_nmi_registered) | |
1145 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1146 | ||
1147 | return ret; | |
cb3c8b90 GOC |
1148 | } |
1149 | ||
7167d08e HK |
1150 | /** |
1151 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1152 | */ | |
1153 | void arch_disable_smp_support(void) | |
1154 | { | |
1155 | disable_ioapic_support(); | |
1156 | } | |
1157 | ||
8aef135c GOC |
1158 | /* |
1159 | * Fall back to non SMP mode after errors. | |
1160 | * | |
1161 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1162 | */ | |
1163 | static __init void disable_smp(void) | |
1164 | { | |
613c25ef TG |
1165 | pr_info("SMP disabled\n"); |
1166 | ||
ef4c59a4 TG |
1167 | disable_ioapic_support(); |
1168 | ||
4f062896 RR |
1169 | init_cpu_present(cpumask_of(0)); |
1170 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1171 | |
8aef135c | 1172 | if (smp_found_config) |
b6df1b8b | 1173 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1174 | else |
b6df1b8b | 1175 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1176 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1177 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1178 | } |
1179 | ||
613c25ef TG |
1180 | enum { |
1181 | SMP_OK, | |
1182 | SMP_NO_CONFIG, | |
1183 | SMP_NO_APIC, | |
1184 | SMP_FORCE_UP, | |
1185 | }; | |
1186 | ||
8aef135c GOC |
1187 | /* |
1188 | * Various sanity checks. | |
1189 | */ | |
1190 | static int __init smp_sanity_check(unsigned max_cpus) | |
1191 | { | |
ac23d4ee | 1192 | preempt_disable(); |
a58f03b0 | 1193 | |
1ff2f20d | 1194 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1195 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1196 | unsigned int cpu; | |
1197 | unsigned nr; | |
1198 | ||
c767a54b JP |
1199 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1200 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1201 | |
1202 | nr = 0; | |
1203 | for_each_present_cpu(cpu) { | |
1204 | if (nr >= 8) | |
c2d1cec1 | 1205 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1206 | nr++; |
1207 | } | |
1208 | ||
1209 | nr = 0; | |
1210 | for_each_possible_cpu(cpu) { | |
1211 | if (nr >= 8) | |
c2d1cec1 | 1212 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1213 | nr++; |
1214 | } | |
1215 | ||
1216 | nr_cpu_ids = 8; | |
1217 | } | |
1218 | #endif | |
1219 | ||
8aef135c | 1220 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1221 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1222 | hard_smp_processor_id()); |
1223 | ||
8aef135c GOC |
1224 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1225 | } | |
1226 | ||
1227 | /* | |
1228 | * If we couldn't find an SMP configuration at boot time, | |
1229 | * get out of here now! | |
1230 | */ | |
1231 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1232 | preempt_enable(); |
c767a54b | 1233 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1234 | return SMP_NO_CONFIG; |
8aef135c GOC |
1235 | } |
1236 | ||
1237 | /* | |
1238 | * Should not be necessary because the MP table should list the boot | |
1239 | * CPU too, but we do it for the sake of robustness anyway. | |
1240 | */ | |
a27a6210 | 1241 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1242 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1243 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1244 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1245 | } | |
ac23d4ee | 1246 | preempt_enable(); |
8aef135c GOC |
1247 | |
1248 | /* | |
1249 | * If we couldn't find a local APIC, then get out of here now! | |
1250 | */ | |
cff9ab2b | 1251 | if (APIC_INTEGRATED(boot_cpu_apic_version) && |
93984fbd | 1252 | !boot_cpu_has(X86_FEATURE_APIC)) { |
103428e5 CG |
1253 | if (!disable_apic) { |
1254 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1255 | boot_cpu_physical_apicid); | |
c767a54b | 1256 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1257 | } |
613c25ef | 1258 | return SMP_NO_APIC; |
8aef135c GOC |
1259 | } |
1260 | ||
8aef135c GOC |
1261 | /* |
1262 | * If SMP should be disabled, then really disable it! | |
1263 | */ | |
1264 | if (!max_cpus) { | |
c767a54b | 1265 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1266 | return SMP_FORCE_UP; |
8aef135c GOC |
1267 | } |
1268 | ||
613c25ef | 1269 | return SMP_OK; |
8aef135c GOC |
1270 | } |
1271 | ||
1272 | static void __init smp_cpu_index_default(void) | |
1273 | { | |
1274 | int i; | |
1275 | struct cpuinfo_x86 *c; | |
1276 | ||
7c04e64a | 1277 | for_each_possible_cpu(i) { |
8aef135c GOC |
1278 | c = &cpu_data(i); |
1279 | /* mark all to hotplug */ | |
9628937d | 1280 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1281 | } |
1282 | } | |
1283 | ||
1284 | /* | |
1285 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1286 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1287 | */ | |
1288 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1289 | { | |
7ad728f9 RR |
1290 | unsigned int i; |
1291 | ||
8aef135c | 1292 | smp_cpu_index_default(); |
792363d2 | 1293 | |
8aef135c GOC |
1294 | /* |
1295 | * Setup boot CPU information | |
1296 | */ | |
30106c17 | 1297 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1298 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1299 | mb(); | |
bd22a2f1 | 1300 | |
7ad728f9 | 1301 | for_each_possible_cpu(i) { |
79f55997 LZ |
1302 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1303 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1304 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1305 | } |
8f37961c TC |
1306 | |
1307 | /* | |
1308 | * Set 'default' x86 topology, this matches default_topology() in that | |
1309 | * it has NUMA nodes as a topology level. See also | |
1310 | * native_smp_cpus_done(). | |
1311 | * | |
1312 | * Must be done before set_cpus_sibling_map() is ran. | |
1313 | */ | |
1314 | set_sched_topology(x86_topology); | |
1315 | ||
8aef135c GOC |
1316 | set_cpu_sibling_map(0); |
1317 | ||
613c25ef TG |
1318 | switch (smp_sanity_check(max_cpus)) { |
1319 | case SMP_NO_CONFIG: | |
8aef135c | 1320 | disable_smp(); |
613c25ef TG |
1321 | if (APIC_init_uniprocessor()) |
1322 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1323 | return; | |
1324 | case SMP_NO_APIC: | |
1325 | disable_smp(); | |
1326 | return; | |
1327 | case SMP_FORCE_UP: | |
1328 | disable_smp(); | |
374aab33 | 1329 | apic_bsp_setup(false); |
250a1ac6 | 1330 | return; |
613c25ef TG |
1331 | case SMP_OK: |
1332 | break; | |
8aef135c GOC |
1333 | } |
1334 | ||
4c9961d5 | 1335 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1336 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1337 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1338 | /* Or can we switch back to PIC here? */ |
1339 | } | |
1340 | ||
384d9fe3 | 1341 | default_setup_apic_routing(); |
374aab33 | 1342 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1343 | |
d54ff31d | 1344 | pr_info("CPU0: "); |
8aef135c | 1345 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1346 | |
9ec808a0 | 1347 | uv_system_init(); |
d0af9eed SS |
1348 | |
1349 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1350 | |
1351 | smp_quirk_init_udelay(); | |
8aef135c | 1352 | } |
d0af9eed SS |
1353 | |
1354 | void arch_enable_nonboot_cpus_begin(void) | |
1355 | { | |
1356 | set_mtrr_aps_delayed_init(); | |
1357 | } | |
1358 | ||
1359 | void arch_enable_nonboot_cpus_end(void) | |
1360 | { | |
1361 | mtrr_aps_init(); | |
1362 | } | |
1363 | ||
a8db8453 GOC |
1364 | /* |
1365 | * Early setup to make printk work. | |
1366 | */ | |
1367 | void __init native_smp_prepare_boot_cpu(void) | |
1368 | { | |
1369 | int me = smp_processor_id(); | |
552be871 | 1370 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1371 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1372 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1373 | cpu_set_state_online(me); |
a8db8453 GOC |
1374 | } |
1375 | ||
83f7eb9c GOC |
1376 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1377 | { | |
c767a54b | 1378 | pr_debug("Boot done\n"); |
83f7eb9c | 1379 | |
8f37961c TC |
1380 | if (x86_has_numa_in_package) |
1381 | set_sched_topology(x86_numa_in_package_topology); | |
1382 | ||
99e8b9ca | 1383 | nmi_selftest(); |
83f7eb9c | 1384 | impress_friends(); |
83f7eb9c | 1385 | setup_ioapic_dest(); |
d0af9eed | 1386 | mtrr_aps_init(); |
83f7eb9c GOC |
1387 | } |
1388 | ||
3b11ce7f MT |
1389 | static int __initdata setup_possible_cpus = -1; |
1390 | static int __init _setup_possible_cpus(char *str) | |
1391 | { | |
1392 | get_option(&str, &setup_possible_cpus); | |
1393 | return 0; | |
1394 | } | |
1395 | early_param("possible_cpus", _setup_possible_cpus); | |
1396 | ||
1397 | ||
68a1c3f8 | 1398 | /* |
4f062896 | 1399 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1400 | * are onlined, or offlined. The reason is per-cpu data-structures |
1401 | * are allocated by some modules at init time, and dont expect to | |
1402 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1403 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1404 | * In case when cpu_hotplug is not compiled, then we resort to current |
1405 | * behaviour, which is cpu_possible == cpu_present. | |
1406 | * - Ashok Raj | |
1407 | * | |
1408 | * Three ways to find out the number of additional hotplug CPUs: | |
1409 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1410 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1411 | * - Otherwise don't reserve additional CPUs. |
1412 | * We do this because additional CPUs waste a lot of memory. | |
1413 | * -AK | |
1414 | */ | |
1415 | __init void prefill_possible_map(void) | |
1416 | { | |
cb48bb59 | 1417 | int i, possible; |
68a1c3f8 | 1418 | |
2a51fe08 PB |
1419 | /* No boot processor was found in mptable or ACPI MADT */ |
1420 | if (!num_processors) { | |
ff856051 VS |
1421 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1422 | int apicid = boot_cpu_physical_apicid; | |
1423 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1424 | |
ff856051 | 1425 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1426 | |
ff856051 VS |
1427 | /* Make sure boot cpu is enumerated */ |
1428 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1429 | apic->apic_id_valid(apicid)) | |
1430 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1431 | } | |
2a51fe08 PB |
1432 | |
1433 | if (!num_processors) | |
1434 | num_processors = 1; | |
1435 | } | |
329513a3 | 1436 | |
5f2eb550 JB |
1437 | i = setup_max_cpus ?: 1; |
1438 | if (setup_possible_cpus == -1) { | |
1439 | possible = num_processors; | |
1440 | #ifdef CONFIG_HOTPLUG_CPU | |
1441 | if (setup_max_cpus) | |
1442 | possible += disabled_cpus; | |
1443 | #else | |
1444 | if (possible > i) | |
1445 | possible = i; | |
1446 | #endif | |
1447 | } else | |
3b11ce7f MT |
1448 | possible = setup_possible_cpus; |
1449 | ||
730cf272 MT |
1450 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1451 | ||
2b633e3f YL |
1452 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1453 | if (possible > nr_cpu_ids) { | |
c767a54b | 1454 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1455 | possible, nr_cpu_ids); |
1456 | possible = nr_cpu_ids; | |
3b11ce7f | 1457 | } |
68a1c3f8 | 1458 | |
5f2eb550 JB |
1459 | #ifdef CONFIG_HOTPLUG_CPU |
1460 | if (!setup_max_cpus) | |
1461 | #endif | |
1462 | if (possible > i) { | |
c767a54b | 1463 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1464 | possible, setup_max_cpus); |
1465 | possible = i; | |
1466 | } | |
1467 | ||
427d77a3 TG |
1468 | nr_cpu_ids = possible; |
1469 | ||
c767a54b | 1470 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1471 | possible, max_t(int, possible - num_processors, 0)); |
1472 | ||
427d77a3 TG |
1473 | reset_cpu_possible_mask(); |
1474 | ||
68a1c3f8 | 1475 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1476 | set_cpu_possible(i, true); |
68a1c3f8 | 1477 | } |
69c18c15 | 1478 | |
14adf855 CE |
1479 | #ifdef CONFIG_HOTPLUG_CPU |
1480 | ||
70b8301f AK |
1481 | /* Recompute SMT state for all CPUs on offline */ |
1482 | static void recompute_smt_state(void) | |
1483 | { | |
1484 | int max_threads, cpu; | |
1485 | ||
1486 | max_threads = 0; | |
1487 | for_each_online_cpu (cpu) { | |
1488 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1489 | ||
1490 | if (threads > max_threads) | |
1491 | max_threads = threads; | |
1492 | } | |
1493 | __max_smt_threads = max_threads; | |
1494 | } | |
1495 | ||
14adf855 CE |
1496 | static void remove_siblinginfo(int cpu) |
1497 | { | |
1498 | int sibling; | |
1499 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1500 | ||
7d79a7bd BG |
1501 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1502 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1503 | /*/ |
1504 | * last thread sibling in this cpu core going down | |
1505 | */ | |
7d79a7bd | 1506 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1507 | cpu_data(sibling).booted_cores--; |
1508 | } | |
1509 | ||
7d79a7bd BG |
1510 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1511 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1512 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1513 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1514 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1515 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1516 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1517 | c->phys_proc_id = 0; |
1518 | c->cpu_core_id = 0; | |
c2d1cec1 | 1519 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1520 | recompute_smt_state(); |
14adf855 CE |
1521 | } |
1522 | ||
4daa832d | 1523 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1524 | { |
c2d1cec1 MT |
1525 | set_cpu_online(cpu, false); |
1526 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1527 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1528 | /* was set by cpu_init() */ |
c2d1cec1 | 1529 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1530 | numa_remove_cpu(cpu); |
69c18c15 GC |
1531 | } |
1532 | ||
8227dce7 | 1533 | void cpu_disable_common(void) |
69c18c15 GC |
1534 | { |
1535 | int cpu = smp_processor_id(); | |
69c18c15 | 1536 | |
69c18c15 GC |
1537 | remove_siblinginfo(cpu); |
1538 | ||
1539 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1540 | lock_vector_lock(); |
69c18c15 | 1541 | remove_cpu_from_maps(cpu); |
d388e5fd | 1542 | unlock_vector_lock(); |
d7b381bb | 1543 | fixup_irqs(); |
8227dce7 AN |
1544 | } |
1545 | ||
1546 | int native_cpu_disable(void) | |
1547 | { | |
da6139e4 PB |
1548 | int ret; |
1549 | ||
1550 | ret = check_irq_vectors_for_cpu_disable(); | |
1551 | if (ret) | |
1552 | return ret; | |
1553 | ||
8227dce7 | 1554 | clear_local_APIC(); |
8227dce7 | 1555 | cpu_disable_common(); |
2ed53c0d | 1556 | |
69c18c15 GC |
1557 | return 0; |
1558 | } | |
1559 | ||
2a442c9c | 1560 | int common_cpu_die(unsigned int cpu) |
54279552 | 1561 | { |
2a442c9c | 1562 | int ret = 0; |
54279552 | 1563 | |
69c18c15 | 1564 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1565 | |
2ed53c0d | 1566 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1567 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1568 | if (system_state == SYSTEM_RUNNING) |
1569 | pr_info("CPU %u is now offline\n", cpu); | |
1570 | } else { | |
1571 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1572 | ret = -1; |
69c18c15 | 1573 | } |
2a442c9c PM |
1574 | |
1575 | return ret; | |
1576 | } | |
1577 | ||
1578 | void native_cpu_die(unsigned int cpu) | |
1579 | { | |
1580 | common_cpu_die(cpu); | |
69c18c15 | 1581 | } |
a21f5d88 AN |
1582 | |
1583 | void play_dead_common(void) | |
1584 | { | |
1585 | idle_task_exit(); | |
a21f5d88 | 1586 | |
a21f5d88 | 1587 | /* Ack it */ |
2a442c9c | 1588 | (void)cpu_report_death(); |
a21f5d88 AN |
1589 | |
1590 | /* | |
1591 | * With physical CPU hotplug, we should halt the cpu | |
1592 | */ | |
1593 | local_irq_disable(); | |
1594 | } | |
1595 | ||
e1c467e6 FY |
1596 | static bool wakeup_cpu0(void) |
1597 | { | |
1598 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1599 | return true; | |
1600 | ||
1601 | return false; | |
1602 | } | |
1603 | ||
ea530692 PA |
1604 | /* |
1605 | * We need to flush the caches before going to sleep, lest we have | |
1606 | * dirty data in our caches when we come back up. | |
1607 | */ | |
1608 | static inline void mwait_play_dead(void) | |
1609 | { | |
1610 | unsigned int eax, ebx, ecx, edx; | |
1611 | unsigned int highest_cstate = 0; | |
1612 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1613 | void *mwait_ptr; |
576cfb40 | 1614 | int i; |
ea530692 | 1615 | |
69fb3676 | 1616 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1617 | return; |
840d2830 | 1618 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1619 | return; |
7b543a53 | 1620 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1621 | return; |
1622 | ||
1623 | eax = CPUID_MWAIT_LEAF; | |
1624 | ecx = 0; | |
1625 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1626 | ||
1627 | /* | |
1628 | * eax will be 0 if EDX enumeration is not valid. | |
1629 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1630 | */ | |
1631 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1632 | eax = 0; | |
1633 | } else { | |
1634 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1635 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1636 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1637 | highest_cstate = i; | |
1638 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1639 | } | |
1640 | } | |
1641 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1642 | (highest_subcstate - 1); | |
1643 | } | |
1644 | ||
ce5f6824 PA |
1645 | /* |
1646 | * This should be a memory location in a cache line which is | |
1647 | * unlikely to be touched by other processors. The actual | |
1648 | * content is immaterial as it is not actually modified in any way. | |
1649 | */ | |
1650 | mwait_ptr = ¤t_thread_info()->flags; | |
1651 | ||
a68e5c94 PA |
1652 | wbinvd(); |
1653 | ||
ea530692 | 1654 | while (1) { |
ce5f6824 PA |
1655 | /* |
1656 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1657 | * the Xeon 7400 series. It's not clear it is actually | |
1658 | * needed, but it should be harmless in either case. | |
1659 | * The WBINVD is insufficient due to the spurious-wakeup | |
1660 | * case where we return around the loop. | |
1661 | */ | |
7d590cca | 1662 | mb(); |
ce5f6824 | 1663 | clflush(mwait_ptr); |
7d590cca | 1664 | mb(); |
ce5f6824 | 1665 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1666 | mb(); |
1667 | __mwait(eax, 0); | |
e1c467e6 FY |
1668 | /* |
1669 | * If NMI wants to wake up CPU0, start CPU0. | |
1670 | */ | |
1671 | if (wakeup_cpu0()) | |
1672 | start_cpu0(); | |
ea530692 PA |
1673 | } |
1674 | } | |
1675 | ||
406f992e | 1676 | void hlt_play_dead(void) |
ea530692 | 1677 | { |
7b543a53 | 1678 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1679 | wbinvd(); |
1680 | ||
ea530692 | 1681 | while (1) { |
ea530692 | 1682 | native_halt(); |
e1c467e6 FY |
1683 | /* |
1684 | * If NMI wants to wake up CPU0, start CPU0. | |
1685 | */ | |
1686 | if (wakeup_cpu0()) | |
1687 | start_cpu0(); | |
ea530692 PA |
1688 | } |
1689 | } | |
1690 | ||
a21f5d88 AN |
1691 | void native_play_dead(void) |
1692 | { | |
1693 | play_dead_common(); | |
86886e55 | 1694 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 | 1695 | |
357b57d7 | 1696 | if (ibrs_inuse) |
704cf01d TC |
1697 | native_wrmsrl(MSR_IA32_SPEC_CTRL, 0); |
1698 | ||
ea530692 | 1699 | mwait_play_dead(); /* Only returns on failure */ |
1a022e3f BO |
1700 | if (cpuidle_play_dead()) |
1701 | hlt_play_dead(); | |
704cf01d | 1702 | |
357b57d7 | 1703 | if (ibrs_inuse) |
704cf01d | 1704 | native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS); |
a21f5d88 AN |
1705 | } |
1706 | ||
69c18c15 | 1707 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1708 | int native_cpu_disable(void) |
69c18c15 GC |
1709 | { |
1710 | return -ENOSYS; | |
1711 | } | |
1712 | ||
93be71b6 | 1713 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1714 | { |
1715 | /* We said "no" in __cpu_disable */ | |
1716 | BUG(); | |
1717 | } | |
a21f5d88 AN |
1718 | |
1719 | void native_play_dead(void) | |
1720 | { | |
1721 | BUG(); | |
1722 | } | |
1723 | ||
68a1c3f8 | 1724 | #endif |