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Commit | Line | Data |
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4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
69c18c15 | 53 | |
8aef135c | 54 | #include <asm/acpi.h> |
cb3c8b90 | 55 | #include <asm/desc.h> |
69c18c15 GC |
56 | #include <asm/nmi.h> |
57 | #include <asm/irq.h> | |
07bbc16a | 58 | #include <asm/idle.h> |
e44b7b75 | 59 | #include <asm/trampoline.h> |
69c18c15 GC |
60 | #include <asm/cpu.h> |
61 | #include <asm/numa.h> | |
cb3c8b90 GOC |
62 | #include <asm/pgtable.h> |
63 | #include <asm/tlbflush.h> | |
64 | #include <asm/mtrr.h> | |
ea530692 | 65 | #include <asm/mwait.h> |
7b6aa335 | 66 | #include <asm/apic.h> |
7167d08e | 67 | #include <asm/io_apic.h> |
569712b2 | 68 | #include <asm/setup.h> |
bdbcdd48 | 69 | #include <asm/uv/uv.h> |
cb3c8b90 | 70 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 71 | |
1164dd00 | 72 | #include <asm/smpboot_hooks.h> |
b81bb373 | 73 | #include <asm/i8259.h> |
cb3c8b90 | 74 | |
a8db8453 GOC |
75 | /* State of each CPU */ |
76 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
77 | ||
cb3c8b90 GOC |
78 | /* Store all idle threads, this can be reused instead of creating |
79 | * a new thread. Also avoids complicated thread destroy functionality | |
80 | * for idle threads. | |
81 | */ | |
82 | #ifdef CONFIG_HOTPLUG_CPU | |
83 | /* | |
84 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
85 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
86 | */ | |
87 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
88 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
89 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
90 | |
91 | /* | |
92 | * We need this for trampoline_base protection from concurrent accesses when | |
93 | * off- and onlining cores wildly. | |
94 | */ | |
95 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
96 | ||
91d88ce2 | 97 | void cpu_hotplug_driver_lock(void) |
d7c53c9e BP |
98 | { |
99 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
100 | } | |
101 | ||
91d88ce2 | 102 | void cpu_hotplug_driver_unlock(void) |
d7c53c9e BP |
103 | { |
104 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
105 | } | |
106 | ||
107 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
108 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 109 | #else |
f86c9985 | 110 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
111 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
112 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
113 | #endif | |
f6bc4029 | 114 | |
a355352b GC |
115 | /* Number of siblings per CPU package */ |
116 | int smp_num_siblings = 1; | |
117 | EXPORT_SYMBOL(smp_num_siblings); | |
118 | ||
119 | /* Last level cache ID of each logical CPU */ | |
120 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
121 | ||
a355352b | 122 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 123 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
124 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
125 | ||
126 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 127 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
128 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
129 | ||
b3d7336d YL |
130 | DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); |
131 | ||
a355352b GC |
132 | /* Per CPU bogomips and other parameters */ |
133 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
134 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 135 | |
2b6163bf | 136 | atomic_t init_deasserted; |
cb3c8b90 | 137 | |
cb3c8b90 GOC |
138 | /* |
139 | * Report back to the Boot Processor. | |
140 | * Running on AP. | |
141 | */ | |
a4928cff | 142 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
143 | { |
144 | int cpuid, phys_id; | |
145 | unsigned long timeout; | |
146 | ||
147 | /* | |
148 | * If waken up by an INIT in an 82489DX configuration | |
149 | * we may get here before an INIT-deassert IPI reaches | |
150 | * our local APIC. We have to wait for the IPI or we'll | |
151 | * lock up on an APIC access. | |
152 | */ | |
a9659366 IM |
153 | if (apic->wait_for_init_deassert) |
154 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
155 | |
156 | /* | |
157 | * (This works even if the APIC is not enabled.) | |
158 | */ | |
4c9961d5 | 159 | phys_id = read_apic_id(); |
cb3c8b90 | 160 | cpuid = smp_processor_id(); |
c2d1cec1 | 161 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
162 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
163 | phys_id, cpuid); | |
164 | } | |
cfc1b9a6 | 165 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
166 | |
167 | /* | |
168 | * STARTUP IPIs are fragile beasts as they might sometimes | |
169 | * trigger some glue motherboard logic. Complete APIC bus | |
170 | * silence for 1 second, this overestimates the time the | |
171 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
172 | * by a factor of two. This should be enough. | |
173 | */ | |
174 | ||
175 | /* | |
176 | * Waiting 2s total for startup (udelay is not yet working) | |
177 | */ | |
178 | timeout = jiffies + 2*HZ; | |
179 | while (time_before(jiffies, timeout)) { | |
180 | /* | |
181 | * Has the boot CPU finished it's STARTUP sequence? | |
182 | */ | |
c2d1cec1 | 183 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
184 | break; |
185 | cpu_relax(); | |
186 | } | |
187 | ||
188 | if (!time_before(jiffies, timeout)) { | |
189 | panic("%s: CPU%d started up but did not get a callout!\n", | |
190 | __func__, cpuid); | |
191 | } | |
192 | ||
193 | /* | |
194 | * the boot CPU has finished the init stage and is spinning | |
195 | * on callin_map until we finish. We are free to set up this | |
196 | * CPU, first the APIC. (this is probably redundant on most | |
197 | * boards) | |
198 | */ | |
199 | ||
cfc1b9a6 | 200 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
201 | if (apic->smp_callin_clear_local_apic) |
202 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
203 | setup_local_APIC(); |
204 | end_local_APIC_setup(); | |
cb3c8b90 | 205 | |
9d133e5d SS |
206 | /* |
207 | * Need to setup vector mappings before we enable interrupts. | |
208 | */ | |
36e9e1ea | 209 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
210 | |
211 | /* | |
212 | * Save our processor parameters. Note: this information | |
213 | * is needed for clock calibration. | |
214 | */ | |
215 | smp_store_cpu_info(cpuid); | |
216 | ||
cb3c8b90 GOC |
217 | /* |
218 | * Get our bogomips. | |
b565201c JS |
219 | * Update loops_per_jiffy in cpu_data. Previous call to |
220 | * smp_store_cpu_info() stored a value that is close but not as | |
221 | * accurate as the value just calculated. | |
cb3c8b90 GOC |
222 | * |
223 | * Need to enable IRQs because it can take longer and then | |
224 | * the NMI watchdog might kill us. | |
225 | */ | |
226 | local_irq_enable(); | |
227 | calibrate_delay(); | |
b565201c | 228 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cb3c8b90 | 229 | local_irq_disable(); |
cfc1b9a6 | 230 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 231 | |
5ef428c4 AK |
232 | /* |
233 | * This must be done before setting cpu_online_mask | |
234 | * or calling notify_cpu_starting. | |
235 | */ | |
236 | set_cpu_sibling_map(raw_smp_processor_id()); | |
237 | wmb(); | |
238 | ||
85257024 PZ |
239 | notify_cpu_starting(cpuid); |
240 | ||
cb3c8b90 GOC |
241 | /* |
242 | * Allow the master to continue. | |
243 | */ | |
c2d1cec1 | 244 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
245 | } |
246 | ||
bbc2ff6a GOC |
247 | /* |
248 | * Activate a secondary processor. | |
249 | */ | |
0ca59dd9 | 250 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
251 | { |
252 | /* | |
253 | * Don't put *anything* before cpu_init(), SMP booting is too | |
254 | * fragile that we want to limit the things done here to the | |
255 | * most necessary things. | |
256 | */ | |
b40827fa BP |
257 | cpu_init(); |
258 | preempt_disable(); | |
259 | smp_callin(); | |
fd89a137 JR |
260 | |
261 | #ifdef CONFIG_X86_32 | |
b40827fa | 262 | /* switch away from the initial page table */ |
fd89a137 JR |
263 | load_cr3(swapper_pg_dir); |
264 | __flush_tlb_all(); | |
265 | #endif | |
266 | ||
bbc2ff6a GOC |
267 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
268 | barrier(); | |
269 | /* | |
270 | * Check TSC synchronization with the BP: | |
271 | */ | |
272 | check_tsc_sync_target(); | |
273 | ||
bbc2ff6a GOC |
274 | /* |
275 | * We need to hold call_lock, so there is no inconsistency | |
276 | * between the time smp_call_function() determines number of | |
277 | * IPI recipients, and the time when the determination is made | |
278 | * for which cpus receive the IPI. Holding this | |
279 | * lock helps us to not include this cpu in a currently in progress | |
280 | * smp_call_function(). | |
d388e5fd EB |
281 | * |
282 | * We need to hold vector_lock so there the set of online cpus | |
283 | * does not change while we are assigning vectors to cpus. Holding | |
284 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 285 | */ |
0cefa5b9 | 286 | ipi_call_lock(); |
d388e5fd | 287 | lock_vector_lock(); |
c2d1cec1 | 288 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 289 | unlock_vector_lock(); |
0cefa5b9 | 290 | ipi_call_unlock(); |
bbc2ff6a | 291 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 292 | x86_platform.nmi_init(); |
bbc2ff6a | 293 | |
fd8a7de1 TG |
294 | /* |
295 | * Wait until the cpu which brought this one up marked it | |
296 | * online before enabling interrupts. If we don't do that then | |
297 | * we can end up waking up the softirq thread before this cpu | |
298 | * reached the active state, which makes the scheduler unhappy | |
299 | * and schedule the softirq thread on the wrong cpu. This is | |
300 | * only observable with forced threaded interrupts, but in | |
301 | * theory it could also happen w/o them. It's just way harder | |
302 | * to achieve. | |
303 | */ | |
304 | while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask)) | |
305 | cpu_relax(); | |
306 | ||
0cefa5b9 MS |
307 | /* enable local interrupts */ |
308 | local_irq_enable(); | |
309 | ||
35f720c5 JP |
310 | /* to prevent fake stack check failure in clock setup */ |
311 | boot_init_stack_canary(); | |
0cefa5b9 | 312 | |
736decac | 313 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
314 | |
315 | wmb(); | |
316 | cpu_idle(); | |
317 | } | |
318 | ||
1d89a7f0 GOC |
319 | /* |
320 | * The bootstrap kernel entry code has set these up. Save them for | |
321 | * a given CPU | |
322 | */ | |
323 | ||
324 | void __cpuinit smp_store_cpu_info(int id) | |
325 | { | |
326 | struct cpuinfo_x86 *c = &cpu_data(id); | |
327 | ||
b3d7336d | 328 | *c = boot_cpu_data; |
1d89a7f0 GOC |
329 | c->cpu_index = id; |
330 | if (id != 0) | |
331 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
332 | } |
333 | ||
d4fbe4f0 AH |
334 | static void __cpuinit link_thread_siblings(int cpu1, int cpu2) |
335 | { | |
d4fbe4f0 AH |
336 | cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); |
337 | cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); | |
338 | cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); | |
339 | cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); | |
b3d7336d YL |
340 | cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); |
341 | cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); | |
d4fbe4f0 AH |
342 | } |
343 | ||
1d89a7f0 | 344 | |
768d9505 GC |
345 | void __cpuinit set_cpu_sibling_map(int cpu) |
346 | { | |
347 | int i; | |
348 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
349 | ||
c2d1cec1 | 350 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
351 | |
352 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
353 | for_each_cpu(i, cpu_sibling_setup_mask) { |
354 | struct cpuinfo_x86 *o = &cpu_data(i); | |
355 | ||
d4fbe4f0 AH |
356 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
357 | if (c->phys_proc_id == o->phys_proc_id && | |
d518573d | 358 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && |
d4fbe4f0 AH |
359 | c->compute_unit_id == o->compute_unit_id) |
360 | link_thread_siblings(cpu, i); | |
361 | } else if (c->phys_proc_id == o->phys_proc_id && | |
362 | c->cpu_core_id == o->cpu_core_id) { | |
363 | link_thread_siblings(cpu, i); | |
768d9505 GC |
364 | } |
365 | } | |
366 | } else { | |
c2d1cec1 | 367 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
368 | } |
369 | ||
b3d7336d | 370 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
768d9505 | 371 | |
7b543a53 | 372 | if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { |
c2d1cec1 | 373 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
374 | c->booted_cores = 1; |
375 | return; | |
376 | } | |
377 | ||
c2d1cec1 | 378 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
379 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
380 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
b3d7336d YL |
381 | cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); |
382 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); | |
768d9505 GC |
383 | } |
384 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
385 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
386 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
387 | /* |
388 | * Does this new cpu bringup a new core? | |
389 | */ | |
c2d1cec1 | 390 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
391 | /* |
392 | * for each core in package, increment | |
393 | * the booted_cores for this new cpu | |
394 | */ | |
c2d1cec1 | 395 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
396 | c->booted_cores++; |
397 | /* | |
398 | * increment the core count for all | |
399 | * the other cpus in this package | |
400 | */ | |
401 | if (i != cpu) | |
402 | cpu_data(i).booted_cores++; | |
403 | } else if (i != cpu && !c->booted_cores) | |
404 | c->booted_cores = cpu_data(i).booted_cores; | |
405 | } | |
406 | } | |
407 | } | |
408 | ||
70708a18 | 409 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 410 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
411 | { |
412 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
413 | /* | |
414 | * For perf, we return last level cache shared map. | |
415 | * And for power savings, we return cpu_core_map | |
416 | */ | |
5a925b42 AH |
417 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
418 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 419 | return cpu_core_mask(cpu); |
70708a18 | 420 | else |
b3d7336d | 421 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
422 | } |
423 | ||
a4928cff | 424 | static void impress_friends(void) |
904541e2 GOC |
425 | { |
426 | int cpu; | |
427 | unsigned long bogosum = 0; | |
428 | /* | |
429 | * Allow the user to impress friends. | |
430 | */ | |
cfc1b9a6 | 431 | pr_debug("Before bogomips.\n"); |
904541e2 | 432 | for_each_possible_cpu(cpu) |
c2d1cec1 | 433 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
434 | bogosum += cpu_data(cpu).loops_per_jiffy; |
435 | printk(KERN_INFO | |
436 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 437 | num_online_cpus(), |
904541e2 GOC |
438 | bogosum/(500000/HZ), |
439 | (bogosum/(5000/HZ))%100); | |
440 | ||
cfc1b9a6 | 441 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
442 | } |
443 | ||
569712b2 | 444 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
445 | { |
446 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 447 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
448 | int timeout; |
449 | u32 status; | |
450 | ||
823b259b | 451 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
452 | |
453 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 454 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
455 | |
456 | /* | |
457 | * Wait for idle. | |
458 | */ | |
459 | status = safe_apic_wait_icr_idle(); | |
460 | if (status) | |
461 | printk(KERN_CONT | |
462 | "a previous APIC delivery may have failed\n"); | |
463 | ||
1b374e4d | 464 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
465 | |
466 | timeout = 0; | |
467 | do { | |
468 | udelay(100); | |
469 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
470 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
471 | ||
472 | switch (status) { | |
473 | case APIC_ICR_RR_VALID: | |
474 | status = apic_read(APIC_RRR); | |
475 | printk(KERN_CONT "%08x\n", status); | |
476 | break; | |
477 | default: | |
478 | printk(KERN_CONT "failed\n"); | |
479 | } | |
480 | } | |
481 | } | |
482 | ||
cb3c8b90 GOC |
483 | /* |
484 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
485 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
486 | * won't ... remember to clear down the APIC, etc later. | |
487 | */ | |
cece3155 | 488 | int __cpuinit |
569712b2 | 489 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
490 | { |
491 | unsigned long send_status, accept_status = 0; | |
492 | int maxlvt; | |
493 | ||
494 | /* Target chip */ | |
cb3c8b90 GOC |
495 | /* Boot on the stack */ |
496 | /* Kick the second */ | |
bdb1a9b6 | 497 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 498 | |
cfc1b9a6 | 499 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
500 | send_status = safe_apic_wait_icr_idle(); |
501 | ||
502 | /* | |
503 | * Give the other CPU some time to accept the IPI. | |
504 | */ | |
505 | udelay(200); | |
569712b2 | 506 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
507 | maxlvt = lapic_get_maxlvt(); |
508 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
509 | apic_write(APIC_ESR, 0); | |
510 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
511 | } | |
cfc1b9a6 | 512 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
513 | |
514 | if (send_status) | |
515 | printk(KERN_ERR "APIC never delivered???\n"); | |
516 | if (accept_status) | |
517 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
518 | ||
519 | return (send_status | accept_status); | |
520 | } | |
cb3c8b90 | 521 | |
cece3155 | 522 | static int __cpuinit |
569712b2 | 523 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
524 | { |
525 | unsigned long send_status, accept_status = 0; | |
526 | int maxlvt, num_starts, j; | |
527 | ||
593f4a78 MR |
528 | maxlvt = lapic_get_maxlvt(); |
529 | ||
cb3c8b90 GOC |
530 | /* |
531 | * Be paranoid about clearing APIC errors. | |
532 | */ | |
533 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
534 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
535 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
536 | apic_read(APIC_ESR); |
537 | } | |
538 | ||
cfc1b9a6 | 539 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
540 | |
541 | /* | |
542 | * Turn INIT on target chip | |
543 | */ | |
cb3c8b90 GOC |
544 | /* |
545 | * Send IPI | |
546 | */ | |
1b374e4d SS |
547 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
548 | phys_apicid); | |
cb3c8b90 | 549 | |
cfc1b9a6 | 550 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
551 | send_status = safe_apic_wait_icr_idle(); |
552 | ||
553 | mdelay(10); | |
554 | ||
cfc1b9a6 | 555 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
556 | |
557 | /* Target chip */ | |
cb3c8b90 | 558 | /* Send IPI */ |
1b374e4d | 559 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 560 | |
cfc1b9a6 | 561 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
562 | send_status = safe_apic_wait_icr_idle(); |
563 | ||
564 | mb(); | |
565 | atomic_set(&init_deasserted, 1); | |
566 | ||
567 | /* | |
568 | * Should we send STARTUP IPIs ? | |
569 | * | |
570 | * Determine this based on the APIC version. | |
571 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
572 | */ | |
573 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
574 | num_starts = 2; | |
575 | else | |
576 | num_starts = 0; | |
577 | ||
578 | /* | |
579 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
580 | * target processor state. | |
581 | */ | |
582 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 583 | stack_start); |
cb3c8b90 GOC |
584 | |
585 | /* | |
586 | * Run STARTUP IPI loop. | |
587 | */ | |
cfc1b9a6 | 588 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 589 | |
cb3c8b90 | 590 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 591 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
592 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
593 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 594 | apic_read(APIC_ESR); |
cfc1b9a6 | 595 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
596 | |
597 | /* | |
598 | * STARTUP IPI | |
599 | */ | |
600 | ||
601 | /* Target chip */ | |
cb3c8b90 GOC |
602 | /* Boot on the stack */ |
603 | /* Kick the second */ | |
1b374e4d SS |
604 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
605 | phys_apicid); | |
cb3c8b90 GOC |
606 | |
607 | /* | |
608 | * Give the other CPU some time to accept the IPI. | |
609 | */ | |
610 | udelay(300); | |
611 | ||
cfc1b9a6 | 612 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 613 | |
cfc1b9a6 | 614 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
615 | send_status = safe_apic_wait_icr_idle(); |
616 | ||
617 | /* | |
618 | * Give the other CPU some time to accept the IPI. | |
619 | */ | |
620 | udelay(200); | |
593f4a78 | 621 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 622 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
623 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
624 | if (send_status || accept_status) | |
625 | break; | |
626 | } | |
cfc1b9a6 | 627 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
628 | |
629 | if (send_status) | |
630 | printk(KERN_ERR "APIC never delivered???\n"); | |
631 | if (accept_status) | |
632 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
633 | ||
634 | return (send_status | accept_status); | |
635 | } | |
cb3c8b90 GOC |
636 | |
637 | struct create_idle { | |
638 | struct work_struct work; | |
639 | struct task_struct *idle; | |
640 | struct completion done; | |
641 | int cpu; | |
642 | }; | |
643 | ||
644 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
645 | { | |
646 | struct create_idle *c_idle = | |
647 | container_of(work, struct create_idle, work); | |
648 | ||
649 | c_idle->idle = fork_idle(c_idle->cpu); | |
650 | complete(&c_idle->done); | |
651 | } | |
652 | ||
2eaad1fd MT |
653 | /* reduce the number of lines printed when booting a large cpu count system */ |
654 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
655 | { | |
656 | static int current_node = -1; | |
4adc8b71 | 657 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
658 | |
659 | if (system_state == SYSTEM_BOOTING) { | |
660 | if (node != current_node) { | |
661 | if (current_node > (-1)) | |
662 | pr_cont(" Ok.\n"); | |
663 | current_node = node; | |
664 | pr_info("Booting Node %3d, Processors ", node); | |
665 | } | |
666 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
667 | return; | |
668 | } else | |
669 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
670 | node, cpu, apicid); | |
671 | } | |
672 | ||
cb3c8b90 GOC |
673 | /* |
674 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
675 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
676 | * Returns zero if CPU booted OK, else error code from |
677 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 678 | */ |
ab6fb7c0 | 679 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
680 | { |
681 | unsigned long boot_error = 0; | |
cb3c8b90 | 682 | unsigned long start_ip; |
ab6fb7c0 | 683 | int timeout; |
cb3c8b90 | 684 | struct create_idle c_idle = { |
ab6fb7c0 IM |
685 | .cpu = cpu, |
686 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 687 | }; |
ab6fb7c0 | 688 | |
ca1cab37 | 689 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 690 | |
cb3c8b90 GOC |
691 | alternatives_smp_switch(1); |
692 | ||
693 | c_idle.idle = get_idle_for_cpu(cpu); | |
694 | ||
695 | /* | |
696 | * We can't use kernel_thread since we must avoid to | |
697 | * reschedule the child. | |
698 | */ | |
699 | if (c_idle.idle) { | |
700 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
701 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
702 | init_idle(c_idle.idle, cpu); | |
703 | goto do_rest; | |
704 | } | |
705 | ||
d7a7c573 SS |
706 | schedule_work(&c_idle.work); |
707 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
708 | |
709 | if (IS_ERR(c_idle.idle)) { | |
710 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 711 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
712 | return PTR_ERR(c_idle.idle); |
713 | } | |
714 | ||
715 | set_idle_for_cpu(cpu, c_idle.idle); | |
716 | do_rest: | |
cb3c8b90 | 717 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 718 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 719 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
720 | irq_ctx_init(cpu); |
721 | #else | |
cb3c8b90 | 722 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 723 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
724 | per_cpu(kernel_stack, cpu) = |
725 | (unsigned long)task_stack_page(c_idle.idle) - | |
726 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 727 | #endif |
a939098a | 728 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 729 | initial_code = (unsigned long)start_secondary; |
11d4c3f9 | 730 | stack_start = c_idle.idle->thread.sp; |
cb3c8b90 GOC |
731 | |
732 | /* start_ip had better be page-aligned! */ | |
4822b7fc | 733 | start_ip = trampoline_address(); |
cb3c8b90 | 734 | |
2eaad1fd MT |
735 | /* So we see what's up */ |
736 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
737 | |
738 | /* | |
739 | * This grunge runs the startup process for | |
740 | * the targeted processor. | |
741 | */ | |
742 | ||
4822b7fc PA |
743 | printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip); |
744 | ||
cb3c8b90 GOC |
745 | atomic_set(&init_deasserted, 0); |
746 | ||
34d05591 | 747 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 748 | |
cfc1b9a6 | 749 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 750 | |
34d05591 JS |
751 | smpboot_setup_warm_reset_vector(start_ip); |
752 | /* | |
753 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
754 | */ |
755 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
756 | apic_write(APIC_ESR, 0); | |
757 | apic_read(APIC_ESR); | |
758 | } | |
34d05591 | 759 | } |
cb3c8b90 | 760 | |
cb3c8b90 | 761 | /* |
1f5bcabf IM |
762 | * Kick the secondary CPU. Use the method in the APIC driver |
763 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 764 | */ |
1f5bcabf IM |
765 | if (apic->wakeup_secondary_cpu) |
766 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
767 | else | |
768 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
769 | |
770 | if (!boot_error) { | |
771 | /* | |
772 | * allow APs to start initializing. | |
773 | */ | |
cfc1b9a6 | 774 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 775 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 776 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
777 | |
778 | /* | |
779 | * Wait 5s total for a response | |
780 | */ | |
781 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 782 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
783 | break; /* It has booted */ |
784 | udelay(100); | |
68f202e4 SS |
785 | /* |
786 | * Allow other tasks to run while we wait for the | |
787 | * AP to come online. This also gives a chance | |
788 | * for the MTRR work(triggered by the AP coming online) | |
789 | * to be completed in the stop machine context. | |
790 | */ | |
791 | schedule(); | |
cb3c8b90 GOC |
792 | } |
793 | ||
21c3fcf3 YL |
794 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
795 | print_cpu_msr(&cpu_data(cpu)); | |
2eaad1fd | 796 | pr_debug("CPU%d: has booted.\n", cpu); |
21c3fcf3 | 797 | } else { |
cb3c8b90 | 798 | boot_error = 1; |
4822b7fc PA |
799 | if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) |
800 | == 0xA5A5A5A5) | |
cb3c8b90 | 801 | /* trampoline started but...? */ |
2eaad1fd | 802 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
803 | else |
804 | /* trampoline code not run */ | |
2eaad1fd | 805 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
806 | if (apic->inquire_remote_apic) |
807 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
808 | } |
809 | } | |
1a51e3a0 | 810 | |
cb3c8b90 GOC |
811 | if (boot_error) { |
812 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 813 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
814 | |
815 | /* was set by do_boot_cpu() */ | |
816 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
817 | ||
818 | /* was set by cpu_init() */ | |
819 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
820 | ||
821 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
822 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
823 | } | |
824 | ||
825 | /* mark "stuck" area as not stuck */ | |
4822b7fc | 826 | *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; |
cb3c8b90 | 827 | |
02421f98 YL |
828 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
829 | /* | |
830 | * Cleanup possible dangling ends... | |
831 | */ | |
832 | smpboot_restore_warm_reset_vector(); | |
833 | } | |
63d38198 | 834 | |
dc186ad7 | 835 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
836 | return boot_error; |
837 | } | |
838 | ||
839 | int __cpuinit native_cpu_up(unsigned int cpu) | |
840 | { | |
a21769a4 | 841 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
842 | unsigned long flags; |
843 | int err; | |
844 | ||
845 | WARN_ON(irqs_disabled()); | |
846 | ||
cfc1b9a6 | 847 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
848 | |
849 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
c284b42a SS |
850 | !physid_isset(apicid, phys_cpu_present_map) || |
851 | (!x2apic_mode && apicid >= 255)) { | |
cb3c8b90 GOC |
852 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); |
853 | return -EINVAL; | |
854 | } | |
855 | ||
856 | /* | |
857 | * Already booted CPU? | |
858 | */ | |
c2d1cec1 | 859 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 860 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
861 | return -ENOSYS; |
862 | } | |
863 | ||
864 | /* | |
865 | * Save current MTRR state in case it was changed since early boot | |
866 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
867 | */ | |
868 | mtrr_save_state(); | |
869 | ||
870 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
871 | ||
cb3c8b90 | 872 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 873 | if (err) { |
cfc1b9a6 | 874 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 875 | return -EIO; |
cb3c8b90 GOC |
876 | } |
877 | ||
878 | /* | |
879 | * Check TSC synchronization with the AP (keep irqs disabled | |
880 | * while doing so): | |
881 | */ | |
882 | local_irq_save(flags); | |
883 | check_tsc_sync_source(cpu); | |
884 | local_irq_restore(flags); | |
885 | ||
7c04e64a | 886 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
887 | cpu_relax(); |
888 | touch_nmi_watchdog(); | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
7167d08e HK |
894 | /** |
895 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
896 | */ | |
897 | void arch_disable_smp_support(void) | |
898 | { | |
899 | disable_ioapic_support(); | |
900 | } | |
901 | ||
8aef135c GOC |
902 | /* |
903 | * Fall back to non SMP mode after errors. | |
904 | * | |
905 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
906 | */ | |
907 | static __init void disable_smp(void) | |
908 | { | |
4f062896 RR |
909 | init_cpu_present(cpumask_of(0)); |
910 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 911 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 912 | |
8aef135c | 913 | if (smp_found_config) |
b6df1b8b | 914 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 915 | else |
b6df1b8b | 916 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
917 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
918 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
919 | } |
920 | ||
921 | /* | |
922 | * Various sanity checks. | |
923 | */ | |
924 | static int __init smp_sanity_check(unsigned max_cpus) | |
925 | { | |
ac23d4ee | 926 | preempt_disable(); |
a58f03b0 | 927 | |
1ff2f20d | 928 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
929 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
930 | unsigned int cpu; | |
931 | unsigned nr; | |
932 | ||
933 | printk(KERN_WARNING | |
934 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 935 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
936 | |
937 | nr = 0; | |
938 | for_each_present_cpu(cpu) { | |
939 | if (nr >= 8) | |
c2d1cec1 | 940 | set_cpu_present(cpu, false); |
a58f03b0 YL |
941 | nr++; |
942 | } | |
943 | ||
944 | nr = 0; | |
945 | for_each_possible_cpu(cpu) { | |
946 | if (nr >= 8) | |
c2d1cec1 | 947 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
948 | nr++; |
949 | } | |
950 | ||
951 | nr_cpu_ids = 8; | |
952 | } | |
953 | #endif | |
954 | ||
8aef135c | 955 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
956 | printk(KERN_WARNING |
957 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
958 | hard_smp_processor_id()); | |
959 | ||
8aef135c GOC |
960 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
961 | } | |
962 | ||
963 | /* | |
964 | * If we couldn't find an SMP configuration at boot time, | |
965 | * get out of here now! | |
966 | */ | |
967 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 968 | preempt_enable(); |
8aef135c GOC |
969 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
970 | disable_smp(); | |
971 | if (APIC_init_uniprocessor()) | |
972 | printk(KERN_NOTICE "Local APIC not detected." | |
973 | " Using dummy APIC emulation.\n"); | |
974 | return -1; | |
975 | } | |
976 | ||
977 | /* | |
978 | * Should not be necessary because the MP table should list the boot | |
979 | * CPU too, but we do it for the sake of robustness anyway. | |
980 | */ | |
a27a6210 | 981 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
982 | printk(KERN_NOTICE |
983 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
984 | boot_cpu_physical_apicid); | |
985 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
986 | } | |
ac23d4ee | 987 | preempt_enable(); |
8aef135c GOC |
988 | |
989 | /* | |
990 | * If we couldn't find a local APIC, then get out of here now! | |
991 | */ | |
992 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
993 | !cpu_has_apic) { | |
103428e5 CG |
994 | if (!disable_apic) { |
995 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
996 | boot_cpu_physical_apicid); | |
997 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 998 | "(tell your hw vendor)\n"); |
103428e5 | 999 | } |
8aef135c | 1000 | smpboot_clear_io_apic(); |
7167d08e | 1001 | disable_ioapic_support(); |
8aef135c GOC |
1002 | return -1; |
1003 | } | |
1004 | ||
1005 | verify_local_APIC(); | |
1006 | ||
1007 | /* | |
1008 | * If SMP should be disabled, then really disable it! | |
1009 | */ | |
1010 | if (!max_cpus) { | |
73d08e63 | 1011 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1012 | smpboot_clear_io_apic(); |
d54db1ac | 1013 | |
e90955c2 | 1014 | connect_bsp_APIC(); |
e90955c2 | 1015 | setup_local_APIC(); |
2fb270f3 | 1016 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
1017 | return -1; |
1018 | } | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static void __init smp_cpu_index_default(void) | |
1024 | { | |
1025 | int i; | |
1026 | struct cpuinfo_x86 *c; | |
1027 | ||
7c04e64a | 1028 | for_each_possible_cpu(i) { |
8aef135c GOC |
1029 | c = &cpu_data(i); |
1030 | /* mark all to hotplug */ | |
9628937d | 1031 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1032 | } |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1037 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1038 | */ | |
1039 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1040 | { | |
7ad728f9 RR |
1041 | unsigned int i; |
1042 | ||
deef3250 | 1043 | preempt_disable(); |
8aef135c | 1044 | smp_cpu_index_default(); |
792363d2 | 1045 | |
8aef135c GOC |
1046 | /* |
1047 | * Setup boot CPU information | |
1048 | */ | |
1049 | smp_store_cpu_info(0); /* Final full version of the data */ | |
792363d2 YL |
1050 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1051 | mb(); | |
bd22a2f1 | 1052 | |
8aef135c | 1053 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1054 | for_each_possible_cpu(i) { |
79f55997 LZ |
1055 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1056 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1057 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1058 | } |
8aef135c GOC |
1059 | set_cpu_sibling_map(0); |
1060 | ||
6e1cb38a | 1061 | |
8aef135c GOC |
1062 | if (smp_sanity_check(max_cpus) < 0) { |
1063 | printk(KERN_INFO "SMP disabled\n"); | |
1064 | disable_smp(); | |
deef3250 | 1065 | goto out; |
8aef135c GOC |
1066 | } |
1067 | ||
fa47f7e5 SS |
1068 | default_setup_apic_routing(); |
1069 | ||
ac23d4ee | 1070 | preempt_disable(); |
4c9961d5 | 1071 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1072 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1073 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1074 | /* Or can we switch back to PIC here? */ |
1075 | } | |
ac23d4ee | 1076 | preempt_enable(); |
8aef135c | 1077 | |
8aef135c | 1078 | connect_bsp_APIC(); |
b5841765 | 1079 | |
8aef135c GOC |
1080 | /* |
1081 | * Switch from PIC to APIC mode. | |
1082 | */ | |
1083 | setup_local_APIC(); | |
1084 | ||
8aef135c GOC |
1085 | /* |
1086 | * Enable IO APIC before setting up error vector | |
1087 | */ | |
1088 | if (!skip_ioapic_setup && nr_ioapics) | |
1089 | enable_IO_APIC(); | |
88d0f550 | 1090 | |
2fb270f3 | 1091 | bsp_end_local_APIC_setup(); |
8aef135c | 1092 | |
d83093b5 IM |
1093 | if (apic->setup_portio_remap) |
1094 | apic->setup_portio_remap(); | |
8aef135c GOC |
1095 | |
1096 | smpboot_setup_io_apic(); | |
1097 | /* | |
1098 | * Set up local APIC timer on boot CPU. | |
1099 | */ | |
1100 | ||
1101 | printk(KERN_INFO "CPU%d: ", 0); | |
1102 | print_cpu_info(&cpu_data(0)); | |
736decac | 1103 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1104 | |
1105 | if (is_uv_system()) | |
1106 | uv_system_init(); | |
d0af9eed SS |
1107 | |
1108 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1109 | out: |
1110 | preempt_enable(); | |
8aef135c | 1111 | } |
d0af9eed | 1112 | |
3fb82d56 SS |
1113 | void arch_disable_nonboot_cpus_begin(void) |
1114 | { | |
1115 | /* | |
1116 | * Avoid the smp alternatives switch during the disable_nonboot_cpus(). | |
1117 | * In the suspend path, we will be back in the SMP mode shortly anyways. | |
1118 | */ | |
1119 | skip_smp_alternatives = true; | |
1120 | } | |
1121 | ||
1122 | void arch_disable_nonboot_cpus_end(void) | |
1123 | { | |
1124 | skip_smp_alternatives = false; | |
1125 | } | |
1126 | ||
d0af9eed SS |
1127 | void arch_enable_nonboot_cpus_begin(void) |
1128 | { | |
1129 | set_mtrr_aps_delayed_init(); | |
1130 | } | |
1131 | ||
1132 | void arch_enable_nonboot_cpus_end(void) | |
1133 | { | |
1134 | mtrr_aps_init(); | |
1135 | } | |
1136 | ||
a8db8453 GOC |
1137 | /* |
1138 | * Early setup to make printk work. | |
1139 | */ | |
1140 | void __init native_smp_prepare_boot_cpu(void) | |
1141 | { | |
1142 | int me = smp_processor_id(); | |
552be871 | 1143 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1144 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1145 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1146 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1147 | } | |
1148 | ||
83f7eb9c GOC |
1149 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1150 | { | |
cfc1b9a6 | 1151 | pr_debug("Boot done.\n"); |
83f7eb9c | 1152 | |
99e8b9ca | 1153 | nmi_selftest(); |
83f7eb9c | 1154 | impress_friends(); |
83f7eb9c GOC |
1155 | #ifdef CONFIG_X86_IO_APIC |
1156 | setup_ioapic_dest(); | |
1157 | #endif | |
d0af9eed | 1158 | mtrr_aps_init(); |
83f7eb9c GOC |
1159 | } |
1160 | ||
3b11ce7f MT |
1161 | static int __initdata setup_possible_cpus = -1; |
1162 | static int __init _setup_possible_cpus(char *str) | |
1163 | { | |
1164 | get_option(&str, &setup_possible_cpus); | |
1165 | return 0; | |
1166 | } | |
1167 | early_param("possible_cpus", _setup_possible_cpus); | |
1168 | ||
1169 | ||
68a1c3f8 | 1170 | /* |
4f062896 | 1171 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1172 | * are onlined, or offlined. The reason is per-cpu data-structures |
1173 | * are allocated by some modules at init time, and dont expect to | |
1174 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1175 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1176 | * In case when cpu_hotplug is not compiled, then we resort to current |
1177 | * behaviour, which is cpu_possible == cpu_present. | |
1178 | * - Ashok Raj | |
1179 | * | |
1180 | * Three ways to find out the number of additional hotplug CPUs: | |
1181 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1182 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1183 | * - Otherwise don't reserve additional CPUs. |
1184 | * We do this because additional CPUs waste a lot of memory. | |
1185 | * -AK | |
1186 | */ | |
1187 | __init void prefill_possible_map(void) | |
1188 | { | |
cb48bb59 | 1189 | int i, possible; |
68a1c3f8 | 1190 | |
329513a3 YL |
1191 | /* no processor from mptable or madt */ |
1192 | if (!num_processors) | |
1193 | num_processors = 1; | |
1194 | ||
5f2eb550 JB |
1195 | i = setup_max_cpus ?: 1; |
1196 | if (setup_possible_cpus == -1) { | |
1197 | possible = num_processors; | |
1198 | #ifdef CONFIG_HOTPLUG_CPU | |
1199 | if (setup_max_cpus) | |
1200 | possible += disabled_cpus; | |
1201 | #else | |
1202 | if (possible > i) | |
1203 | possible = i; | |
1204 | #endif | |
1205 | } else | |
3b11ce7f MT |
1206 | possible = setup_possible_cpus; |
1207 | ||
730cf272 MT |
1208 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1209 | ||
2b633e3f YL |
1210 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1211 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1212 | printk(KERN_WARNING |
1213 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1214 | possible, nr_cpu_ids); |
1215 | possible = nr_cpu_ids; | |
3b11ce7f | 1216 | } |
68a1c3f8 | 1217 | |
5f2eb550 JB |
1218 | #ifdef CONFIG_HOTPLUG_CPU |
1219 | if (!setup_max_cpus) | |
1220 | #endif | |
1221 | if (possible > i) { | |
1222 | printk(KERN_WARNING | |
1223 | "%d Processors exceeds max_cpus limit of %u\n", | |
1224 | possible, setup_max_cpus); | |
1225 | possible = i; | |
1226 | } | |
1227 | ||
68a1c3f8 GC |
1228 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1229 | possible, max_t(int, possible - num_processors, 0)); | |
1230 | ||
1231 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1232 | set_cpu_possible(i, true); |
5f2eb550 JB |
1233 | for (; i < NR_CPUS; i++) |
1234 | set_cpu_possible(i, false); | |
3461b0af MT |
1235 | |
1236 | nr_cpu_ids = possible; | |
68a1c3f8 | 1237 | } |
69c18c15 | 1238 | |
14adf855 CE |
1239 | #ifdef CONFIG_HOTPLUG_CPU |
1240 | ||
1241 | static void remove_siblinginfo(int cpu) | |
1242 | { | |
1243 | int sibling; | |
1244 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1245 | ||
c2d1cec1 MT |
1246 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1247 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1248 | /*/ |
1249 | * last thread sibling in this cpu core going down | |
1250 | */ | |
c2d1cec1 | 1251 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1252 | cpu_data(sibling).booted_cores--; |
1253 | } | |
1254 | ||
c2d1cec1 MT |
1255 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1256 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1257 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1258 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1259 | c->phys_proc_id = 0; |
1260 | c->cpu_core_id = 0; | |
c2d1cec1 | 1261 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1262 | } |
1263 | ||
69c18c15 GC |
1264 | static void __ref remove_cpu_from_maps(int cpu) |
1265 | { | |
c2d1cec1 MT |
1266 | set_cpu_online(cpu, false); |
1267 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1268 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1269 | /* was set by cpu_init() */ |
c2d1cec1 | 1270 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1271 | numa_remove_cpu(cpu); |
69c18c15 GC |
1272 | } |
1273 | ||
8227dce7 | 1274 | void cpu_disable_common(void) |
69c18c15 GC |
1275 | { |
1276 | int cpu = smp_processor_id(); | |
69c18c15 | 1277 | |
69c18c15 GC |
1278 | remove_siblinginfo(cpu); |
1279 | ||
1280 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1281 | lock_vector_lock(); |
69c18c15 | 1282 | remove_cpu_from_maps(cpu); |
d388e5fd | 1283 | unlock_vector_lock(); |
d7b381bb | 1284 | fixup_irqs(); |
8227dce7 AN |
1285 | } |
1286 | ||
1287 | int native_cpu_disable(void) | |
1288 | { | |
1289 | int cpu = smp_processor_id(); | |
1290 | ||
1291 | /* | |
1292 | * Perhaps use cpufreq to drop frequency, but that could go | |
1293 | * into generic code. | |
1294 | * | |
1295 | * We won't take down the boot processor on i386 due to some | |
1296 | * interrupts only being able to be serviced by the BSP. | |
1297 | * Especially so if we're not using an IOAPIC -zwane | |
1298 | */ | |
1299 | if (cpu == 0) | |
1300 | return -EBUSY; | |
1301 | ||
8227dce7 AN |
1302 | clear_local_APIC(); |
1303 | ||
1304 | cpu_disable_common(); | |
69c18c15 GC |
1305 | return 0; |
1306 | } | |
1307 | ||
93be71b6 | 1308 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1309 | { |
1310 | /* We don't do anything here: idle task is faking death itself. */ | |
1311 | unsigned int i; | |
1312 | ||
1313 | for (i = 0; i < 10; i++) { | |
1314 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1315 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1316 | if (system_state == SYSTEM_RUNNING) |
1317 | pr_info("CPU %u is now offline\n", cpu); | |
1318 | ||
69c18c15 GC |
1319 | if (1 == num_online_cpus()) |
1320 | alternatives_smp_switch(0); | |
1321 | return; | |
1322 | } | |
1323 | msleep(100); | |
1324 | } | |
2eaad1fd | 1325 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1326 | } |
a21f5d88 AN |
1327 | |
1328 | void play_dead_common(void) | |
1329 | { | |
1330 | idle_task_exit(); | |
1331 | reset_lazy_tlbstate(); | |
02c68a02 | 1332 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1333 | |
1334 | mb(); | |
1335 | /* Ack it */ | |
0a3aee0d | 1336 | __this_cpu_write(cpu_state, CPU_DEAD); |
a21f5d88 AN |
1337 | |
1338 | /* | |
1339 | * With physical CPU hotplug, we should halt the cpu | |
1340 | */ | |
1341 | local_irq_disable(); | |
1342 | } | |
1343 | ||
ea530692 PA |
1344 | /* |
1345 | * We need to flush the caches before going to sleep, lest we have | |
1346 | * dirty data in our caches when we come back up. | |
1347 | */ | |
1348 | static inline void mwait_play_dead(void) | |
1349 | { | |
1350 | unsigned int eax, ebx, ecx, edx; | |
1351 | unsigned int highest_cstate = 0; | |
1352 | unsigned int highest_subcstate = 0; | |
1353 | int i; | |
ce5f6824 | 1354 | void *mwait_ptr; |
93789b32 | 1355 | struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); |
ea530692 | 1356 | |
4f3c125c | 1357 | if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) |
ea530692 | 1358 | return; |
349c004e | 1359 | if (!this_cpu_has(X86_FEATURE_CLFLSH)) |
ce5f6824 | 1360 | return; |
7b543a53 | 1361 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1362 | return; |
1363 | ||
1364 | eax = CPUID_MWAIT_LEAF; | |
1365 | ecx = 0; | |
1366 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1367 | ||
1368 | /* | |
1369 | * eax will be 0 if EDX enumeration is not valid. | |
1370 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1371 | */ | |
1372 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1373 | eax = 0; | |
1374 | } else { | |
1375 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1376 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1377 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1378 | highest_cstate = i; | |
1379 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1380 | } | |
1381 | } | |
1382 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1383 | (highest_subcstate - 1); | |
1384 | } | |
1385 | ||
ce5f6824 PA |
1386 | /* |
1387 | * This should be a memory location in a cache line which is | |
1388 | * unlikely to be touched by other processors. The actual | |
1389 | * content is immaterial as it is not actually modified in any way. | |
1390 | */ | |
1391 | mwait_ptr = ¤t_thread_info()->flags; | |
1392 | ||
a68e5c94 PA |
1393 | wbinvd(); |
1394 | ||
ea530692 | 1395 | while (1) { |
ce5f6824 PA |
1396 | /* |
1397 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1398 | * the Xeon 7400 series. It's not clear it is actually | |
1399 | * needed, but it should be harmless in either case. | |
1400 | * The WBINVD is insufficient due to the spurious-wakeup | |
1401 | * case where we return around the loop. | |
1402 | */ | |
1403 | clflush(mwait_ptr); | |
1404 | __monitor(mwait_ptr, 0, 0); | |
ea530692 PA |
1405 | mb(); |
1406 | __mwait(eax, 0); | |
1407 | } | |
1408 | } | |
1409 | ||
1410 | static inline void hlt_play_dead(void) | |
1411 | { | |
7b543a53 | 1412 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1413 | wbinvd(); |
1414 | ||
ea530692 | 1415 | while (1) { |
ea530692 PA |
1416 | native_halt(); |
1417 | } | |
1418 | } | |
1419 | ||
a21f5d88 AN |
1420 | void native_play_dead(void) |
1421 | { | |
1422 | play_dead_common(); | |
86886e55 | 1423 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1424 | |
1425 | mwait_play_dead(); /* Only returns on failure */ | |
1426 | hlt_play_dead(); | |
a21f5d88 AN |
1427 | } |
1428 | ||
69c18c15 | 1429 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1430 | int native_cpu_disable(void) |
69c18c15 GC |
1431 | { |
1432 | return -ENOSYS; | |
1433 | } | |
1434 | ||
93be71b6 | 1435 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1436 | { |
1437 | /* We said "no" in __cpu_disable */ | |
1438 | BUG(); | |
1439 | } | |
a21f5d88 AN |
1440 | |
1441 | void native_play_dead(void) | |
1442 | { | |
1443 | BUG(); | |
1444 | } | |
1445 | ||
68a1c3f8 | 1446 | #endif |