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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
644c1541 VP |
71 | #include <asm/i387.h> |
72 | #include <asm/fpu-internal.h> | |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
b81bb373 | 76 | #include <asm/i8259.h> |
48927bbb | 77 | #include <asm/realmode.h> |
646e29a1 | 78 | #include <asm/misc.h> |
48927bbb | 79 | |
a8db8453 GOC |
80 | /* State of each CPU */ |
81 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
82 | ||
a355352b GC |
83 | /* Number of siblings per CPU package */ |
84 | int smp_num_siblings = 1; | |
85 | EXPORT_SYMBOL(smp_num_siblings); | |
86 | ||
87 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 88 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 89 | |
a355352b | 90 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
93 | ||
94 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
96 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
97 | ||
0816b0f0 | 98 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 99 | |
a355352b | 100 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 101 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 102 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 103 | |
2b6163bf | 104 | atomic_t init_deasserted; |
cb3c8b90 | 105 | |
f77aa308 TG |
106 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
107 | { | |
108 | unsigned long flags; | |
109 | ||
110 | spin_lock_irqsave(&rtc_lock, flags); | |
111 | CMOS_WRITE(0xa, 0xf); | |
112 | spin_unlock_irqrestore(&rtc_lock, flags); | |
113 | local_flush_tlb(); | |
114 | pr_debug("1.\n"); | |
115 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
116 | start_eip >> 4; | |
117 | pr_debug("2.\n"); | |
118 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
119 | start_eip & 0xf; | |
120 | pr_debug("3.\n"); | |
121 | } | |
122 | ||
123 | static inline void smpboot_restore_warm_reset_vector(void) | |
124 | { | |
125 | unsigned long flags; | |
126 | ||
127 | /* | |
128 | * Install writable page 0 entry to set BIOS data area. | |
129 | */ | |
130 | local_flush_tlb(); | |
131 | ||
132 | /* | |
133 | * Paranoid: Set warm reset code and vector here back | |
134 | * to default values. | |
135 | */ | |
136 | spin_lock_irqsave(&rtc_lock, flags); | |
137 | CMOS_WRITE(0, 0xf); | |
138 | spin_unlock_irqrestore(&rtc_lock, flags); | |
139 | ||
140 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
141 | } | |
142 | ||
cb3c8b90 | 143 | /* |
30106c17 FY |
144 | * Report back to the Boot Processor during boot time or to the caller processor |
145 | * during CPU online. | |
cb3c8b90 | 146 | */ |
148f9bb8 | 147 | static void smp_callin(void) |
cb3c8b90 GOC |
148 | { |
149 | int cpuid, phys_id; | |
cb3c8b90 GOC |
150 | |
151 | /* | |
152 | * If waken up by an INIT in an 82489DX configuration | |
153 | * we may get here before an INIT-deassert IPI reaches | |
154 | * our local APIC. We have to wait for the IPI or we'll | |
155 | * lock up on an APIC access. | |
e1c467e6 FY |
156 | * |
157 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 158 | */ |
e1c467e6 | 159 | cpuid = smp_processor_id(); |
465822cf DR |
160 | if (apic->wait_for_init_deassert && cpuid) |
161 | while (!atomic_read(&init_deasserted)) | |
162 | cpu_relax(); | |
cb3c8b90 GOC |
163 | |
164 | /* | |
165 | * (This works even if the APIC is not enabled.) | |
166 | */ | |
4c9961d5 | 167 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
168 | |
169 | /* | |
170 | * the boot CPU has finished the init stage and is spinning | |
171 | * on callin_map until we finish. We are free to set up this | |
172 | * CPU, first the APIC. (this is probably redundant on most | |
173 | * boards) | |
174 | */ | |
cb3c8b90 GOC |
175 | setup_local_APIC(); |
176 | end_local_APIC_setup(); | |
cb3c8b90 | 177 | |
9d133e5d SS |
178 | /* |
179 | * Need to setup vector mappings before we enable interrupts. | |
180 | */ | |
36e9e1ea | 181 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
182 | |
183 | /* | |
184 | * Save our processor parameters. Note: this information | |
185 | * is needed for clock calibration. | |
186 | */ | |
187 | smp_store_cpu_info(cpuid); | |
188 | ||
cb3c8b90 GOC |
189 | /* |
190 | * Get our bogomips. | |
b565201c JS |
191 | * Update loops_per_jiffy in cpu_data. Previous call to |
192 | * smp_store_cpu_info() stored a value that is close but not as | |
193 | * accurate as the value just calculated. | |
cb3c8b90 | 194 | */ |
cb3c8b90 | 195 | calibrate_delay(); |
b565201c | 196 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 197 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 198 | |
5ef428c4 AK |
199 | /* |
200 | * This must be done before setting cpu_online_mask | |
201 | * or calling notify_cpu_starting. | |
202 | */ | |
203 | set_cpu_sibling_map(raw_smp_processor_id()); | |
204 | wmb(); | |
205 | ||
85257024 PZ |
206 | notify_cpu_starting(cpuid); |
207 | ||
cb3c8b90 GOC |
208 | /* |
209 | * Allow the master to continue. | |
210 | */ | |
c2d1cec1 | 211 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
212 | } |
213 | ||
e1c467e6 FY |
214 | static int cpu0_logical_apicid; |
215 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
216 | /* |
217 | * Activate a secondary processor. | |
218 | */ | |
148f9bb8 | 219 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
220 | { |
221 | /* | |
222 | * Don't put *anything* before cpu_init(), SMP booting is too | |
223 | * fragile that we want to limit the things done here to the | |
224 | * most necessary things. | |
225 | */ | |
b40827fa | 226 | cpu_init(); |
df156f90 | 227 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
228 | preempt_disable(); |
229 | smp_callin(); | |
fd89a137 | 230 | |
e1c467e6 FY |
231 | enable_start_cpu0 = 0; |
232 | ||
fd89a137 | 233 | #ifdef CONFIG_X86_32 |
b40827fa | 234 | /* switch away from the initial page table */ |
fd89a137 JR |
235 | load_cr3(swapper_pg_dir); |
236 | __flush_tlb_all(); | |
237 | #endif | |
238 | ||
bbc2ff6a GOC |
239 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
240 | barrier(); | |
241 | /* | |
242 | * Check TSC synchronization with the BP: | |
243 | */ | |
244 | check_tsc_sync_target(); | |
245 | ||
3891a04a PA |
246 | /* |
247 | * Enable the espfix hack for this CPU | |
248 | */ | |
197725de | 249 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a PA |
250 | init_espfix_ap(); |
251 | #endif | |
252 | ||
bbc2ff6a | 253 | /* |
d388e5fd EB |
254 | * We need to hold vector_lock so there the set of online cpus |
255 | * does not change while we are assigning vectors to cpus. Holding | |
256 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 257 | */ |
d388e5fd | 258 | lock_vector_lock(); |
c2d1cec1 | 259 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 260 | unlock_vector_lock(); |
bbc2ff6a | 261 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 262 | x86_platform.nmi_init(); |
bbc2ff6a | 263 | |
0cefa5b9 MS |
264 | /* enable local interrupts */ |
265 | local_irq_enable(); | |
266 | ||
35f720c5 JP |
267 | /* to prevent fake stack check failure in clock setup */ |
268 | boot_init_stack_canary(); | |
0cefa5b9 | 269 | |
736decac | 270 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
271 | |
272 | wmb(); | |
7d1a9417 | 273 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
274 | } |
275 | ||
30106c17 FY |
276 | void __init smp_store_boot_cpu_info(void) |
277 | { | |
278 | int id = 0; /* CPU 0 */ | |
279 | struct cpuinfo_x86 *c = &cpu_data(id); | |
280 | ||
281 | *c = boot_cpu_data; | |
282 | c->cpu_index = id; | |
283 | } | |
284 | ||
1d89a7f0 GOC |
285 | /* |
286 | * The bootstrap kernel entry code has set these up. Save them for | |
287 | * a given CPU | |
288 | */ | |
148f9bb8 | 289 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
290 | { |
291 | struct cpuinfo_x86 *c = &cpu_data(id); | |
292 | ||
b3d7336d | 293 | *c = boot_cpu_data; |
1d89a7f0 | 294 | c->cpu_index = id; |
30106c17 FY |
295 | /* |
296 | * During boot time, CPU0 has this setup already. Save the info when | |
297 | * bringing up AP or offlined CPU0. | |
298 | */ | |
299 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
300 | } |
301 | ||
cebf15eb DH |
302 | static bool |
303 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
304 | { | |
305 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
306 | ||
307 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
308 | } | |
309 | ||
148f9bb8 | 310 | static bool |
316ad248 | 311 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 312 | { |
316ad248 PZ |
313 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
314 | ||
cebf15eb | 315 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
316 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
317 | "[node: %d != %d]. Ignoring dependency.\n", | |
318 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
319 | } | |
320 | ||
321 | #define link_mask(_m, c1, c2) \ | |
322 | do { \ | |
323 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ | |
324 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ | |
325 | } while (0) | |
326 | ||
148f9bb8 | 327 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 328 | { |
193f3fcb | 329 | if (cpu_has_topoext) { |
316ad248 PZ |
330 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
331 | ||
332 | if (c->phys_proc_id == o->phys_proc_id && | |
333 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
334 | c->compute_unit_id == o->compute_unit_id) | |
335 | return topology_sane(c, o, "smt"); | |
336 | ||
337 | } else if (c->phys_proc_id == o->phys_proc_id && | |
338 | c->cpu_core_id == o->cpu_core_id) { | |
339 | return topology_sane(c, o, "smt"); | |
340 | } | |
341 | ||
342 | return false; | |
343 | } | |
344 | ||
148f9bb8 | 345 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
346 | { |
347 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
348 | ||
349 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
350 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
351 | return topology_sane(c, o, "llc"); | |
352 | ||
353 | return false; | |
d4fbe4f0 AH |
354 | } |
355 | ||
cebf15eb DH |
356 | /* |
357 | * Unlike the other levels, we do not enforce keeping a | |
358 | * multicore group inside a NUMA node. If this happens, we will | |
359 | * discard the MC level of the topology later. | |
360 | */ | |
361 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 362 | { |
cebf15eb DH |
363 | if (c->phys_proc_id == o->phys_proc_id) |
364 | return true; | |
316ad248 PZ |
365 | return false; |
366 | } | |
1d89a7f0 | 367 | |
cebf15eb DH |
368 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
369 | #ifdef CONFIG_SCHED_SMT | |
370 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
371 | #endif | |
372 | #ifdef CONFIG_SCHED_MC | |
373 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
374 | #endif | |
375 | { NULL, }, | |
376 | }; | |
377 | /* | |
378 | * set_sched_topology() sets the topology internal to a CPU. The | |
379 | * NUMA topologies are layered on top of it to build the full | |
380 | * system topology. | |
381 | * | |
382 | * If NUMA nodes are observed to occur within a CPU package, this | |
383 | * function should be called. It forces the sched domain code to | |
384 | * only use the SMT level for the CPU portion of the topology. | |
385 | * This essentially falls back to relying on NUMA information | |
386 | * from the SRAT table to describe the entire system topology | |
387 | * (except for hyperthreads). | |
388 | */ | |
389 | static void primarily_use_numa_for_topology(void) | |
390 | { | |
391 | set_sched_topology(numa_inside_package_topology); | |
392 | } | |
393 | ||
148f9bb8 | 394 | void set_cpu_sibling_map(int cpu) |
768d9505 | 395 | { |
316ad248 | 396 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 397 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 398 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
399 | struct cpuinfo_x86 *o; |
400 | int i; | |
768d9505 | 401 | |
c2d1cec1 | 402 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 403 | |
b0bc225d | 404 | if (!has_mp) { |
c2d1cec1 | 405 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
316ad248 PZ |
406 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
407 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); | |
768d9505 GC |
408 | c->booted_cores = 1; |
409 | return; | |
410 | } | |
411 | ||
c2d1cec1 | 412 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
413 | o = &cpu_data(i); |
414 | ||
415 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
416 | link_mask(sibling, cpu, i); | |
417 | ||
b0bc225d | 418 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
316ad248 PZ |
419 | link_mask(llc_shared, cpu, i); |
420 | ||
ceb1cbac KB |
421 | } |
422 | ||
423 | /* | |
424 | * This needs a separate iteration over the cpus because we rely on all | |
425 | * cpu_sibling_mask links to be set-up. | |
426 | */ | |
427 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
428 | o = &cpu_data(i); | |
429 | ||
cebf15eb | 430 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
316ad248 PZ |
431 | link_mask(core, cpu, i); |
432 | ||
768d9505 GC |
433 | /* |
434 | * Does this new cpu bringup a new core? | |
435 | */ | |
c2d1cec1 | 436 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
437 | /* |
438 | * for each core in package, increment | |
439 | * the booted_cores for this new cpu | |
440 | */ | |
c2d1cec1 | 441 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
442 | c->booted_cores++; |
443 | /* | |
444 | * increment the core count for all | |
445 | * the other cpus in this package | |
446 | */ | |
447 | if (i != cpu) | |
448 | cpu_data(i).booted_cores++; | |
449 | } else if (i != cpu && !c->booted_cores) | |
450 | c->booted_cores = cpu_data(i).booted_cores; | |
451 | } | |
728e5653 | 452 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 453 | primarily_use_numa_for_topology(); |
768d9505 GC |
454 | } |
455 | } | |
456 | ||
70708a18 | 457 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 458 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 459 | { |
9f646389 | 460 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
461 | } |
462 | ||
a4928cff | 463 | static void impress_friends(void) |
904541e2 GOC |
464 | { |
465 | int cpu; | |
466 | unsigned long bogosum = 0; | |
467 | /* | |
468 | * Allow the user to impress friends. | |
469 | */ | |
c767a54b | 470 | pr_debug("Before bogomips\n"); |
904541e2 | 471 | for_each_possible_cpu(cpu) |
c2d1cec1 | 472 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 473 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 474 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 475 | num_online_cpus(), |
904541e2 GOC |
476 | bogosum/(500000/HZ), |
477 | (bogosum/(5000/HZ))%100); | |
478 | ||
c767a54b | 479 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
480 | } |
481 | ||
569712b2 | 482 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
483 | { |
484 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 485 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
486 | int timeout; |
487 | u32 status; | |
488 | ||
c767a54b | 489 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
490 | |
491 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 492 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
493 | |
494 | /* | |
495 | * Wait for idle. | |
496 | */ | |
497 | status = safe_apic_wait_icr_idle(); | |
498 | if (status) | |
c767a54b | 499 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 500 | |
1b374e4d | 501 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
502 | |
503 | timeout = 0; | |
504 | do { | |
505 | udelay(100); | |
506 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
507 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
508 | ||
509 | switch (status) { | |
510 | case APIC_ICR_RR_VALID: | |
511 | status = apic_read(APIC_RRR); | |
c767a54b | 512 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
513 | break; |
514 | default: | |
c767a54b | 515 | pr_cont("failed\n"); |
cb3c8b90 GOC |
516 | } |
517 | } | |
518 | } | |
519 | ||
cb3c8b90 GOC |
520 | /* |
521 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
522 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
523 | * won't ... remember to clear down the APIC, etc later. | |
524 | */ | |
148f9bb8 | 525 | int |
e1c467e6 | 526 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
527 | { |
528 | unsigned long send_status, accept_status = 0; | |
529 | int maxlvt; | |
530 | ||
531 | /* Target chip */ | |
cb3c8b90 GOC |
532 | /* Boot on the stack */ |
533 | /* Kick the second */ | |
e1c467e6 | 534 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 535 | |
cfc1b9a6 | 536 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
537 | send_status = safe_apic_wait_icr_idle(); |
538 | ||
539 | /* | |
540 | * Give the other CPU some time to accept the IPI. | |
541 | */ | |
542 | udelay(200); | |
569712b2 | 543 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
544 | maxlvt = lapic_get_maxlvt(); |
545 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
546 | apic_write(APIC_ESR, 0); | |
547 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
548 | } | |
c767a54b | 549 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
550 | |
551 | if (send_status) | |
c767a54b | 552 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 553 | if (accept_status) |
c767a54b | 554 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
555 | |
556 | return (send_status | accept_status); | |
557 | } | |
cb3c8b90 | 558 | |
148f9bb8 | 559 | static int |
569712b2 | 560 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
561 | { |
562 | unsigned long send_status, accept_status = 0; | |
563 | int maxlvt, num_starts, j; | |
564 | ||
593f4a78 MR |
565 | maxlvt = lapic_get_maxlvt(); |
566 | ||
cb3c8b90 GOC |
567 | /* |
568 | * Be paranoid about clearing APIC errors. | |
569 | */ | |
570 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
571 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
572 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
573 | apic_read(APIC_ESR); |
574 | } | |
575 | ||
c767a54b | 576 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
577 | |
578 | /* | |
579 | * Turn INIT on target chip | |
580 | */ | |
cb3c8b90 GOC |
581 | /* |
582 | * Send IPI | |
583 | */ | |
1b374e4d SS |
584 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
585 | phys_apicid); | |
cb3c8b90 | 586 | |
cfc1b9a6 | 587 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
588 | send_status = safe_apic_wait_icr_idle(); |
589 | ||
590 | mdelay(10); | |
591 | ||
c767a54b | 592 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
593 | |
594 | /* Target chip */ | |
cb3c8b90 | 595 | /* Send IPI */ |
1b374e4d | 596 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 597 | |
cfc1b9a6 | 598 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
599 | send_status = safe_apic_wait_icr_idle(); |
600 | ||
601 | mb(); | |
602 | atomic_set(&init_deasserted, 1); | |
603 | ||
604 | /* | |
605 | * Should we send STARTUP IPIs ? | |
606 | * | |
607 | * Determine this based on the APIC version. | |
608 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
609 | */ | |
610 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
611 | num_starts = 2; | |
612 | else | |
613 | num_starts = 0; | |
614 | ||
615 | /* | |
616 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
617 | * target processor state. | |
618 | */ | |
619 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 620 | stack_start); |
cb3c8b90 GOC |
621 | |
622 | /* | |
623 | * Run STARTUP IPI loop. | |
624 | */ | |
c767a54b | 625 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 626 | |
cb3c8b90 | 627 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 628 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
629 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
630 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 631 | apic_read(APIC_ESR); |
c767a54b | 632 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
633 | |
634 | /* | |
635 | * STARTUP IPI | |
636 | */ | |
637 | ||
638 | /* Target chip */ | |
cb3c8b90 GOC |
639 | /* Boot on the stack */ |
640 | /* Kick the second */ | |
1b374e4d SS |
641 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
642 | phys_apicid); | |
cb3c8b90 GOC |
643 | |
644 | /* | |
645 | * Give the other CPU some time to accept the IPI. | |
646 | */ | |
647 | udelay(300); | |
648 | ||
c767a54b | 649 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 650 | |
cfc1b9a6 | 651 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
652 | send_status = safe_apic_wait_icr_idle(); |
653 | ||
654 | /* | |
655 | * Give the other CPU some time to accept the IPI. | |
656 | */ | |
657 | udelay(200); | |
593f4a78 | 658 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 659 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
660 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
661 | if (send_status || accept_status) | |
662 | break; | |
663 | } | |
c767a54b | 664 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
665 | |
666 | if (send_status) | |
c767a54b | 667 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 668 | if (accept_status) |
c767a54b | 669 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
670 | |
671 | return (send_status | accept_status); | |
672 | } | |
cb3c8b90 | 673 | |
a17bce4d BP |
674 | void smp_announce(void) |
675 | { | |
676 | int num_nodes = num_online_nodes(); | |
677 | ||
678 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
679 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
680 | } | |
681 | ||
2eaad1fd | 682 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 683 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
684 | { |
685 | static int current_node = -1; | |
4adc8b71 | 686 | int node = early_cpu_to_node(cpu); |
a17bce4d | 687 | static int width, node_width; |
646e29a1 BP |
688 | |
689 | if (!width) | |
690 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 691 | |
a17bce4d BP |
692 | if (!node_width) |
693 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
694 | ||
695 | if (cpu == 1) | |
696 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
697 | ||
2eaad1fd MT |
698 | if (system_state == SYSTEM_BOOTING) { |
699 | if (node != current_node) { | |
700 | if (current_node > (-1)) | |
a17bce4d | 701 | pr_cont("\n"); |
2eaad1fd | 702 | current_node = node; |
a17bce4d BP |
703 | |
704 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
705 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 706 | } |
646e29a1 BP |
707 | |
708 | /* Add padding for the BSP */ | |
709 | if (cpu == 1) | |
710 | pr_cont("%*s", width + 1, " "); | |
711 | ||
712 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
713 | ||
2eaad1fd MT |
714 | } else |
715 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
716 | node, cpu, apicid); | |
717 | } | |
718 | ||
e1c467e6 FY |
719 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
720 | { | |
721 | int cpu; | |
722 | ||
723 | cpu = smp_processor_id(); | |
724 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
725 | return NMI_HANDLED; | |
726 | ||
727 | return NMI_DONE; | |
728 | } | |
729 | ||
730 | /* | |
731 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
732 | * | |
733 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
734 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
735 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
736 | * | |
737 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
738 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
739 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
740 | * real platform and request are available. | |
741 | */ | |
148f9bb8 | 742 | static int |
e1c467e6 FY |
743 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
744 | int *cpu0_nmi_registered) | |
745 | { | |
746 | int id; | |
747 | int boot_error; | |
748 | ||
ea7bdc65 JK |
749 | preempt_disable(); |
750 | ||
e1c467e6 FY |
751 | /* |
752 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
753 | */ | |
ea7bdc65 JK |
754 | if (cpu) { |
755 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
756 | goto out; | |
757 | } | |
e1c467e6 FY |
758 | |
759 | /* | |
760 | * Wake up BSP by nmi. | |
761 | * | |
762 | * Register a NMI handler to help wake up CPU0. | |
763 | */ | |
764 | boot_error = register_nmi_handler(NMI_LOCAL, | |
765 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
766 | ||
767 | if (!boot_error) { | |
768 | enable_start_cpu0 = 1; | |
769 | *cpu0_nmi_registered = 1; | |
770 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
771 | id = cpu0_logical_apicid; | |
772 | else | |
773 | id = apicid; | |
774 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
775 | } | |
ea7bdc65 JK |
776 | |
777 | out: | |
778 | preempt_enable(); | |
e1c467e6 FY |
779 | |
780 | return boot_error; | |
781 | } | |
782 | ||
cb3c8b90 GOC |
783 | /* |
784 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
785 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
786 | * Returns zero if CPU booted OK, else error code from |
787 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 788 | */ |
148f9bb8 | 789 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 790 | { |
48927bbb | 791 | volatile u32 *trampoline_status = |
b429dbf6 | 792 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 793 | /* start_ip had better be page-aligned! */ |
f37240f1 | 794 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 795 | |
cb3c8b90 | 796 | unsigned long boot_error = 0; |
e1c467e6 | 797 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 798 | unsigned long timeout; |
cb3c8b90 | 799 | |
816afe4f RR |
800 | /* Just in case we booted with a single CPU. */ |
801 | alternatives_enable_smp(); | |
cb3c8b90 | 802 | |
7eb43a6d TG |
803 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
804 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
805 | per_cpu(current_task, cpu) = idle; | |
cb3c8b90 | 806 | |
c6f5e0ac | 807 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 808 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
809 | irq_ctx_init(cpu); |
810 | #else | |
7eb43a6d | 811 | clear_tsk_thread_flag(idle, TIF_FORK); |
004aa322 | 812 | initial_gs = per_cpu_offset(cpu); |
198d208d | 813 | #endif |
9af45651 | 814 | per_cpu(kernel_stack, cpu) = |
7eb43a6d | 815 | (unsigned long)task_stack_page(idle) - |
9af45651 | 816 | KERNEL_STACK_OFFSET + THREAD_SIZE; |
a939098a | 817 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 818 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 819 | stack_start = idle->thread.sp; |
cb3c8b90 | 820 | |
2eaad1fd MT |
821 | /* So we see what's up */ |
822 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
823 | |
824 | /* | |
825 | * This grunge runs the startup process for | |
826 | * the targeted processor. | |
827 | */ | |
828 | ||
829 | atomic_set(&init_deasserted, 0); | |
830 | ||
34d05591 | 831 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 832 | |
cfc1b9a6 | 833 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 834 | |
34d05591 JS |
835 | smpboot_setup_warm_reset_vector(start_ip); |
836 | /* | |
837 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
838 | */ |
839 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
840 | apic_write(APIC_ESR, 0); | |
841 | apic_read(APIC_ESR); | |
842 | } | |
34d05591 | 843 | } |
cb3c8b90 | 844 | |
ce4b1b16 IM |
845 | /* |
846 | * AP might wait on cpu_callout_mask in cpu_init() with | |
847 | * cpu_initialized_mask set if previous attempt to online | |
848 | * it timed-out. Clear cpu_initialized_mask so that after | |
849 | * INIT/SIPI it could start with a clean state. | |
850 | */ | |
851 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
852 | smp_mb(); | |
853 | ||
cb3c8b90 | 854 | /* |
e1c467e6 FY |
855 | * Wake up a CPU in difference cases: |
856 | * - Use the method in the APIC driver if it's defined | |
857 | * Otherwise, | |
858 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 859 | */ |
1f5bcabf IM |
860 | if (apic->wakeup_secondary_cpu) |
861 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
862 | else | |
e1c467e6 FY |
863 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
864 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
865 | |
866 | if (!boot_error) { | |
867 | /* | |
ce4b1b16 | 868 | * Wait 10s total for a response from AP |
cb3c8b90 | 869 | */ |
ce4b1b16 IM |
870 | boot_error = -1; |
871 | timeout = jiffies + 10*HZ; | |
872 | while (time_before(jiffies, timeout)) { | |
873 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
874 | /* | |
875 | * Tell AP to proceed with initialization | |
876 | */ | |
877 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
878 | boot_error = 0; | |
879 | break; | |
880 | } | |
881 | udelay(100); | |
882 | schedule(); | |
883 | } | |
884 | } | |
cb3c8b90 | 885 | |
ce4b1b16 | 886 | if (!boot_error) { |
cb3c8b90 | 887 | /* |
ce4b1b16 | 888 | * Wait till AP completes initial initialization |
cb3c8b90 | 889 | */ |
ce4b1b16 | 890 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
891 | /* |
892 | * Allow other tasks to run while we wait for the | |
893 | * AP to come online. This also gives a chance | |
894 | * for the MTRR work(triggered by the AP coming online) | |
895 | * to be completed in the stop machine context. | |
896 | */ | |
ce4b1b16 | 897 | udelay(100); |
68f202e4 | 898 | schedule(); |
cb3c8b90 | 899 | } |
cb3c8b90 GOC |
900 | } |
901 | ||
902 | /* mark "stuck" area as not stuck */ | |
48927bbb | 903 | *trampoline_status = 0; |
cb3c8b90 | 904 | |
02421f98 YL |
905 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
906 | /* | |
907 | * Cleanup possible dangling ends... | |
908 | */ | |
909 | smpboot_restore_warm_reset_vector(); | |
910 | } | |
e1c467e6 FY |
911 | /* |
912 | * Clean up the nmi handler. Do this after the callin and callout sync | |
913 | * to avoid impact of possible long unregister time. | |
914 | */ | |
915 | if (cpu0_nmi_registered) | |
916 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
917 | ||
cb3c8b90 GOC |
918 | return boot_error; |
919 | } | |
920 | ||
148f9bb8 | 921 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 922 | { |
a21769a4 | 923 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
924 | unsigned long flags; |
925 | int err; | |
926 | ||
927 | WARN_ON(irqs_disabled()); | |
928 | ||
cfc1b9a6 | 929 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 930 | |
30106c17 | 931 | if (apicid == BAD_APICID || |
c284b42a | 932 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 933 | !apic->apic_id_valid(apicid)) { |
c767a54b | 934 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
935 | return -EINVAL; |
936 | } | |
937 | ||
938 | /* | |
939 | * Already booted CPU? | |
940 | */ | |
c2d1cec1 | 941 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 942 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
943 | return -ENOSYS; |
944 | } | |
945 | ||
946 | /* | |
947 | * Save current MTRR state in case it was changed since early boot | |
948 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
949 | */ | |
950 | mtrr_save_state(); | |
951 | ||
952 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
953 | ||
644c1541 VP |
954 | /* the FPU context is blank, nobody can own it */ |
955 | __cpu_disable_lazy_restore(cpu); | |
956 | ||
7eb43a6d | 957 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 958 | if (err) { |
feef1e8e | 959 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 960 | return -EIO; |
cb3c8b90 GOC |
961 | } |
962 | ||
963 | /* | |
964 | * Check TSC synchronization with the AP (keep irqs disabled | |
965 | * while doing so): | |
966 | */ | |
967 | local_irq_save(flags); | |
968 | check_tsc_sync_source(cpu); | |
969 | local_irq_restore(flags); | |
970 | ||
7c04e64a | 971 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
972 | cpu_relax(); |
973 | touch_nmi_watchdog(); | |
974 | } | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
7167d08e HK |
979 | /** |
980 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
981 | */ | |
982 | void arch_disable_smp_support(void) | |
983 | { | |
984 | disable_ioapic_support(); | |
985 | } | |
986 | ||
8aef135c GOC |
987 | /* |
988 | * Fall back to non SMP mode after errors. | |
989 | * | |
990 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
991 | */ | |
992 | static __init void disable_smp(void) | |
993 | { | |
ef4c59a4 TG |
994 | disable_ioapic_support(); |
995 | ||
4f062896 RR |
996 | init_cpu_present(cpumask_of(0)); |
997 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 998 | |
8aef135c | 999 | if (smp_found_config) |
b6df1b8b | 1000 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1001 | else |
b6df1b8b | 1002 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
1003 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
1004 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
1005 | } |
1006 | ||
1007 | /* | |
1008 | * Various sanity checks. | |
1009 | */ | |
1010 | static int __init smp_sanity_check(unsigned max_cpus) | |
1011 | { | |
ac23d4ee | 1012 | preempt_disable(); |
a58f03b0 | 1013 | |
1ff2f20d | 1014 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1015 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1016 | unsigned int cpu; | |
1017 | unsigned nr; | |
1018 | ||
c767a54b JP |
1019 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1020 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1021 | |
1022 | nr = 0; | |
1023 | for_each_present_cpu(cpu) { | |
1024 | if (nr >= 8) | |
c2d1cec1 | 1025 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1026 | nr++; |
1027 | } | |
1028 | ||
1029 | nr = 0; | |
1030 | for_each_possible_cpu(cpu) { | |
1031 | if (nr >= 8) | |
c2d1cec1 | 1032 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1033 | nr++; |
1034 | } | |
1035 | ||
1036 | nr_cpu_ids = 8; | |
1037 | } | |
1038 | #endif | |
1039 | ||
8aef135c | 1040 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1041 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1042 | hard_smp_processor_id()); |
1043 | ||
8aef135c GOC |
1044 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1045 | } | |
1046 | ||
1047 | /* | |
1048 | * If we couldn't find an SMP configuration at boot time, | |
1049 | * get out of here now! | |
1050 | */ | |
1051 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1052 | preempt_enable(); |
c767a54b | 1053 | pr_notice("SMP motherboard not detected\n"); |
8aef135c GOC |
1054 | disable_smp(); |
1055 | if (APIC_init_uniprocessor()) | |
c767a54b | 1056 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
8aef135c GOC |
1057 | return -1; |
1058 | } | |
1059 | ||
1060 | /* | |
1061 | * Should not be necessary because the MP table should list the boot | |
1062 | * CPU too, but we do it for the sake of robustness anyway. | |
1063 | */ | |
a27a6210 | 1064 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1065 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1066 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1067 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1068 | } | |
ac23d4ee | 1069 | preempt_enable(); |
8aef135c GOC |
1070 | |
1071 | /* | |
1072 | * If we couldn't find a local APIC, then get out of here now! | |
1073 | */ | |
1074 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1075 | !cpu_has_apic) { | |
103428e5 CG |
1076 | if (!disable_apic) { |
1077 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1078 | boot_cpu_physical_apicid); | |
c767a54b | 1079 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1080 | } |
7167d08e | 1081 | disable_ioapic_support(); |
8aef135c GOC |
1082 | return -1; |
1083 | } | |
1084 | ||
1085 | verify_local_APIC(); | |
1086 | ||
1087 | /* | |
1088 | * If SMP should be disabled, then really disable it! | |
1089 | */ | |
1090 | if (!max_cpus) { | |
c767a54b | 1091 | pr_info("SMP mode deactivated\n"); |
ef4c59a4 | 1092 | disable_ioapic_support(); |
d54db1ac | 1093 | |
e90955c2 | 1094 | connect_bsp_APIC(); |
e90955c2 | 1095 | setup_local_APIC(); |
2fb270f3 | 1096 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
1097 | return -1; |
1098 | } | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | static void __init smp_cpu_index_default(void) | |
1104 | { | |
1105 | int i; | |
1106 | struct cpuinfo_x86 *c; | |
1107 | ||
7c04e64a | 1108 | for_each_possible_cpu(i) { |
8aef135c GOC |
1109 | c = &cpu_data(i); |
1110 | /* mark all to hotplug */ | |
9628937d | 1111 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1112 | } |
1113 | } | |
1114 | ||
1115 | /* | |
1116 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1117 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1118 | */ | |
1119 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1120 | { | |
7ad728f9 RR |
1121 | unsigned int i; |
1122 | ||
8aef135c | 1123 | smp_cpu_index_default(); |
792363d2 | 1124 | |
8aef135c GOC |
1125 | /* |
1126 | * Setup boot CPU information | |
1127 | */ | |
30106c17 | 1128 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1129 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1130 | mb(); | |
bd22a2f1 | 1131 | |
8aef135c | 1132 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1133 | for_each_possible_cpu(i) { |
79f55997 LZ |
1134 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1135 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1136 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1137 | } |
8aef135c GOC |
1138 | set_cpu_sibling_map(0); |
1139 | ||
1140 | if (smp_sanity_check(max_cpus) < 0) { | |
c767a54b | 1141 | pr_info("SMP disabled\n"); |
8aef135c | 1142 | disable_smp(); |
250a1ac6 | 1143 | return; |
8aef135c GOC |
1144 | } |
1145 | ||
fa47f7e5 SS |
1146 | default_setup_apic_routing(); |
1147 | ||
4c9961d5 | 1148 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1149 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1150 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1151 | /* Or can we switch back to PIC here? */ |
1152 | } | |
1153 | ||
8aef135c | 1154 | connect_bsp_APIC(); |
b5841765 | 1155 | |
8aef135c GOC |
1156 | /* |
1157 | * Switch from PIC to APIC mode. | |
1158 | */ | |
1159 | setup_local_APIC(); | |
1160 | ||
e1c467e6 FY |
1161 | if (x2apic_mode) |
1162 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1163 | else | |
1164 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1165 | ||
ef4c59a4 TG |
1166 | /* Enable IO APIC before setting up error vector */ |
1167 | enable_IO_APIC(); | |
88d0f550 | 1168 | |
2fb270f3 | 1169 | bsp_end_local_APIC_setup(); |
ef4c59a4 TG |
1170 | setup_IO_APIC(); |
1171 | ||
8aef135c GOC |
1172 | /* |
1173 | * Set up local APIC timer on boot CPU. | |
1174 | */ | |
c767a54b | 1175 | pr_info("CPU%d: ", 0); |
8aef135c | 1176 | print_cpu_info(&cpu_data(0)); |
736decac | 1177 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1178 | |
1179 | if (is_uv_system()) | |
1180 | uv_system_init(); | |
d0af9eed SS |
1181 | |
1182 | set_mtrr_aps_delayed_init(); | |
8aef135c | 1183 | } |
d0af9eed SS |
1184 | |
1185 | void arch_enable_nonboot_cpus_begin(void) | |
1186 | { | |
1187 | set_mtrr_aps_delayed_init(); | |
1188 | } | |
1189 | ||
1190 | void arch_enable_nonboot_cpus_end(void) | |
1191 | { | |
1192 | mtrr_aps_init(); | |
1193 | } | |
1194 | ||
a8db8453 GOC |
1195 | /* |
1196 | * Early setup to make printk work. | |
1197 | */ | |
1198 | void __init native_smp_prepare_boot_cpu(void) | |
1199 | { | |
1200 | int me = smp_processor_id(); | |
552be871 | 1201 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1202 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1203 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1204 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1205 | } | |
1206 | ||
83f7eb9c GOC |
1207 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1208 | { | |
c767a54b | 1209 | pr_debug("Boot done\n"); |
83f7eb9c | 1210 | |
99e8b9ca | 1211 | nmi_selftest(); |
83f7eb9c | 1212 | impress_friends(); |
83f7eb9c | 1213 | setup_ioapic_dest(); |
d0af9eed | 1214 | mtrr_aps_init(); |
83f7eb9c GOC |
1215 | } |
1216 | ||
3b11ce7f MT |
1217 | static int __initdata setup_possible_cpus = -1; |
1218 | static int __init _setup_possible_cpus(char *str) | |
1219 | { | |
1220 | get_option(&str, &setup_possible_cpus); | |
1221 | return 0; | |
1222 | } | |
1223 | early_param("possible_cpus", _setup_possible_cpus); | |
1224 | ||
1225 | ||
68a1c3f8 | 1226 | /* |
4f062896 | 1227 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1228 | * are onlined, or offlined. The reason is per-cpu data-structures |
1229 | * are allocated by some modules at init time, and dont expect to | |
1230 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1231 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1232 | * In case when cpu_hotplug is not compiled, then we resort to current |
1233 | * behaviour, which is cpu_possible == cpu_present. | |
1234 | * - Ashok Raj | |
1235 | * | |
1236 | * Three ways to find out the number of additional hotplug CPUs: | |
1237 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1238 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1239 | * - Otherwise don't reserve additional CPUs. |
1240 | * We do this because additional CPUs waste a lot of memory. | |
1241 | * -AK | |
1242 | */ | |
1243 | __init void prefill_possible_map(void) | |
1244 | { | |
cb48bb59 | 1245 | int i, possible; |
68a1c3f8 | 1246 | |
329513a3 YL |
1247 | /* no processor from mptable or madt */ |
1248 | if (!num_processors) | |
1249 | num_processors = 1; | |
1250 | ||
5f2eb550 JB |
1251 | i = setup_max_cpus ?: 1; |
1252 | if (setup_possible_cpus == -1) { | |
1253 | possible = num_processors; | |
1254 | #ifdef CONFIG_HOTPLUG_CPU | |
1255 | if (setup_max_cpus) | |
1256 | possible += disabled_cpus; | |
1257 | #else | |
1258 | if (possible > i) | |
1259 | possible = i; | |
1260 | #endif | |
1261 | } else | |
3b11ce7f MT |
1262 | possible = setup_possible_cpus; |
1263 | ||
730cf272 MT |
1264 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1265 | ||
2b633e3f YL |
1266 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1267 | if (possible > nr_cpu_ids) { | |
c767a54b | 1268 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1269 | possible, nr_cpu_ids); |
1270 | possible = nr_cpu_ids; | |
3b11ce7f | 1271 | } |
68a1c3f8 | 1272 | |
5f2eb550 JB |
1273 | #ifdef CONFIG_HOTPLUG_CPU |
1274 | if (!setup_max_cpus) | |
1275 | #endif | |
1276 | if (possible > i) { | |
c767a54b | 1277 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1278 | possible, setup_max_cpus); |
1279 | possible = i; | |
1280 | } | |
1281 | ||
c767a54b | 1282 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1283 | possible, max_t(int, possible - num_processors, 0)); |
1284 | ||
1285 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1286 | set_cpu_possible(i, true); |
5f2eb550 JB |
1287 | for (; i < NR_CPUS; i++) |
1288 | set_cpu_possible(i, false); | |
3461b0af MT |
1289 | |
1290 | nr_cpu_ids = possible; | |
68a1c3f8 | 1291 | } |
69c18c15 | 1292 | |
14adf855 CE |
1293 | #ifdef CONFIG_HOTPLUG_CPU |
1294 | ||
1295 | static void remove_siblinginfo(int cpu) | |
1296 | { | |
1297 | int sibling; | |
1298 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1299 | ||
c2d1cec1 MT |
1300 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1301 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1302 | /*/ |
1303 | * last thread sibling in this cpu core going down | |
1304 | */ | |
c2d1cec1 | 1305 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1306 | cpu_data(sibling).booted_cores--; |
1307 | } | |
1308 | ||
c2d1cec1 MT |
1309 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1310 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
03bd4e1f WL |
1311 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1312 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1313 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
c2d1cec1 MT |
1314 | cpumask_clear(cpu_sibling_mask(cpu)); |
1315 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1316 | c->phys_proc_id = 0; |
1317 | c->cpu_core_id = 0; | |
c2d1cec1 | 1318 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1319 | } |
1320 | ||
69c18c15 GC |
1321 | static void __ref remove_cpu_from_maps(int cpu) |
1322 | { | |
c2d1cec1 MT |
1323 | set_cpu_online(cpu, false); |
1324 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1325 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1326 | /* was set by cpu_init() */ |
c2d1cec1 | 1327 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1328 | numa_remove_cpu(cpu); |
69c18c15 GC |
1329 | } |
1330 | ||
54279552 BO |
1331 | static DEFINE_PER_CPU(struct completion, die_complete); |
1332 | ||
8227dce7 | 1333 | void cpu_disable_common(void) |
69c18c15 GC |
1334 | { |
1335 | int cpu = smp_processor_id(); | |
69c18c15 | 1336 | |
54279552 BO |
1337 | init_completion(&per_cpu(die_complete, smp_processor_id())); |
1338 | ||
69c18c15 GC |
1339 | remove_siblinginfo(cpu); |
1340 | ||
1341 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1342 | lock_vector_lock(); |
69c18c15 | 1343 | remove_cpu_from_maps(cpu); |
d388e5fd | 1344 | unlock_vector_lock(); |
d7b381bb | 1345 | fixup_irqs(); |
8227dce7 AN |
1346 | } |
1347 | ||
1348 | int native_cpu_disable(void) | |
1349 | { | |
da6139e4 PB |
1350 | int ret; |
1351 | ||
1352 | ret = check_irq_vectors_for_cpu_disable(); | |
1353 | if (ret) | |
1354 | return ret; | |
1355 | ||
8227dce7 | 1356 | clear_local_APIC(); |
8227dce7 | 1357 | cpu_disable_common(); |
2ed53c0d | 1358 | |
69c18c15 GC |
1359 | return 0; |
1360 | } | |
1361 | ||
54279552 BO |
1362 | void cpu_die_common(unsigned int cpu) |
1363 | { | |
1364 | wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ); | |
1365 | } | |
1366 | ||
93be71b6 | 1367 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1368 | { |
1369 | /* We don't do anything here: idle task is faking death itself. */ | |
54279552 BO |
1370 | |
1371 | cpu_die_common(cpu); | |
2ed53c0d LT |
1372 | |
1373 | /* They ack this in play_dead() by setting CPU_DEAD */ | |
1374 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1375 | if (system_state == SYSTEM_RUNNING) | |
1376 | pr_info("CPU %u is now offline\n", cpu); | |
1377 | } else { | |
1378 | pr_err("CPU %u didn't die...\n", cpu); | |
69c18c15 | 1379 | } |
69c18c15 | 1380 | } |
a21f5d88 AN |
1381 | |
1382 | void play_dead_common(void) | |
1383 | { | |
1384 | idle_task_exit(); | |
1385 | reset_lazy_tlbstate(); | |
02c68a02 | 1386 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1387 | |
1388 | mb(); | |
1389 | /* Ack it */ | |
0a3aee0d | 1390 | __this_cpu_write(cpu_state, CPU_DEAD); |
2ed53c0d | 1391 | complete(&per_cpu(die_complete, smp_processor_id())); |
a21f5d88 AN |
1392 | |
1393 | /* | |
1394 | * With physical CPU hotplug, we should halt the cpu | |
1395 | */ | |
1396 | local_irq_disable(); | |
1397 | } | |
1398 | ||
e1c467e6 FY |
1399 | static bool wakeup_cpu0(void) |
1400 | { | |
1401 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1402 | return true; | |
1403 | ||
1404 | return false; | |
1405 | } | |
1406 | ||
ea530692 PA |
1407 | /* |
1408 | * We need to flush the caches before going to sleep, lest we have | |
1409 | * dirty data in our caches when we come back up. | |
1410 | */ | |
1411 | static inline void mwait_play_dead(void) | |
1412 | { | |
1413 | unsigned int eax, ebx, ecx, edx; | |
1414 | unsigned int highest_cstate = 0; | |
1415 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1416 | void *mwait_ptr; |
576cfb40 | 1417 | int i; |
ea530692 | 1418 | |
69fb3676 | 1419 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1420 | return; |
840d2830 | 1421 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1422 | return; |
7b543a53 | 1423 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1424 | return; |
1425 | ||
1426 | eax = CPUID_MWAIT_LEAF; | |
1427 | ecx = 0; | |
1428 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1429 | ||
1430 | /* | |
1431 | * eax will be 0 if EDX enumeration is not valid. | |
1432 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1433 | */ | |
1434 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1435 | eax = 0; | |
1436 | } else { | |
1437 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1438 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1439 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1440 | highest_cstate = i; | |
1441 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1442 | } | |
1443 | } | |
1444 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1445 | (highest_subcstate - 1); | |
1446 | } | |
1447 | ||
ce5f6824 PA |
1448 | /* |
1449 | * This should be a memory location in a cache line which is | |
1450 | * unlikely to be touched by other processors. The actual | |
1451 | * content is immaterial as it is not actually modified in any way. | |
1452 | */ | |
1453 | mwait_ptr = ¤t_thread_info()->flags; | |
1454 | ||
a68e5c94 PA |
1455 | wbinvd(); |
1456 | ||
ea530692 | 1457 | while (1) { |
ce5f6824 PA |
1458 | /* |
1459 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1460 | * the Xeon 7400 series. It's not clear it is actually | |
1461 | * needed, but it should be harmless in either case. | |
1462 | * The WBINVD is insufficient due to the spurious-wakeup | |
1463 | * case where we return around the loop. | |
1464 | */ | |
7d590cca | 1465 | mb(); |
ce5f6824 | 1466 | clflush(mwait_ptr); |
7d590cca | 1467 | mb(); |
ce5f6824 | 1468 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1469 | mb(); |
1470 | __mwait(eax, 0); | |
e1c467e6 FY |
1471 | /* |
1472 | * If NMI wants to wake up CPU0, start CPU0. | |
1473 | */ | |
1474 | if (wakeup_cpu0()) | |
1475 | start_cpu0(); | |
ea530692 PA |
1476 | } |
1477 | } | |
1478 | ||
1479 | static inline void hlt_play_dead(void) | |
1480 | { | |
7b543a53 | 1481 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1482 | wbinvd(); |
1483 | ||
ea530692 | 1484 | while (1) { |
ea530692 | 1485 | native_halt(); |
e1c467e6 FY |
1486 | /* |
1487 | * If NMI wants to wake up CPU0, start CPU0. | |
1488 | */ | |
1489 | if (wakeup_cpu0()) | |
1490 | start_cpu0(); | |
ea530692 PA |
1491 | } |
1492 | } | |
1493 | ||
a21f5d88 AN |
1494 | void native_play_dead(void) |
1495 | { | |
1496 | play_dead_common(); | |
86886e55 | 1497 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1498 | |
1499 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1500 | if (cpuidle_play_dead()) |
1501 | hlt_play_dead(); | |
a21f5d88 AN |
1502 | } |
1503 | ||
69c18c15 | 1504 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1505 | int native_cpu_disable(void) |
69c18c15 GC |
1506 | { |
1507 | return -ENOSYS; | |
1508 | } | |
1509 | ||
93be71b6 | 1510 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1511 | { |
1512 | /* We said "no" in __cpu_disable */ | |
1513 | BUG(); | |
1514 | } | |
a21f5d88 AN |
1515 | |
1516 | void native_play_dead(void) | |
1517 | { | |
1518 | BUG(); | |
1519 | } | |
1520 | ||
68a1c3f8 | 1521 | #endif |