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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
186f4360 | 46 | #include <linux/export.h> |
70708a18 | 47 | #include <linux/sched.h> |
105ab3d8 | 48 | #include <linux/sched/topology.h> |
ef8bd77f | 49 | #include <linux/sched/hotplug.h> |
68db0cf1 | 50 | #include <linux/sched/task_stack.h> |
69c18c15 | 51 | #include <linux/percpu.h> |
91718e8d | 52 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
53 | #include <linux/err.h> |
54 | #include <linux/nmi.h> | |
69575d38 | 55 | #include <linux/tboot.h> |
35f720c5 | 56 | #include <linux/stackprotector.h> |
5a0e3ad6 | 57 | #include <linux/gfp.h> |
1a022e3f | 58 | #include <linux/cpuidle.h> |
69c18c15 | 59 | |
8aef135c | 60 | #include <asm/acpi.h> |
cb3c8b90 | 61 | #include <asm/desc.h> |
69c18c15 GC |
62 | #include <asm/nmi.h> |
63 | #include <asm/irq.h> | |
48927bbb | 64 | #include <asm/realmode.h> |
69c18c15 GC |
65 | #include <asm/cpu.h> |
66 | #include <asm/numa.h> | |
cb3c8b90 GOC |
67 | #include <asm/pgtable.h> |
68 | #include <asm/tlbflush.h> | |
69 | #include <asm/mtrr.h> | |
ea530692 | 70 | #include <asm/mwait.h> |
7b6aa335 | 71 | #include <asm/apic.h> |
7167d08e | 72 | #include <asm/io_apic.h> |
78f7f1e5 | 73 | #include <asm/fpu/internal.h> |
569712b2 | 74 | #include <asm/setup.h> |
bdbcdd48 | 75 | #include <asm/uv/uv.h> |
cb3c8b90 | 76 | #include <linux/mc146818rtc.h> |
b81bb373 | 77 | #include <asm/i8259.h> |
48927bbb | 78 | #include <asm/realmode.h> |
646e29a1 | 79 | #include <asm/misc.h> |
9043442b | 80 | #include <asm/qspinlock.h> |
3f6a3b03 | 81 | #include <asm/spec-ctrl.h> |
48927bbb | 82 | |
a355352b GC |
83 | /* Number of siblings per CPU package */ |
84 | int smp_num_siblings = 1; | |
85 | EXPORT_SYMBOL(smp_num_siblings); | |
86 | ||
87 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 88 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 89 | |
a355352b | 90 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
93 | ||
94 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
96 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
97 | ||
0816b0f0 | 98 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 99 | |
a355352b | 100 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 101 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 102 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 103 | |
1f12e32f | 104 | /* Logical package management. We might want to allocate that dynamically */ |
1f12e32f TG |
105 | unsigned int __max_logical_packages __read_mostly; |
106 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 107 | static unsigned int logical_packages __read_mostly; |
1f12e32f | 108 | |
70b8301f | 109 | /* Maximum number of SMT threads on any online core */ |
947134d9 | 110 | int __read_mostly __max_smt_threads = 1; |
70b8301f | 111 | |
7d25127c TC |
112 | /* Flag to indicate if a complete sched domain rebuild is required */ |
113 | bool x86_topology_update; | |
114 | ||
115 | int arch_update_cpu_topology(void) | |
116 | { | |
117 | int retval = x86_topology_update; | |
118 | ||
119 | x86_topology_update = false; | |
120 | return retval; | |
121 | } | |
122 | ||
f77aa308 TG |
123 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
124 | { | |
125 | unsigned long flags; | |
126 | ||
127 | spin_lock_irqsave(&rtc_lock, flags); | |
128 | CMOS_WRITE(0xa, 0xf); | |
129 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
130 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
131 | start_eip >> 4; | |
f77aa308 TG |
132 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
133 | start_eip & 0xf; | |
f77aa308 TG |
134 | } |
135 | ||
136 | static inline void smpboot_restore_warm_reset_vector(void) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
f77aa308 TG |
140 | /* |
141 | * Paranoid: Set warm reset code and vector here back | |
142 | * to default values. | |
143 | */ | |
144 | spin_lock_irqsave(&rtc_lock, flags); | |
145 | CMOS_WRITE(0, 0xf); | |
146 | spin_unlock_irqrestore(&rtc_lock, flags); | |
147 | ||
148 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
149 | } | |
150 | ||
cb3c8b90 | 151 | /* |
30106c17 FY |
152 | * Report back to the Boot Processor during boot time or to the caller processor |
153 | * during CPU online. | |
cb3c8b90 | 154 | */ |
148f9bb8 | 155 | static void smp_callin(void) |
cb3c8b90 GOC |
156 | { |
157 | int cpuid, phys_id; | |
cb3c8b90 GOC |
158 | |
159 | /* | |
160 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
161 | * cpu_callout_mask guarantees we don't get here before |
162 | * an INIT_deassert IPI reaches our local APIC, so it is | |
163 | * now safe to touch our local APIC. | |
cb3c8b90 | 164 | */ |
e1c467e6 | 165 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
166 | |
167 | /* | |
168 | * (This works even if the APIC is not enabled.) | |
169 | */ | |
4c9961d5 | 170 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
171 | |
172 | /* | |
173 | * the boot CPU has finished the init stage and is spinning | |
174 | * on callin_map until we finish. We are free to set up this | |
175 | * CPU, first the APIC. (this is probably redundant on most | |
176 | * boards) | |
177 | */ | |
05f7e46d | 178 | apic_ap_setup(); |
cb3c8b90 | 179 | |
b565201c JS |
180 | /* |
181 | * Save our processor parameters. Note: this information | |
182 | * is needed for clock calibration. | |
183 | */ | |
184 | smp_store_cpu_info(cpuid); | |
185 | ||
76ce7cfe PT |
186 | /* |
187 | * The topology information must be up to date before | |
188 | * calibrate_delay() and notify_cpu_starting(). | |
189 | */ | |
190 | set_cpu_sibling_map(raw_smp_processor_id()); | |
191 | ||
cb3c8b90 GOC |
192 | /* |
193 | * Get our bogomips. | |
b565201c JS |
194 | * Update loops_per_jiffy in cpu_data. Previous call to |
195 | * smp_store_cpu_info() stored a value that is close but not as | |
196 | * accurate as the value just calculated. | |
cb3c8b90 | 197 | */ |
cb3c8b90 | 198 | calibrate_delay(); |
b565201c | 199 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 200 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 201 | |
5ef428c4 AK |
202 | wmb(); |
203 | ||
85257024 PZ |
204 | notify_cpu_starting(cpuid); |
205 | ||
cb3c8b90 GOC |
206 | /* |
207 | * Allow the master to continue. | |
208 | */ | |
c2d1cec1 | 209 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
210 | } |
211 | ||
e1c467e6 FY |
212 | static int cpu0_logical_apicid; |
213 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
214 | /* |
215 | * Activate a secondary processor. | |
216 | */ | |
148f9bb8 | 217 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
218 | { |
219 | /* | |
c7ad5ad2 AL |
220 | * Don't put *anything* except direct CPU state initialization |
221 | * before cpu_init(), SMP booting is too fragile that we want to | |
222 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 223 | */ |
c7ad5ad2 AL |
224 | if (boot_cpu_has(X86_FEATURE_PCID)) |
225 | __write_cr4(__read_cr4() | X86_CR4_PCIDE); | |
e1c467e6 | 226 | |
fd89a137 | 227 | #ifdef CONFIG_X86_32 |
b40827fa | 228 | /* switch away from the initial page table */ |
fd89a137 JR |
229 | load_cr3(swapper_pg_dir); |
230 | __flush_tlb_all(); | |
231 | #endif | |
55d2d0ad | 232 | load_current_idt(); |
4ba55e65 AL |
233 | cpu_init(); |
234 | x86_cpuinit.early_percpu_clock_init(); | |
235 | preempt_disable(); | |
236 | smp_callin(); | |
237 | ||
238 | enable_start_cpu0 = 0; | |
239 | ||
bbc2ff6a GOC |
240 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
241 | barrier(); | |
242 | /* | |
a1652bb8 | 243 | * Check TSC synchronization with the boot CPU: |
bbc2ff6a GOC |
244 | */ |
245 | check_tsc_sync_target(); | |
246 | ||
3f6a3b03 TG |
247 | speculative_store_bypass_ht_init(); |
248 | ||
bbc2ff6a | 249 | /* |
8ed4f3e6 TG |
250 | * Lock vector_lock, set CPU online and bring the vector |
251 | * allocator online. Online must be set with vector_lock held | |
252 | * to prevent a concurrent irq setup/teardown from seeing a | |
253 | * half valid vector space. | |
bbc2ff6a | 254 | */ |
d388e5fd | 255 | lock_vector_lock(); |
c2d1cec1 | 256 | set_cpu_online(smp_processor_id(), true); |
8ed4f3e6 | 257 | lapic_online(); |
d388e5fd | 258 | unlock_vector_lock(); |
2a442c9c | 259 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 260 | x86_platform.nmi_init(); |
bbc2ff6a | 261 | |
0cefa5b9 MS |
262 | /* enable local interrupts */ |
263 | local_irq_enable(); | |
264 | ||
35f720c5 JP |
265 | /* to prevent fake stack check failure in clock setup */ |
266 | boot_init_stack_canary(); | |
0cefa5b9 | 267 | |
736decac | 268 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
269 | |
270 | wmb(); | |
fc6d73d6 | 271 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
272 | } |
273 | ||
30bb9811 AK |
274 | /** |
275 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
276 | * | |
277 | * Returns logical package id or -1 if not found | |
278 | */ | |
279 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
280 | { | |
281 | int cpu; | |
282 | ||
283 | for_each_possible_cpu(cpu) { | |
284 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
285 | ||
286 | if (c->initialized && c->phys_proc_id == phys_pkg) | |
287 | return c->logical_proc_id; | |
288 | } | |
289 | return -1; | |
290 | } | |
291 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
292 | ||
9d85eb91 TG |
293 | /** |
294 | * topology_update_package_map - Update the physical to logical package map | |
295 | * @pkg: The physical package id as retrieved via CPUID | |
296 | * @cpu: The cpu for which this is updated | |
297 | */ | |
298 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 299 | { |
30bb9811 | 300 | int new; |
1f12e32f | 301 | |
30bb9811 AK |
302 | /* Already available somewhere? */ |
303 | new = topology_phys_to_logical_pkg(pkg); | |
304 | if (new >= 0) | |
1f12e32f TG |
305 | goto found; |
306 | ||
7b0501b1 | 307 | new = logical_packages++; |
9d85eb91 TG |
308 | if (new != pkg) { |
309 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
310 | cpu, pkg, new); | |
311 | } | |
1f12e32f | 312 | found: |
30bb9811 | 313 | cpu_data(cpu).logical_proc_id = new; |
1f12e32f TG |
314 | return 0; |
315 | } | |
316 | ||
30106c17 FY |
317 | void __init smp_store_boot_cpu_info(void) |
318 | { | |
319 | int id = 0; /* CPU 0 */ | |
320 | struct cpuinfo_x86 *c = &cpu_data(id); | |
321 | ||
322 | *c = boot_cpu_data; | |
323 | c->cpu_index = id; | |
b4c0a732 | 324 | topology_update_package_map(c->phys_proc_id, id); |
30bb9811 | 325 | c->initialized = true; |
30106c17 FY |
326 | } |
327 | ||
1d89a7f0 GOC |
328 | /* |
329 | * The bootstrap kernel entry code has set these up. Save them for | |
330 | * a given CPU | |
331 | */ | |
148f9bb8 | 332 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
333 | { |
334 | struct cpuinfo_x86 *c = &cpu_data(id); | |
335 | ||
30bb9811 AK |
336 | /* Copy boot_cpu_data only on the first bringup */ |
337 | if (!c->initialized) | |
338 | *c = boot_cpu_data; | |
1d89a7f0 | 339 | c->cpu_index = id; |
30106c17 FY |
340 | /* |
341 | * During boot time, CPU0 has this setup already. Save the info when | |
342 | * bringing up AP or offlined CPU0. | |
343 | */ | |
344 | identify_secondary_cpu(c); | |
30bb9811 | 345 | c->initialized = true; |
1d89a7f0 GOC |
346 | } |
347 | ||
cebf15eb DH |
348 | static bool |
349 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
350 | { | |
351 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
352 | ||
353 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
354 | } | |
355 | ||
148f9bb8 | 356 | static bool |
316ad248 | 357 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 358 | { |
316ad248 PZ |
359 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
360 | ||
cebf15eb | 361 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
362 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
363 | "[node: %d != %d]. Ignoring dependency.\n", | |
364 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
365 | } | |
366 | ||
7d79a7bd | 367 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 368 | do { \ |
7d79a7bd BG |
369 | cpumask_set_cpu((c1), mfunc(c2)); \ |
370 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
371 | } while (0) |
372 | ||
148f9bb8 | 373 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 374 | { |
362f924b | 375 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
376 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
377 | ||
378 | if (c->phys_proc_id == o->phys_proc_id && | |
79a8b9aa BP |
379 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
380 | if (c->cpu_core_id == o->cpu_core_id) | |
381 | return topology_sane(c, o, "smt"); | |
382 | ||
383 | if ((c->cu_id != 0xff) && | |
384 | (o->cu_id != 0xff) && | |
385 | (c->cu_id == o->cu_id)) | |
386 | return topology_sane(c, o, "smt"); | |
387 | } | |
316ad248 PZ |
388 | |
389 | } else if (c->phys_proc_id == o->phys_proc_id && | |
390 | c->cpu_core_id == o->cpu_core_id) { | |
391 | return topology_sane(c, o, "smt"); | |
392 | } | |
393 | ||
394 | return false; | |
395 | } | |
396 | ||
148f9bb8 | 397 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
398 | { |
399 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
400 | ||
401 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
402 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
403 | return topology_sane(c, o, "llc"); | |
404 | ||
405 | return false; | |
d4fbe4f0 AH |
406 | } |
407 | ||
cebf15eb DH |
408 | /* |
409 | * Unlike the other levels, we do not enforce keeping a | |
410 | * multicore group inside a NUMA node. If this happens, we will | |
411 | * discard the MC level of the topology later. | |
412 | */ | |
413 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 414 | { |
cebf15eb DH |
415 | if (c->phys_proc_id == o->phys_proc_id) |
416 | return true; | |
316ad248 PZ |
417 | return false; |
418 | } | |
1d89a7f0 | 419 | |
d3d37d85 TC |
420 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
421 | static inline int x86_sched_itmt_flags(void) | |
422 | { | |
423 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
424 | } | |
425 | ||
426 | #ifdef CONFIG_SCHED_MC | |
427 | static int x86_core_flags(void) | |
428 | { | |
429 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
430 | } | |
431 | #endif | |
432 | #ifdef CONFIG_SCHED_SMT | |
433 | static int x86_smt_flags(void) | |
434 | { | |
435 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
436 | } | |
437 | #endif | |
438 | #endif | |
439 | ||
8f37961c | 440 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 441 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 442 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
443 | #endif |
444 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 445 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
446 | #endif |
447 | { NULL, }, | |
448 | }; | |
8f37961c TC |
449 | |
450 | static struct sched_domain_topology_level x86_topology[] = { | |
451 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 452 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
453 | #endif |
454 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 455 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
456 | #endif |
457 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
458 | { NULL, }, | |
459 | }; | |
460 | ||
cebf15eb | 461 | /* |
8f37961c TC |
462 | * Set if a package/die has multiple NUMA nodes inside. |
463 | * AMD Magny-Cours and Intel Cluster-on-Die have this. | |
cebf15eb | 464 | */ |
8f37961c | 465 | static bool x86_has_numa_in_package; |
cebf15eb | 466 | |
148f9bb8 | 467 | void set_cpu_sibling_map(int cpu) |
768d9505 | 468 | { |
316ad248 | 469 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 470 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 471 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 472 | struct cpuinfo_x86 *o; |
70b8301f | 473 | int i, threads; |
768d9505 | 474 | |
c2d1cec1 | 475 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 476 | |
b0bc225d | 477 | if (!has_mp) { |
7d79a7bd | 478 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 479 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 480 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
481 | c->booted_cores = 1; |
482 | return; | |
483 | } | |
484 | ||
c2d1cec1 | 485 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
486 | o = &cpu_data(i); |
487 | ||
488 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 489 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 490 | |
b0bc225d | 491 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 492 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 493 | |
ceb1cbac KB |
494 | } |
495 | ||
496 | /* | |
497 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 498 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
499 | */ |
500 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
501 | o = &cpu_data(i); | |
502 | ||
cebf15eb | 503 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 504 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 505 | |
768d9505 GC |
506 | /* |
507 | * Does this new cpu bringup a new core? | |
508 | */ | |
7d79a7bd BG |
509 | if (cpumask_weight( |
510 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
511 | /* |
512 | * for each core in package, increment | |
513 | * the booted_cores for this new cpu | |
514 | */ | |
7d79a7bd BG |
515 | if (cpumask_first( |
516 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
517 | c->booted_cores++; |
518 | /* | |
519 | * increment the core count for all | |
520 | * the other cpus in this package | |
521 | */ | |
522 | if (i != cpu) | |
523 | cpu_data(i).booted_cores++; | |
524 | } else if (i != cpu && !c->booted_cores) | |
525 | c->booted_cores = cpu_data(i).booted_cores; | |
526 | } | |
728e5653 | 527 | if (match_die(c, o) && !topology_same_node(c, o)) |
8f37961c | 528 | x86_has_numa_in_package = true; |
768d9505 | 529 | } |
70b8301f AK |
530 | |
531 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
532 | if (threads > __max_smt_threads) | |
533 | __max_smt_threads = threads; | |
768d9505 GC |
534 | } |
535 | ||
70708a18 | 536 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 537 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 538 | { |
9f646389 | 539 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
540 | } |
541 | ||
a4928cff | 542 | static void impress_friends(void) |
904541e2 GOC |
543 | { |
544 | int cpu; | |
545 | unsigned long bogosum = 0; | |
546 | /* | |
547 | * Allow the user to impress friends. | |
548 | */ | |
c767a54b | 549 | pr_debug("Before bogomips\n"); |
904541e2 | 550 | for_each_possible_cpu(cpu) |
c2d1cec1 | 551 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 552 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 553 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 554 | num_online_cpus(), |
904541e2 GOC |
555 | bogosum/(500000/HZ), |
556 | (bogosum/(5000/HZ))%100); | |
557 | ||
c767a54b | 558 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
559 | } |
560 | ||
569712b2 | 561 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
562 | { |
563 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 564 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
565 | int timeout; |
566 | u32 status; | |
567 | ||
c767a54b | 568 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
569 | |
570 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 571 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
572 | |
573 | /* | |
574 | * Wait for idle. | |
575 | */ | |
576 | status = safe_apic_wait_icr_idle(); | |
577 | if (status) | |
c767a54b | 578 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 579 | |
1b374e4d | 580 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
581 | |
582 | timeout = 0; | |
583 | do { | |
584 | udelay(100); | |
585 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
586 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
587 | ||
588 | switch (status) { | |
589 | case APIC_ICR_RR_VALID: | |
590 | status = apic_read(APIC_RRR); | |
c767a54b | 591 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
592 | break; |
593 | default: | |
c767a54b | 594 | pr_cont("failed\n"); |
cb3c8b90 GOC |
595 | } |
596 | } | |
597 | } | |
598 | ||
d68921f9 LB |
599 | /* |
600 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
601 | * that there should be a 10ms delay between the BSP asserting INIT | |
602 | * and de-asserting INIT, when starting a remote processor. | |
603 | * But that slows boot and resume on modern processors, which include | |
604 | * many cores and don't require that delay. | |
605 | * | |
606 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 607 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
608 | */ |
609 | #define UDELAY_10MS_DEFAULT 10000 | |
610 | ||
656279a1 | 611 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
612 | |
613 | static int __init cpu_init_udelay(char *str) | |
614 | { | |
615 | get_option(&str, &init_udelay); | |
616 | ||
617 | return 0; | |
618 | } | |
619 | early_param("cpu_init_udelay", cpu_init_udelay); | |
620 | ||
1a744cb3 LB |
621 | static void __init smp_quirk_init_udelay(void) |
622 | { | |
623 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 624 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
625 | return; |
626 | ||
627 | /* if modern processor, use no delay */ | |
628 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 629 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 630 | init_udelay = 0; |
656279a1 LB |
631 | return; |
632 | } | |
f1ccd249 LB |
633 | /* else, use legacy delay */ |
634 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
635 | } |
636 | ||
cb3c8b90 GOC |
637 | /* |
638 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
639 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
640 | * won't ... remember to clear down the APIC, etc later. | |
641 | */ | |
148f9bb8 | 642 | int |
e1c467e6 | 643 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
644 | { |
645 | unsigned long send_status, accept_status = 0; | |
646 | int maxlvt; | |
647 | ||
648 | /* Target chip */ | |
cb3c8b90 GOC |
649 | /* Boot on the stack */ |
650 | /* Kick the second */ | |
e1c467e6 | 651 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 652 | |
cfc1b9a6 | 653 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
654 | send_status = safe_apic_wait_icr_idle(); |
655 | ||
656 | /* | |
657 | * Give the other CPU some time to accept the IPI. | |
658 | */ | |
659 | udelay(200); | |
cff9ab2b | 660 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
661 | maxlvt = lapic_get_maxlvt(); |
662 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
663 | apic_write(APIC_ESR, 0); | |
664 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
665 | } | |
c767a54b | 666 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
667 | |
668 | if (send_status) | |
c767a54b | 669 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 670 | if (accept_status) |
c767a54b | 671 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
672 | |
673 | return (send_status | accept_status); | |
674 | } | |
cb3c8b90 | 675 | |
148f9bb8 | 676 | static int |
569712b2 | 677 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 678 | { |
f5d6a52f | 679 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
680 | int maxlvt, num_starts, j; |
681 | ||
593f4a78 MR |
682 | maxlvt = lapic_get_maxlvt(); |
683 | ||
cb3c8b90 GOC |
684 | /* |
685 | * Be paranoid about clearing APIC errors. | |
686 | */ | |
cff9ab2b | 687 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
688 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
689 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
690 | apic_read(APIC_ESR); |
691 | } | |
692 | ||
c767a54b | 693 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
694 | |
695 | /* | |
696 | * Turn INIT on target chip | |
697 | */ | |
cb3c8b90 GOC |
698 | /* |
699 | * Send IPI | |
700 | */ | |
1b374e4d SS |
701 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
702 | phys_apicid); | |
cb3c8b90 | 703 | |
cfc1b9a6 | 704 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
705 | send_status = safe_apic_wait_icr_idle(); |
706 | ||
7cb68598 | 707 | udelay(init_udelay); |
cb3c8b90 | 708 | |
c767a54b | 709 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
710 | |
711 | /* Target chip */ | |
cb3c8b90 | 712 | /* Send IPI */ |
1b374e4d | 713 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 714 | |
cfc1b9a6 | 715 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
716 | send_status = safe_apic_wait_icr_idle(); |
717 | ||
718 | mb(); | |
cb3c8b90 GOC |
719 | |
720 | /* | |
721 | * Should we send STARTUP IPIs ? | |
722 | * | |
723 | * Determine this based on the APIC version. | |
724 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
725 | */ | |
cff9ab2b | 726 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
727 | num_starts = 2; |
728 | else | |
729 | num_starts = 0; | |
730 | ||
cb3c8b90 GOC |
731 | /* |
732 | * Run STARTUP IPI loop. | |
733 | */ | |
c767a54b | 734 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 735 | |
cb3c8b90 | 736 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 737 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
738 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
739 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 740 | apic_read(APIC_ESR); |
c767a54b | 741 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
742 | |
743 | /* | |
744 | * STARTUP IPI | |
745 | */ | |
746 | ||
747 | /* Target chip */ | |
cb3c8b90 GOC |
748 | /* Boot on the stack */ |
749 | /* Kick the second */ | |
1b374e4d SS |
750 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
751 | phys_apicid); | |
cb3c8b90 GOC |
752 | |
753 | /* | |
754 | * Give the other CPU some time to accept the IPI. | |
755 | */ | |
fcafddec LB |
756 | if (init_udelay == 0) |
757 | udelay(10); | |
758 | else | |
a9bcaa02 | 759 | udelay(300); |
cb3c8b90 | 760 | |
c767a54b | 761 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 762 | |
cfc1b9a6 | 763 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
764 | send_status = safe_apic_wait_icr_idle(); |
765 | ||
766 | /* | |
767 | * Give the other CPU some time to accept the IPI. | |
768 | */ | |
fcafddec LB |
769 | if (init_udelay == 0) |
770 | udelay(10); | |
771 | else | |
a9bcaa02 | 772 | udelay(200); |
cb3c8b90 | 773 | |
593f4a78 | 774 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 775 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
776 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
777 | if (send_status || accept_status) | |
778 | break; | |
779 | } | |
c767a54b | 780 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
781 | |
782 | if (send_status) | |
c767a54b | 783 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 784 | if (accept_status) |
c767a54b | 785 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
786 | |
787 | return (send_status | accept_status); | |
788 | } | |
cb3c8b90 | 789 | |
2eaad1fd | 790 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 791 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
792 | { |
793 | static int current_node = -1; | |
4adc8b71 | 794 | int node = early_cpu_to_node(cpu); |
a17bce4d | 795 | static int width, node_width; |
646e29a1 BP |
796 | |
797 | if (!width) | |
798 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 799 | |
a17bce4d BP |
800 | if (!node_width) |
801 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
802 | ||
803 | if (cpu == 1) | |
804 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
805 | ||
719b3680 | 806 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
807 | if (node != current_node) { |
808 | if (current_node > (-1)) | |
a17bce4d | 809 | pr_cont("\n"); |
2eaad1fd | 810 | current_node = node; |
a17bce4d BP |
811 | |
812 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
813 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 814 | } |
646e29a1 BP |
815 | |
816 | /* Add padding for the BSP */ | |
817 | if (cpu == 1) | |
818 | pr_cont("%*s", width + 1, " "); | |
819 | ||
820 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
821 | ||
2eaad1fd MT |
822 | } else |
823 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
824 | node, cpu, apicid); | |
825 | } | |
826 | ||
e1c467e6 FY |
827 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
828 | { | |
829 | int cpu; | |
830 | ||
831 | cpu = smp_processor_id(); | |
832 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
833 | return NMI_HANDLED; | |
834 | ||
835 | return NMI_DONE; | |
836 | } | |
837 | ||
838 | /* | |
839 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
840 | * | |
841 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
842 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
843 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
844 | * | |
845 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
846 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
847 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
848 | * real platform and request are available. | |
849 | */ | |
148f9bb8 | 850 | static int |
e1c467e6 FY |
851 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
852 | int *cpu0_nmi_registered) | |
853 | { | |
854 | int id; | |
855 | int boot_error; | |
856 | ||
ea7bdc65 JK |
857 | preempt_disable(); |
858 | ||
e1c467e6 FY |
859 | /* |
860 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
861 | */ | |
ea7bdc65 JK |
862 | if (cpu) { |
863 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
864 | goto out; | |
865 | } | |
e1c467e6 FY |
866 | |
867 | /* | |
868 | * Wake up BSP by nmi. | |
869 | * | |
870 | * Register a NMI handler to help wake up CPU0. | |
871 | */ | |
872 | boot_error = register_nmi_handler(NMI_LOCAL, | |
873 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
874 | ||
875 | if (!boot_error) { | |
876 | enable_start_cpu0 = 1; | |
877 | *cpu0_nmi_registered = 1; | |
878 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
879 | id = cpu0_logical_apicid; | |
880 | else | |
881 | id = apicid; | |
882 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
883 | } | |
ea7bdc65 JK |
884 | |
885 | out: | |
886 | preempt_enable(); | |
e1c467e6 FY |
887 | |
888 | return boot_error; | |
889 | } | |
890 | ||
3f85483b BO |
891 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
892 | { | |
893 | /* Just in case we booted with a single CPU. */ | |
894 | alternatives_enable_smp(); | |
895 | ||
896 | per_cpu(current_task, cpu) = idle; | |
897 | ||
898 | #ifdef CONFIG_X86_32 | |
899 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
900 | irq_ctx_init(cpu); | |
cd493a6d | 901 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 902 | #else |
3f85483b BO |
903 | initial_gs = per_cpu_offset(cpu); |
904 | #endif | |
3f85483b BO |
905 | } |
906 | ||
cb3c8b90 GOC |
907 | /* |
908 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
909 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
910 | * Returns zero if CPU booted OK, else error code from |
911 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 912 | */ |
10e66760 VK |
913 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
914 | int *cpu0_nmi_registered) | |
cb3c8b90 | 915 | { |
48927bbb | 916 | volatile u32 *trampoline_status = |
b429dbf6 | 917 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 918 | /* start_ip had better be page-aligned! */ |
f37240f1 | 919 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 920 | |
cb3c8b90 | 921 | unsigned long boot_error = 0; |
ce4b1b16 | 922 | unsigned long timeout; |
cb3c8b90 | 923 | |
b9b1a9c3 | 924 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 925 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 926 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 927 | initial_stack = idle->thread.sp; |
cb3c8b90 | 928 | |
613e396b | 929 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 930 | init_espfix_ap(cpu); |
20d5e4a9 | 931 | |
2eaad1fd MT |
932 | /* So we see what's up */ |
933 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
934 | |
935 | /* | |
936 | * This grunge runs the startup process for | |
937 | * the targeted processor. | |
938 | */ | |
939 | ||
34d05591 | 940 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 941 | |
cfc1b9a6 | 942 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 943 | |
34d05591 JS |
944 | smpboot_setup_warm_reset_vector(start_ip); |
945 | /* | |
946 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 947 | */ |
cff9ab2b | 948 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
949 | apic_write(APIC_ESR, 0); |
950 | apic_read(APIC_ESR); | |
951 | } | |
34d05591 | 952 | } |
cb3c8b90 | 953 | |
ce4b1b16 IM |
954 | /* |
955 | * AP might wait on cpu_callout_mask in cpu_init() with | |
956 | * cpu_initialized_mask set if previous attempt to online | |
957 | * it timed-out. Clear cpu_initialized_mask so that after | |
958 | * INIT/SIPI it could start with a clean state. | |
959 | */ | |
960 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
961 | smp_mb(); | |
962 | ||
cb3c8b90 | 963 | /* |
e1c467e6 FY |
964 | * Wake up a CPU in difference cases: |
965 | * - Use the method in the APIC driver if it's defined | |
966 | * Otherwise, | |
967 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 968 | */ |
1f5bcabf IM |
969 | if (apic->wakeup_secondary_cpu) |
970 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
971 | else | |
e1c467e6 | 972 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 973 | cpu0_nmi_registered); |
cb3c8b90 GOC |
974 | |
975 | if (!boot_error) { | |
976 | /* | |
6e38f1e7 | 977 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 978 | */ |
ce4b1b16 IM |
979 | boot_error = -1; |
980 | timeout = jiffies + 10*HZ; | |
981 | while (time_before(jiffies, timeout)) { | |
982 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
983 | /* | |
984 | * Tell AP to proceed with initialization | |
985 | */ | |
986 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
987 | boot_error = 0; | |
988 | break; | |
989 | } | |
ce4b1b16 IM |
990 | schedule(); |
991 | } | |
992 | } | |
cb3c8b90 | 993 | |
ce4b1b16 | 994 | if (!boot_error) { |
cb3c8b90 | 995 | /* |
ce4b1b16 | 996 | * Wait till AP completes initial initialization |
cb3c8b90 | 997 | */ |
ce4b1b16 | 998 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
999 | /* |
1000 | * Allow other tasks to run while we wait for the | |
1001 | * AP to come online. This also gives a chance | |
1002 | * for the MTRR work(triggered by the AP coming online) | |
1003 | * to be completed in the stop machine context. | |
1004 | */ | |
1005 | schedule(); | |
cb3c8b90 | 1006 | } |
cb3c8b90 GOC |
1007 | } |
1008 | ||
1009 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1010 | *trampoline_status = 0; |
cb3c8b90 | 1011 | |
02421f98 YL |
1012 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1013 | /* | |
1014 | * Cleanup possible dangling ends... | |
1015 | */ | |
1016 | smpboot_restore_warm_reset_vector(); | |
1017 | } | |
e1c467e6 | 1018 | |
cb3c8b90 GOC |
1019 | return boot_error; |
1020 | } | |
1021 | ||
148f9bb8 | 1022 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1023 | { |
a21769a4 | 1024 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1025 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1026 | unsigned long flags; |
10e66760 | 1027 | int err, ret = 0; |
cb3c8b90 | 1028 | |
7a10e2a9 | 1029 | lockdep_assert_irqs_enabled(); |
cb3c8b90 | 1030 | |
cfc1b9a6 | 1031 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1032 | |
30106c17 | 1033 | if (apicid == BAD_APICID || |
c284b42a | 1034 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1035 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1036 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1037 | return -EINVAL; |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * Already booted CPU? | |
1042 | */ | |
c2d1cec1 | 1043 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1044 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1045 | return -ENOSYS; |
1046 | } | |
1047 | ||
1048 | /* | |
1049 | * Save current MTRR state in case it was changed since early boot | |
1050 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1051 | */ | |
1052 | mtrr_save_state(); | |
1053 | ||
2a442c9c PM |
1054 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1055 | err = cpu_check_up_prepare(cpu); | |
1056 | if (err && err != -EBUSY) | |
1057 | return err; | |
cb3c8b90 | 1058 | |
644c1541 | 1059 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1060 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1061 | |
3f85483b BO |
1062 | common_cpu_up(cpu, tidle); |
1063 | ||
10e66760 | 1064 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1065 | if (err) { |
feef1e8e | 1066 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1067 | ret = -EIO; |
1068 | goto unreg_nmi; | |
cb3c8b90 GOC |
1069 | } |
1070 | ||
1071 | /* | |
1072 | * Check TSC synchronization with the AP (keep irqs disabled | |
1073 | * while doing so): | |
1074 | */ | |
1075 | local_irq_save(flags); | |
1076 | check_tsc_sync_source(cpu); | |
1077 | local_irq_restore(flags); | |
1078 | ||
7c04e64a | 1079 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1080 | cpu_relax(); |
1081 | touch_nmi_watchdog(); | |
1082 | } | |
1083 | ||
10e66760 VK |
1084 | unreg_nmi: |
1085 | /* | |
1086 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1087 | * to avoid impact of possible long unregister time. | |
1088 | */ | |
1089 | if (cpu0_nmi_registered) | |
1090 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1091 | ||
1092 | return ret; | |
cb3c8b90 GOC |
1093 | } |
1094 | ||
7167d08e HK |
1095 | /** |
1096 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1097 | */ | |
1098 | void arch_disable_smp_support(void) | |
1099 | { | |
1100 | disable_ioapic_support(); | |
1101 | } | |
1102 | ||
8aef135c GOC |
1103 | /* |
1104 | * Fall back to non SMP mode after errors. | |
1105 | * | |
1106 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1107 | */ | |
1108 | static __init void disable_smp(void) | |
1109 | { | |
613c25ef TG |
1110 | pr_info("SMP disabled\n"); |
1111 | ||
ef4c59a4 TG |
1112 | disable_ioapic_support(); |
1113 | ||
4f062896 RR |
1114 | init_cpu_present(cpumask_of(0)); |
1115 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1116 | |
8aef135c | 1117 | if (smp_found_config) |
b6df1b8b | 1118 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1119 | else |
b6df1b8b | 1120 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1121 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1122 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1123 | } |
1124 | ||
1125 | /* | |
1126 | * Various sanity checks. | |
1127 | */ | |
4f45ed9f | 1128 | static void __init smp_sanity_check(void) |
8aef135c | 1129 | { |
ac23d4ee | 1130 | preempt_disable(); |
a58f03b0 | 1131 | |
1ff2f20d | 1132 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1133 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1134 | unsigned int cpu; | |
1135 | unsigned nr; | |
1136 | ||
c767a54b JP |
1137 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1138 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1139 | |
1140 | nr = 0; | |
1141 | for_each_present_cpu(cpu) { | |
1142 | if (nr >= 8) | |
c2d1cec1 | 1143 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1144 | nr++; |
1145 | } | |
1146 | ||
1147 | nr = 0; | |
1148 | for_each_possible_cpu(cpu) { | |
1149 | if (nr >= 8) | |
c2d1cec1 | 1150 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1151 | nr++; |
1152 | } | |
1153 | ||
1154 | nr_cpu_ids = 8; | |
1155 | } | |
1156 | #endif | |
1157 | ||
8aef135c | 1158 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1159 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1160 | hard_smp_processor_id()); |
1161 | ||
8aef135c GOC |
1162 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1163 | } | |
1164 | ||
8aef135c GOC |
1165 | /* |
1166 | * Should not be necessary because the MP table should list the boot | |
1167 | * CPU too, but we do it for the sake of robustness anyway. | |
1168 | */ | |
a27a6210 | 1169 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1170 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1171 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1172 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1173 | } | |
ac23d4ee | 1174 | preempt_enable(); |
8aef135c GOC |
1175 | } |
1176 | ||
1177 | static void __init smp_cpu_index_default(void) | |
1178 | { | |
1179 | int i; | |
1180 | struct cpuinfo_x86 *c; | |
1181 | ||
7c04e64a | 1182 | for_each_possible_cpu(i) { |
8aef135c GOC |
1183 | c = &cpu_data(i); |
1184 | /* mark all to hotplug */ | |
9628937d | 1185 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1186 | } |
1187 | } | |
1188 | ||
4b1244b4 DL |
1189 | static void __init smp_get_logical_apicid(void) |
1190 | { | |
1191 | if (x2apic_mode) | |
1192 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1193 | else | |
1194 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1195 | } | |
1196 | ||
8aef135c | 1197 | /* |
935356ce DL |
1198 | * Prepare for SMP bootup. |
1199 | * @max_cpus: configured maximum number of CPUs, It is a legacy parameter | |
1200 | * for common interface support. | |
8aef135c GOC |
1201 | */ |
1202 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1203 | { | |
7ad728f9 RR |
1204 | unsigned int i; |
1205 | ||
8aef135c | 1206 | smp_cpu_index_default(); |
792363d2 | 1207 | |
8aef135c GOC |
1208 | /* |
1209 | * Setup boot CPU information | |
1210 | */ | |
30106c17 | 1211 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1212 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1213 | mb(); | |
bd22a2f1 | 1214 | |
7ad728f9 | 1215 | for_each_possible_cpu(i) { |
79f55997 LZ |
1216 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1217 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1218 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1219 | } |
8f37961c TC |
1220 | |
1221 | /* | |
1222 | * Set 'default' x86 topology, this matches default_topology() in that | |
1223 | * it has NUMA nodes as a topology level. See also | |
1224 | * native_smp_cpus_done(). | |
1225 | * | |
1226 | * Must be done before set_cpus_sibling_map() is ran. | |
1227 | */ | |
1228 | set_sched_topology(x86_topology); | |
1229 | ||
8aef135c GOC |
1230 | set_cpu_sibling_map(0); |
1231 | ||
4f45ed9f DL |
1232 | smp_sanity_check(); |
1233 | ||
1234 | switch (apic_intr_mode) { | |
1235 | case APIC_PIC: | |
1236 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
613c25ef TG |
1237 | disable_smp(); |
1238 | return; | |
4f45ed9f | 1239 | case APIC_SYMMETRIC_IO_NO_ROUTING: |
613c25ef | 1240 | disable_smp(); |
a2510d15 DL |
1241 | /* Setup local timer */ |
1242 | x86_init.timers.setup_percpu_clockev(); | |
250a1ac6 | 1243 | return; |
4f45ed9f DL |
1244 | case APIC_VIRTUAL_WIRE: |
1245 | case APIC_SYMMETRIC_IO: | |
613c25ef | 1246 | break; |
8aef135c GOC |
1247 | } |
1248 | ||
a2510d15 DL |
1249 | /* Setup local timer */ |
1250 | x86_init.timers.setup_percpu_clockev(); | |
8aef135c | 1251 | |
4b1244b4 | 1252 | smp_get_logical_apicid(); |
ef4c59a4 | 1253 | |
d54ff31d | 1254 | pr_info("CPU0: "); |
8aef135c | 1255 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1256 | |
ca5d376e DL |
1257 | native_pv_lock_init(); |
1258 | ||
9ec808a0 | 1259 | uv_system_init(); |
d0af9eed SS |
1260 | |
1261 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1262 | |
1263 | smp_quirk_init_udelay(); | |
3f6a3b03 TG |
1264 | |
1265 | speculative_store_bypass_ht_init(); | |
8aef135c | 1266 | } |
d0af9eed SS |
1267 | |
1268 | void arch_enable_nonboot_cpus_begin(void) | |
1269 | { | |
1270 | set_mtrr_aps_delayed_init(); | |
1271 | } | |
1272 | ||
1273 | void arch_enable_nonboot_cpus_end(void) | |
1274 | { | |
1275 | mtrr_aps_init(); | |
1276 | } | |
1277 | ||
a8db8453 GOC |
1278 | /* |
1279 | * Early setup to make printk work. | |
1280 | */ | |
1281 | void __init native_smp_prepare_boot_cpu(void) | |
1282 | { | |
1283 | int me = smp_processor_id(); | |
552be871 | 1284 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1285 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1286 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1287 | cpu_set_state_online(me); |
a8db8453 GOC |
1288 | } |
1289 | ||
c6b99a00 | 1290 | void __init calculate_max_logical_packages(void) |
83f7eb9c | 1291 | { |
b4c0a732 PB |
1292 | int ncpus; |
1293 | ||
b4c0a732 PB |
1294 | /* |
1295 | * Today neither Intel nor AMD support heterogenous systems so | |
1296 | * extrapolate the boot cpu's data to all packages. | |
1297 | */ | |
947134d9 | 1298 | ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); |
b4c0a732 PB |
1299 | __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); |
1300 | pr_info("Max logical packages: %u\n", __max_logical_packages); | |
c6b99a00 PB |
1301 | } |
1302 | ||
1303 | void __init native_smp_cpus_done(unsigned int max_cpus) | |
1304 | { | |
1305 | pr_debug("Boot done\n"); | |
1306 | ||
1307 | calculate_max_logical_packages(); | |
83f7eb9c | 1308 | |
8f37961c TC |
1309 | if (x86_has_numa_in_package) |
1310 | set_sched_topology(x86_numa_in_package_topology); | |
1311 | ||
99e8b9ca | 1312 | nmi_selftest(); |
83f7eb9c | 1313 | impress_friends(); |
d0af9eed | 1314 | mtrr_aps_init(); |
83f7eb9c GOC |
1315 | } |
1316 | ||
3b11ce7f MT |
1317 | static int __initdata setup_possible_cpus = -1; |
1318 | static int __init _setup_possible_cpus(char *str) | |
1319 | { | |
1320 | get_option(&str, &setup_possible_cpus); | |
1321 | return 0; | |
1322 | } | |
1323 | early_param("possible_cpus", _setup_possible_cpus); | |
1324 | ||
1325 | ||
68a1c3f8 | 1326 | /* |
4f062896 | 1327 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1328 | * are onlined, or offlined. The reason is per-cpu data-structures |
1329 | * are allocated by some modules at init time, and dont expect to | |
1330 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1331 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1332 | * In case when cpu_hotplug is not compiled, then we resort to current |
1333 | * behaviour, which is cpu_possible == cpu_present. | |
1334 | * - Ashok Raj | |
1335 | * | |
1336 | * Three ways to find out the number of additional hotplug CPUs: | |
1337 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1338 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1339 | * - Otherwise don't reserve additional CPUs. |
1340 | * We do this because additional CPUs waste a lot of memory. | |
1341 | * -AK | |
1342 | */ | |
1343 | __init void prefill_possible_map(void) | |
1344 | { | |
cb48bb59 | 1345 | int i, possible; |
68a1c3f8 | 1346 | |
2a51fe08 PB |
1347 | /* No boot processor was found in mptable or ACPI MADT */ |
1348 | if (!num_processors) { | |
ff856051 VS |
1349 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1350 | int apicid = boot_cpu_physical_apicid; | |
1351 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1352 | |
ff856051 | 1353 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1354 | |
ff856051 VS |
1355 | /* Make sure boot cpu is enumerated */ |
1356 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1357 | apic->apic_id_valid(apicid)) | |
1358 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1359 | } | |
2a51fe08 PB |
1360 | |
1361 | if (!num_processors) | |
1362 | num_processors = 1; | |
1363 | } | |
329513a3 | 1364 | |
5f2eb550 JB |
1365 | i = setup_max_cpus ?: 1; |
1366 | if (setup_possible_cpus == -1) { | |
1367 | possible = num_processors; | |
1368 | #ifdef CONFIG_HOTPLUG_CPU | |
1369 | if (setup_max_cpus) | |
1370 | possible += disabled_cpus; | |
1371 | #else | |
1372 | if (possible > i) | |
1373 | possible = i; | |
1374 | #endif | |
1375 | } else | |
3b11ce7f MT |
1376 | possible = setup_possible_cpus; |
1377 | ||
730cf272 MT |
1378 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1379 | ||
2b633e3f YL |
1380 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1381 | if (possible > nr_cpu_ids) { | |
9b130ad5 | 1382 | pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", |
2b633e3f YL |
1383 | possible, nr_cpu_ids); |
1384 | possible = nr_cpu_ids; | |
3b11ce7f | 1385 | } |
68a1c3f8 | 1386 | |
5f2eb550 JB |
1387 | #ifdef CONFIG_HOTPLUG_CPU |
1388 | if (!setup_max_cpus) | |
1389 | #endif | |
1390 | if (possible > i) { | |
c767a54b | 1391 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1392 | possible, setup_max_cpus); |
1393 | possible = i; | |
1394 | } | |
1395 | ||
427d77a3 TG |
1396 | nr_cpu_ids = possible; |
1397 | ||
c767a54b | 1398 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1399 | possible, max_t(int, possible - num_processors, 0)); |
1400 | ||
427d77a3 TG |
1401 | reset_cpu_possible_mask(); |
1402 | ||
68a1c3f8 | 1403 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1404 | set_cpu_possible(i, true); |
68a1c3f8 | 1405 | } |
69c18c15 | 1406 | |
14adf855 CE |
1407 | #ifdef CONFIG_HOTPLUG_CPU |
1408 | ||
70b8301f AK |
1409 | /* Recompute SMT state for all CPUs on offline */ |
1410 | static void recompute_smt_state(void) | |
1411 | { | |
1412 | int max_threads, cpu; | |
1413 | ||
1414 | max_threads = 0; | |
1415 | for_each_online_cpu (cpu) { | |
1416 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1417 | ||
1418 | if (threads > max_threads) | |
1419 | max_threads = threads; | |
1420 | } | |
1421 | __max_smt_threads = max_threads; | |
1422 | } | |
1423 | ||
14adf855 CE |
1424 | static void remove_siblinginfo(int cpu) |
1425 | { | |
1426 | int sibling; | |
1427 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1428 | ||
7d79a7bd BG |
1429 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1430 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1431 | /*/ |
1432 | * last thread sibling in this cpu core going down | |
1433 | */ | |
7d79a7bd | 1434 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1435 | cpu_data(sibling).booted_cores--; |
1436 | } | |
1437 | ||
7d79a7bd BG |
1438 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1439 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1440 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1441 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1442 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1443 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1444 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 | 1445 | c->cpu_core_id = 0; |
c2d1cec1 | 1446 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1447 | recompute_smt_state(); |
14adf855 CE |
1448 | } |
1449 | ||
4daa832d | 1450 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1451 | { |
c2d1cec1 MT |
1452 | set_cpu_online(cpu, false); |
1453 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1454 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1455 | /* was set by cpu_init() */ |
c2d1cec1 | 1456 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1457 | numa_remove_cpu(cpu); |
69c18c15 GC |
1458 | } |
1459 | ||
8227dce7 | 1460 | void cpu_disable_common(void) |
69c18c15 GC |
1461 | { |
1462 | int cpu = smp_processor_id(); | |
69c18c15 | 1463 | |
69c18c15 GC |
1464 | remove_siblinginfo(cpu); |
1465 | ||
1466 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1467 | lock_vector_lock(); |
69c18c15 | 1468 | remove_cpu_from_maps(cpu); |
d388e5fd | 1469 | unlock_vector_lock(); |
d7b381bb | 1470 | fixup_irqs(); |
0fa115da | 1471 | lapic_offline(); |
8227dce7 AN |
1472 | } |
1473 | ||
1474 | int native_cpu_disable(void) | |
1475 | { | |
da6139e4 PB |
1476 | int ret; |
1477 | ||
2cffad7b | 1478 | ret = lapic_can_unplug_cpu(); |
da6139e4 PB |
1479 | if (ret) |
1480 | return ret; | |
1481 | ||
8227dce7 | 1482 | clear_local_APIC(); |
8227dce7 | 1483 | cpu_disable_common(); |
2ed53c0d | 1484 | |
69c18c15 GC |
1485 | return 0; |
1486 | } | |
1487 | ||
2a442c9c | 1488 | int common_cpu_die(unsigned int cpu) |
54279552 | 1489 | { |
2a442c9c | 1490 | int ret = 0; |
54279552 | 1491 | |
69c18c15 | 1492 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1493 | |
2ed53c0d | 1494 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1495 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1496 | if (system_state == SYSTEM_RUNNING) |
1497 | pr_info("CPU %u is now offline\n", cpu); | |
1498 | } else { | |
1499 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1500 | ret = -1; |
69c18c15 | 1501 | } |
2a442c9c PM |
1502 | |
1503 | return ret; | |
1504 | } | |
1505 | ||
1506 | void native_cpu_die(unsigned int cpu) | |
1507 | { | |
1508 | common_cpu_die(cpu); | |
69c18c15 | 1509 | } |
a21f5d88 AN |
1510 | |
1511 | void play_dead_common(void) | |
1512 | { | |
1513 | idle_task_exit(); | |
a21f5d88 | 1514 | |
a21f5d88 | 1515 | /* Ack it */ |
2a442c9c | 1516 | (void)cpu_report_death(); |
a21f5d88 AN |
1517 | |
1518 | /* | |
1519 | * With physical CPU hotplug, we should halt the cpu | |
1520 | */ | |
1521 | local_irq_disable(); | |
1522 | } | |
1523 | ||
e1c467e6 FY |
1524 | static bool wakeup_cpu0(void) |
1525 | { | |
1526 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1527 | return true; | |
1528 | ||
1529 | return false; | |
1530 | } | |
1531 | ||
ea530692 PA |
1532 | /* |
1533 | * We need to flush the caches before going to sleep, lest we have | |
1534 | * dirty data in our caches when we come back up. | |
1535 | */ | |
1536 | static inline void mwait_play_dead(void) | |
1537 | { | |
1538 | unsigned int eax, ebx, ecx, edx; | |
1539 | unsigned int highest_cstate = 0; | |
1540 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1541 | void *mwait_ptr; |
576cfb40 | 1542 | int i; |
ea530692 | 1543 | |
69fb3676 | 1544 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1545 | return; |
840d2830 | 1546 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1547 | return; |
7b543a53 | 1548 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1549 | return; |
1550 | ||
1551 | eax = CPUID_MWAIT_LEAF; | |
1552 | ecx = 0; | |
1553 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1554 | ||
1555 | /* | |
1556 | * eax will be 0 if EDX enumeration is not valid. | |
1557 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1558 | */ | |
1559 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1560 | eax = 0; | |
1561 | } else { | |
1562 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1563 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1564 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1565 | highest_cstate = i; | |
1566 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1567 | } | |
1568 | } | |
1569 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1570 | (highest_subcstate - 1); | |
1571 | } | |
1572 | ||
ce5f6824 PA |
1573 | /* |
1574 | * This should be a memory location in a cache line which is | |
1575 | * unlikely to be touched by other processors. The actual | |
1576 | * content is immaterial as it is not actually modified in any way. | |
1577 | */ | |
1578 | mwait_ptr = ¤t_thread_info()->flags; | |
1579 | ||
a68e5c94 PA |
1580 | wbinvd(); |
1581 | ||
ea530692 | 1582 | while (1) { |
ce5f6824 PA |
1583 | /* |
1584 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1585 | * the Xeon 7400 series. It's not clear it is actually | |
1586 | * needed, but it should be harmless in either case. | |
1587 | * The WBINVD is insufficient due to the spurious-wakeup | |
1588 | * case where we return around the loop. | |
1589 | */ | |
7d590cca | 1590 | mb(); |
ce5f6824 | 1591 | clflush(mwait_ptr); |
7d590cca | 1592 | mb(); |
ce5f6824 | 1593 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1594 | mb(); |
1595 | __mwait(eax, 0); | |
e1c467e6 FY |
1596 | /* |
1597 | * If NMI wants to wake up CPU0, start CPU0. | |
1598 | */ | |
1599 | if (wakeup_cpu0()) | |
1600 | start_cpu0(); | |
ea530692 PA |
1601 | } |
1602 | } | |
1603 | ||
406f992e | 1604 | void hlt_play_dead(void) |
ea530692 | 1605 | { |
7b543a53 | 1606 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1607 | wbinvd(); |
1608 | ||
ea530692 | 1609 | while (1) { |
ea530692 | 1610 | native_halt(); |
e1c467e6 FY |
1611 | /* |
1612 | * If NMI wants to wake up CPU0, start CPU0. | |
1613 | */ | |
1614 | if (wakeup_cpu0()) | |
1615 | start_cpu0(); | |
ea530692 PA |
1616 | } |
1617 | } | |
1618 | ||
a21f5d88 AN |
1619 | void native_play_dead(void) |
1620 | { | |
1621 | play_dead_common(); | |
86886e55 | 1622 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1623 | |
1624 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1625 | if (cpuidle_play_dead()) |
1626 | hlt_play_dead(); | |
a21f5d88 AN |
1627 | } |
1628 | ||
69c18c15 | 1629 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1630 | int native_cpu_disable(void) |
69c18c15 GC |
1631 | { |
1632 | return -ENOSYS; | |
1633 | } | |
1634 | ||
93be71b6 | 1635 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1636 | { |
1637 | /* We said "no" in __cpu_disable */ | |
1638 | BUG(); | |
1639 | } | |
a21f5d88 AN |
1640 | |
1641 | void native_play_dead(void) | |
1642 | { | |
1643 | BUG(); | |
1644 | } | |
1645 | ||
68a1c3f8 | 1646 | #endif |