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Commit | Line | Data |
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4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
69c18c15 | 53 | |
8aef135c | 54 | #include <asm/acpi.h> |
cb3c8b90 | 55 | #include <asm/desc.h> |
69c18c15 GC |
56 | #include <asm/nmi.h> |
57 | #include <asm/irq.h> | |
07bbc16a | 58 | #include <asm/idle.h> |
e44b7b75 | 59 | #include <asm/trampoline.h> |
69c18c15 GC |
60 | #include <asm/cpu.h> |
61 | #include <asm/numa.h> | |
cb3c8b90 GOC |
62 | #include <asm/pgtable.h> |
63 | #include <asm/tlbflush.h> | |
64 | #include <asm/mtrr.h> | |
ea530692 | 65 | #include <asm/mwait.h> |
7b6aa335 | 66 | #include <asm/apic.h> |
569712b2 | 67 | #include <asm/setup.h> |
bdbcdd48 | 68 | #include <asm/uv/uv.h> |
cb3c8b90 | 69 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 70 | |
1164dd00 | 71 | #include <asm/smpboot_hooks.h> |
b81bb373 | 72 | #include <asm/i8259.h> |
cb3c8b90 | 73 | |
16ecf7a4 | 74 | #ifdef CONFIG_X86_32 |
4cedb334 | 75 | u8 apicid_2_node[MAX_APICID]; |
acbb6734 GOC |
76 | #endif |
77 | ||
a8db8453 GOC |
78 | /* State of each CPU */ |
79 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
80 | ||
cb3c8b90 GOC |
81 | /* Store all idle threads, this can be reused instead of creating |
82 | * a new thread. Also avoids complicated thread destroy functionality | |
83 | * for idle threads. | |
84 | */ | |
85 | #ifdef CONFIG_HOTPLUG_CPU | |
86 | /* | |
87 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
88 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
89 | */ | |
90 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
91 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
92 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
93 | |
94 | /* | |
95 | * We need this for trampoline_base protection from concurrent accesses when | |
96 | * off- and onlining cores wildly. | |
97 | */ | |
98 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
99 | ||
100 | void cpu_hotplug_driver_lock() | |
101 | { | |
102 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
103 | } | |
104 | ||
105 | void cpu_hotplug_driver_unlock() | |
106 | { | |
107 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
108 | } | |
109 | ||
110 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
111 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 112 | #else |
f86c9985 | 113 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
114 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
115 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
116 | #endif | |
f6bc4029 | 117 | |
a355352b GC |
118 | /* Number of siblings per CPU package */ |
119 | int smp_num_siblings = 1; | |
120 | EXPORT_SYMBOL(smp_num_siblings); | |
121 | ||
122 | /* Last level cache ID of each logical CPU */ | |
123 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
124 | ||
a355352b | 125 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 126 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
127 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
128 | ||
129 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 130 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
131 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
132 | ||
133 | /* Per CPU bogomips and other parameters */ | |
134 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
135 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 136 | |
2b6163bf | 137 | atomic_t init_deasserted; |
cb3c8b90 | 138 | |
7cc3959e | 139 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
140 | /* which node each logical CPU is on */ |
141 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
142 | EXPORT_SYMBOL(cpu_to_node_map); | |
143 | ||
144 | /* set up a mapping between cpu and node. */ | |
145 | static void map_cpu_to_node(int cpu, int node) | |
146 | { | |
147 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 148 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
149 | cpu_to_node_map[cpu] = node; |
150 | } | |
151 | ||
152 | /* undo a mapping between cpu and node. */ | |
153 | static void unmap_cpu_to_node(int cpu) | |
154 | { | |
155 | int node; | |
156 | ||
157 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
158 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 159 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
160 | cpu_to_node_map[cpu] = 0; |
161 | } | |
162 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
163 | #define map_cpu_to_node(cpu, node) ({}) | |
164 | #define unmap_cpu_to_node(cpu) ({}) | |
165 | #endif | |
166 | ||
167 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
168 | static int boot_cpu_logical_apicid; |
169 | ||
7cc3959e GOC |
170 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
171 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
172 | ||
a4928cff | 173 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
174 | { |
175 | int cpu = smp_processor_id(); | |
176 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 177 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
178 | |
179 | if (!node_online(node)) | |
180 | node = first_online_node; | |
181 | ||
182 | cpu_2_logical_apicid[cpu] = apicid; | |
183 | map_cpu_to_node(cpu, node); | |
184 | } | |
185 | ||
1481a3dd | 186 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
187 | { |
188 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
189 | unmap_cpu_to_node(cpu); | |
190 | } | |
191 | #else | |
7cc3959e GOC |
192 | #define map_cpu_to_logical_apicid() do {} while (0) |
193 | #endif | |
194 | ||
cb3c8b90 GOC |
195 | /* |
196 | * Report back to the Boot Processor. | |
197 | * Running on AP. | |
198 | */ | |
a4928cff | 199 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
200 | { |
201 | int cpuid, phys_id; | |
202 | unsigned long timeout; | |
203 | ||
204 | /* | |
205 | * If waken up by an INIT in an 82489DX configuration | |
206 | * we may get here before an INIT-deassert IPI reaches | |
207 | * our local APIC. We have to wait for the IPI or we'll | |
208 | * lock up on an APIC access. | |
209 | */ | |
a9659366 IM |
210 | if (apic->wait_for_init_deassert) |
211 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
212 | |
213 | /* | |
214 | * (This works even if the APIC is not enabled.) | |
215 | */ | |
4c9961d5 | 216 | phys_id = read_apic_id(); |
cb3c8b90 | 217 | cpuid = smp_processor_id(); |
c2d1cec1 | 218 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
219 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
220 | phys_id, cpuid); | |
221 | } | |
cfc1b9a6 | 222 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
223 | |
224 | /* | |
225 | * STARTUP IPIs are fragile beasts as they might sometimes | |
226 | * trigger some glue motherboard logic. Complete APIC bus | |
227 | * silence for 1 second, this overestimates the time the | |
228 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
229 | * by a factor of two. This should be enough. | |
230 | */ | |
231 | ||
232 | /* | |
233 | * Waiting 2s total for startup (udelay is not yet working) | |
234 | */ | |
235 | timeout = jiffies + 2*HZ; | |
236 | while (time_before(jiffies, timeout)) { | |
237 | /* | |
238 | * Has the boot CPU finished it's STARTUP sequence? | |
239 | */ | |
c2d1cec1 | 240 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
241 | break; |
242 | cpu_relax(); | |
243 | } | |
244 | ||
245 | if (!time_before(jiffies, timeout)) { | |
246 | panic("%s: CPU%d started up but did not get a callout!\n", | |
247 | __func__, cpuid); | |
248 | } | |
249 | ||
250 | /* | |
251 | * the boot CPU has finished the init stage and is spinning | |
252 | * on callin_map until we finish. We are free to set up this | |
253 | * CPU, first the APIC. (this is probably redundant on most | |
254 | * boards) | |
255 | */ | |
256 | ||
cfc1b9a6 | 257 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
258 | if (apic->smp_callin_clear_local_apic) |
259 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
260 | setup_local_APIC(); |
261 | end_local_APIC_setup(); | |
262 | map_cpu_to_logical_apicid(); | |
263 | ||
9d133e5d SS |
264 | /* |
265 | * Need to setup vector mappings before we enable interrupts. | |
266 | */ | |
36e9e1ea | 267 | setup_vector_irq(smp_processor_id()); |
cb3c8b90 GOC |
268 | /* |
269 | * Get our bogomips. | |
270 | * | |
271 | * Need to enable IRQs because it can take longer and then | |
272 | * the NMI watchdog might kill us. | |
273 | */ | |
274 | local_irq_enable(); | |
275 | calibrate_delay(); | |
276 | local_irq_disable(); | |
cfc1b9a6 | 277 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
278 | |
279 | /* | |
280 | * Save our processor parameters | |
281 | */ | |
282 | smp_store_cpu_info(cpuid); | |
283 | ||
85257024 PZ |
284 | notify_cpu_starting(cpuid); |
285 | ||
cb3c8b90 GOC |
286 | /* |
287 | * Allow the master to continue. | |
288 | */ | |
c2d1cec1 | 289 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
290 | } |
291 | ||
bbc2ff6a GOC |
292 | /* |
293 | * Activate a secondary processor. | |
294 | */ | |
0ca59dd9 | 295 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
296 | { |
297 | /* | |
298 | * Don't put *anything* before cpu_init(), SMP booting is too | |
299 | * fragile that we want to limit the things done here to the | |
300 | * most necessary things. | |
301 | */ | |
b40827fa BP |
302 | cpu_init(); |
303 | preempt_disable(); | |
304 | smp_callin(); | |
fd89a137 JR |
305 | |
306 | #ifdef CONFIG_X86_32 | |
b40827fa | 307 | /* switch away from the initial page table */ |
fd89a137 JR |
308 | load_cr3(swapper_pg_dir); |
309 | __flush_tlb_all(); | |
310 | #endif | |
311 | ||
bbc2ff6a GOC |
312 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
313 | barrier(); | |
314 | /* | |
315 | * Check TSC synchronization with the BP: | |
316 | */ | |
317 | check_tsc_sync_target(); | |
318 | ||
4f062896 | 319 | /* This must be done before setting cpu_online_mask */ |
bbc2ff6a GOC |
320 | set_cpu_sibling_map(raw_smp_processor_id()); |
321 | wmb(); | |
322 | ||
323 | /* | |
324 | * We need to hold call_lock, so there is no inconsistency | |
325 | * between the time smp_call_function() determines number of | |
326 | * IPI recipients, and the time when the determination is made | |
327 | * for which cpus receive the IPI. Holding this | |
328 | * lock helps us to not include this cpu in a currently in progress | |
329 | * smp_call_function(). | |
d388e5fd EB |
330 | * |
331 | * We need to hold vector_lock so there the set of online cpus | |
332 | * does not change while we are assigning vectors to cpus. Holding | |
333 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 334 | */ |
0cefa5b9 | 335 | ipi_call_lock(); |
d388e5fd | 336 | lock_vector_lock(); |
c2d1cec1 | 337 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 338 | unlock_vector_lock(); |
0cefa5b9 | 339 | ipi_call_unlock(); |
bbc2ff6a | 340 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 341 | x86_platform.nmi_init(); |
bbc2ff6a | 342 | |
0cefa5b9 MS |
343 | /* enable local interrupts */ |
344 | local_irq_enable(); | |
345 | ||
35f720c5 JP |
346 | /* to prevent fake stack check failure in clock setup */ |
347 | boot_init_stack_canary(); | |
0cefa5b9 | 348 | |
736decac | 349 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
350 | |
351 | wmb(); | |
352 | cpu_idle(); | |
353 | } | |
354 | ||
155dd720 RR |
355 | #ifdef CONFIG_CPUMASK_OFFSTACK |
356 | /* In this case, llc_shared_map is a pointer to a cpumask. */ | |
357 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
358 | const struct cpuinfo_x86 *src) | |
359 | { | |
360 | struct cpumask *llc = dst->llc_shared_map; | |
361 | *dst = *src; | |
362 | dst->llc_shared_map = llc; | |
363 | } | |
364 | #else | |
365 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
366 | const struct cpuinfo_x86 *src) | |
367 | { | |
368 | *dst = *src; | |
369 | } | |
370 | #endif /* CONFIG_CPUMASK_OFFSTACK */ | |
371 | ||
1d89a7f0 GOC |
372 | /* |
373 | * The bootstrap kernel entry code has set these up. Save them for | |
374 | * a given CPU | |
375 | */ | |
376 | ||
377 | void __cpuinit smp_store_cpu_info(int id) | |
378 | { | |
379 | struct cpuinfo_x86 *c = &cpu_data(id); | |
380 | ||
155dd720 | 381 | copy_cpuinfo_x86(c, &boot_cpu_data); |
1d89a7f0 GOC |
382 | c->cpu_index = id; |
383 | if (id != 0) | |
384 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
385 | } |
386 | ||
d4fbe4f0 AH |
387 | static void __cpuinit link_thread_siblings(int cpu1, int cpu2) |
388 | { | |
389 | struct cpuinfo_x86 *c1 = &cpu_data(cpu1); | |
390 | struct cpuinfo_x86 *c2 = &cpu_data(cpu2); | |
391 | ||
392 | cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); | |
393 | cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); | |
394 | cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); | |
395 | cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); | |
396 | cpumask_set_cpu(cpu1, c2->llc_shared_map); | |
397 | cpumask_set_cpu(cpu2, c1->llc_shared_map); | |
398 | } | |
399 | ||
1d89a7f0 | 400 | |
768d9505 GC |
401 | void __cpuinit set_cpu_sibling_map(int cpu) |
402 | { | |
403 | int i; | |
404 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
405 | ||
c2d1cec1 | 406 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
407 | |
408 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
409 | for_each_cpu(i, cpu_sibling_setup_mask) { |
410 | struct cpuinfo_x86 *o = &cpu_data(i); | |
411 | ||
d4fbe4f0 AH |
412 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
413 | if (c->phys_proc_id == o->phys_proc_id && | |
414 | c->compute_unit_id == o->compute_unit_id) | |
415 | link_thread_siblings(cpu, i); | |
416 | } else if (c->phys_proc_id == o->phys_proc_id && | |
417 | c->cpu_core_id == o->cpu_core_id) { | |
418 | link_thread_siblings(cpu, i); | |
768d9505 GC |
419 | } |
420 | } | |
421 | } else { | |
c2d1cec1 | 422 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
423 | } |
424 | ||
155dd720 | 425 | cpumask_set_cpu(cpu, c->llc_shared_map); |
768d9505 GC |
426 | |
427 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 428 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
429 | c->booted_cores = 1; |
430 | return; | |
431 | } | |
432 | ||
c2d1cec1 | 433 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
434 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
435 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
155dd720 RR |
436 | cpumask_set_cpu(i, c->llc_shared_map); |
437 | cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); | |
768d9505 GC |
438 | } |
439 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
440 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
441 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
442 | /* |
443 | * Does this new cpu bringup a new core? | |
444 | */ | |
c2d1cec1 | 445 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
446 | /* |
447 | * for each core in package, increment | |
448 | * the booted_cores for this new cpu | |
449 | */ | |
c2d1cec1 | 450 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
451 | c->booted_cores++; |
452 | /* | |
453 | * increment the core count for all | |
454 | * the other cpus in this package | |
455 | */ | |
456 | if (i != cpu) | |
457 | cpu_data(i).booted_cores++; | |
458 | } else if (i != cpu && !c->booted_cores) | |
459 | c->booted_cores = cpu_data(i).booted_cores; | |
460 | } | |
461 | } | |
462 | } | |
463 | ||
70708a18 | 464 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 465 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
466 | { |
467 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
468 | /* | |
469 | * For perf, we return last level cache shared map. | |
470 | * And for power savings, we return cpu_core_map | |
471 | */ | |
5a925b42 AH |
472 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
473 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 474 | return cpu_core_mask(cpu); |
70708a18 | 475 | else |
155dd720 | 476 | return c->llc_shared_map; |
030bb203 RR |
477 | } |
478 | ||
a4928cff | 479 | static void impress_friends(void) |
904541e2 GOC |
480 | { |
481 | int cpu; | |
482 | unsigned long bogosum = 0; | |
483 | /* | |
484 | * Allow the user to impress friends. | |
485 | */ | |
cfc1b9a6 | 486 | pr_debug("Before bogomips.\n"); |
904541e2 | 487 | for_each_possible_cpu(cpu) |
c2d1cec1 | 488 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
489 | bogosum += cpu_data(cpu).loops_per_jiffy; |
490 | printk(KERN_INFO | |
491 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 492 | num_online_cpus(), |
904541e2 GOC |
493 | bogosum/(500000/HZ), |
494 | (bogosum/(5000/HZ))%100); | |
495 | ||
cfc1b9a6 | 496 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
497 | } |
498 | ||
569712b2 | 499 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
500 | { |
501 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
502 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
503 | int timeout; | |
504 | u32 status; | |
505 | ||
823b259b | 506 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
507 | |
508 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 509 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
510 | |
511 | /* | |
512 | * Wait for idle. | |
513 | */ | |
514 | status = safe_apic_wait_icr_idle(); | |
515 | if (status) | |
516 | printk(KERN_CONT | |
517 | "a previous APIC delivery may have failed\n"); | |
518 | ||
1b374e4d | 519 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
520 | |
521 | timeout = 0; | |
522 | do { | |
523 | udelay(100); | |
524 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
525 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
526 | ||
527 | switch (status) { | |
528 | case APIC_ICR_RR_VALID: | |
529 | status = apic_read(APIC_RRR); | |
530 | printk(KERN_CONT "%08x\n", status); | |
531 | break; | |
532 | default: | |
533 | printk(KERN_CONT "failed\n"); | |
534 | } | |
535 | } | |
536 | } | |
537 | ||
cb3c8b90 GOC |
538 | /* |
539 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
540 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
541 | * won't ... remember to clear down the APIC, etc later. | |
542 | */ | |
cece3155 | 543 | int __cpuinit |
569712b2 | 544 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
545 | { |
546 | unsigned long send_status, accept_status = 0; | |
547 | int maxlvt; | |
548 | ||
549 | /* Target chip */ | |
cb3c8b90 GOC |
550 | /* Boot on the stack */ |
551 | /* Kick the second */ | |
bdb1a9b6 | 552 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 553 | |
cfc1b9a6 | 554 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
555 | send_status = safe_apic_wait_icr_idle(); |
556 | ||
557 | /* | |
558 | * Give the other CPU some time to accept the IPI. | |
559 | */ | |
560 | udelay(200); | |
569712b2 | 561 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
562 | maxlvt = lapic_get_maxlvt(); |
563 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
564 | apic_write(APIC_ESR, 0); | |
565 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
566 | } | |
cfc1b9a6 | 567 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
568 | |
569 | if (send_status) | |
570 | printk(KERN_ERR "APIC never delivered???\n"); | |
571 | if (accept_status) | |
572 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
573 | ||
574 | return (send_status | accept_status); | |
575 | } | |
cb3c8b90 | 576 | |
cece3155 | 577 | static int __cpuinit |
569712b2 | 578 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
579 | { |
580 | unsigned long send_status, accept_status = 0; | |
581 | int maxlvt, num_starts, j; | |
582 | ||
593f4a78 MR |
583 | maxlvt = lapic_get_maxlvt(); |
584 | ||
cb3c8b90 GOC |
585 | /* |
586 | * Be paranoid about clearing APIC errors. | |
587 | */ | |
588 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
589 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
590 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
591 | apic_read(APIC_ESR); |
592 | } | |
593 | ||
cfc1b9a6 | 594 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
595 | |
596 | /* | |
597 | * Turn INIT on target chip | |
598 | */ | |
cb3c8b90 GOC |
599 | /* |
600 | * Send IPI | |
601 | */ | |
1b374e4d SS |
602 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
603 | phys_apicid); | |
cb3c8b90 | 604 | |
cfc1b9a6 | 605 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
606 | send_status = safe_apic_wait_icr_idle(); |
607 | ||
608 | mdelay(10); | |
609 | ||
cfc1b9a6 | 610 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
611 | |
612 | /* Target chip */ | |
cb3c8b90 | 613 | /* Send IPI */ |
1b374e4d | 614 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 615 | |
cfc1b9a6 | 616 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
617 | send_status = safe_apic_wait_icr_idle(); |
618 | ||
619 | mb(); | |
620 | atomic_set(&init_deasserted, 1); | |
621 | ||
622 | /* | |
623 | * Should we send STARTUP IPIs ? | |
624 | * | |
625 | * Determine this based on the APIC version. | |
626 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
627 | */ | |
628 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
629 | num_starts = 2; | |
630 | else | |
631 | num_starts = 0; | |
632 | ||
633 | /* | |
634 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
635 | * target processor state. | |
636 | */ | |
637 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 638 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
639 | |
640 | /* | |
641 | * Run STARTUP IPI loop. | |
642 | */ | |
cfc1b9a6 | 643 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 644 | |
cb3c8b90 | 645 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 646 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
647 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
648 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 649 | apic_read(APIC_ESR); |
cfc1b9a6 | 650 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
651 | |
652 | /* | |
653 | * STARTUP IPI | |
654 | */ | |
655 | ||
656 | /* Target chip */ | |
cb3c8b90 GOC |
657 | /* Boot on the stack */ |
658 | /* Kick the second */ | |
1b374e4d SS |
659 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
660 | phys_apicid); | |
cb3c8b90 GOC |
661 | |
662 | /* | |
663 | * Give the other CPU some time to accept the IPI. | |
664 | */ | |
665 | udelay(300); | |
666 | ||
cfc1b9a6 | 667 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 668 | |
cfc1b9a6 | 669 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
670 | send_status = safe_apic_wait_icr_idle(); |
671 | ||
672 | /* | |
673 | * Give the other CPU some time to accept the IPI. | |
674 | */ | |
675 | udelay(200); | |
593f4a78 | 676 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 677 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
678 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
679 | if (send_status || accept_status) | |
680 | break; | |
681 | } | |
cfc1b9a6 | 682 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
683 | |
684 | if (send_status) | |
685 | printk(KERN_ERR "APIC never delivered???\n"); | |
686 | if (accept_status) | |
687 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
688 | ||
689 | return (send_status | accept_status); | |
690 | } | |
cb3c8b90 GOC |
691 | |
692 | struct create_idle { | |
693 | struct work_struct work; | |
694 | struct task_struct *idle; | |
695 | struct completion done; | |
696 | int cpu; | |
697 | }; | |
698 | ||
699 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
700 | { | |
701 | struct create_idle *c_idle = | |
702 | container_of(work, struct create_idle, work); | |
703 | ||
704 | c_idle->idle = fork_idle(c_idle->cpu); | |
705 | complete(&c_idle->done); | |
706 | } | |
707 | ||
2eaad1fd MT |
708 | /* reduce the number of lines printed when booting a large cpu count system */ |
709 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
710 | { | |
711 | static int current_node = -1; | |
4adc8b71 | 712 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
713 | |
714 | if (system_state == SYSTEM_BOOTING) { | |
715 | if (node != current_node) { | |
716 | if (current_node > (-1)) | |
717 | pr_cont(" Ok.\n"); | |
718 | current_node = node; | |
719 | pr_info("Booting Node %3d, Processors ", node); | |
720 | } | |
721 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
722 | return; | |
723 | } else | |
724 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
725 | node, cpu, apicid); | |
726 | } | |
727 | ||
cb3c8b90 GOC |
728 | /* |
729 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
730 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
731 | * Returns zero if CPU booted OK, else error code from |
732 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 733 | */ |
ab6fb7c0 | 734 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
735 | { |
736 | unsigned long boot_error = 0; | |
cb3c8b90 | 737 | unsigned long start_ip; |
ab6fb7c0 | 738 | int timeout; |
cb3c8b90 | 739 | struct create_idle c_idle = { |
ab6fb7c0 IM |
740 | .cpu = cpu, |
741 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 742 | }; |
ab6fb7c0 | 743 | |
ca1cab37 | 744 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 745 | |
cb3c8b90 GOC |
746 | alternatives_smp_switch(1); |
747 | ||
748 | c_idle.idle = get_idle_for_cpu(cpu); | |
749 | ||
750 | /* | |
751 | * We can't use kernel_thread since we must avoid to | |
752 | * reschedule the child. | |
753 | */ | |
754 | if (c_idle.idle) { | |
755 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
756 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
757 | init_idle(c_idle.idle, cpu); | |
758 | goto do_rest; | |
759 | } | |
760 | ||
d7a7c573 SS |
761 | schedule_work(&c_idle.work); |
762 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
763 | |
764 | if (IS_ERR(c_idle.idle)) { | |
765 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 766 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
767 | return PTR_ERR(c_idle.idle); |
768 | } | |
769 | ||
770 | set_idle_for_cpu(cpu, c_idle.idle); | |
771 | do_rest: | |
cb3c8b90 | 772 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 773 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 774 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
775 | irq_ctx_init(cpu); |
776 | #else | |
cb3c8b90 | 777 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 778 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
779 | per_cpu(kernel_stack, cpu) = |
780 | (unsigned long)task_stack_page(c_idle.idle) - | |
781 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 782 | #endif |
a939098a | 783 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 784 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 785 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
786 | |
787 | /* start_ip had better be page-aligned! */ | |
788 | start_ip = setup_trampoline(); | |
789 | ||
2eaad1fd MT |
790 | /* So we see what's up */ |
791 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
792 | |
793 | /* | |
794 | * This grunge runs the startup process for | |
795 | * the targeted processor. | |
796 | */ | |
797 | ||
798 | atomic_set(&init_deasserted, 0); | |
799 | ||
34d05591 | 800 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 801 | |
cfc1b9a6 | 802 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 803 | |
34d05591 JS |
804 | smpboot_setup_warm_reset_vector(start_ip); |
805 | /* | |
806 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
807 | */ |
808 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
809 | apic_write(APIC_ESR, 0); | |
810 | apic_read(APIC_ESR); | |
811 | } | |
34d05591 | 812 | } |
cb3c8b90 | 813 | |
cb3c8b90 | 814 | /* |
1f5bcabf IM |
815 | * Kick the secondary CPU. Use the method in the APIC driver |
816 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 817 | */ |
1f5bcabf IM |
818 | if (apic->wakeup_secondary_cpu) |
819 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
820 | else | |
821 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
822 | |
823 | if (!boot_error) { | |
824 | /* | |
825 | * allow APs to start initializing. | |
826 | */ | |
cfc1b9a6 | 827 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 828 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 829 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
830 | |
831 | /* | |
832 | * Wait 5s total for a response | |
833 | */ | |
834 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 835 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
836 | break; /* It has booted */ |
837 | udelay(100); | |
68f202e4 SS |
838 | /* |
839 | * Allow other tasks to run while we wait for the | |
840 | * AP to come online. This also gives a chance | |
841 | * for the MTRR work(triggered by the AP coming online) | |
842 | * to be completed in the stop machine context. | |
843 | */ | |
844 | schedule(); | |
cb3c8b90 GOC |
845 | } |
846 | ||
2eaad1fd MT |
847 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
848 | pr_debug("CPU%d: has booted.\n", cpu); | |
849 | else { | |
cb3c8b90 GOC |
850 | boot_error = 1; |
851 | if (*((volatile unsigned char *)trampoline_base) | |
852 | == 0xA5) | |
853 | /* trampoline started but...? */ | |
2eaad1fd | 854 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
855 | else |
856 | /* trampoline code not run */ | |
2eaad1fd | 857 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
858 | if (apic->inquire_remote_apic) |
859 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
860 | } |
861 | } | |
1a51e3a0 | 862 | |
cb3c8b90 GOC |
863 | if (boot_error) { |
864 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 865 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
866 | |
867 | /* was set by do_boot_cpu() */ | |
868 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
869 | ||
870 | /* was set by cpu_init() */ | |
871 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
872 | ||
873 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
874 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
875 | } | |
876 | ||
877 | /* mark "stuck" area as not stuck */ | |
878 | *((volatile unsigned long *)trampoline_base) = 0; | |
879 | ||
02421f98 YL |
880 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
881 | /* | |
882 | * Cleanup possible dangling ends... | |
883 | */ | |
884 | smpboot_restore_warm_reset_vector(); | |
885 | } | |
63d38198 | 886 | |
dc186ad7 | 887 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
888 | return boot_error; |
889 | } | |
890 | ||
891 | int __cpuinit native_cpu_up(unsigned int cpu) | |
892 | { | |
a21769a4 | 893 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
894 | unsigned long flags; |
895 | int err; | |
896 | ||
897 | WARN_ON(irqs_disabled()); | |
898 | ||
cfc1b9a6 | 899 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
900 | |
901 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
902 | !physid_isset(apicid, phys_cpu_present_map)) { | |
903 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
904 | return -EINVAL; | |
905 | } | |
906 | ||
907 | /* | |
908 | * Already booted CPU? | |
909 | */ | |
c2d1cec1 | 910 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 911 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
912 | return -ENOSYS; |
913 | } | |
914 | ||
915 | /* | |
916 | * Save current MTRR state in case it was changed since early boot | |
917 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
918 | */ | |
919 | mtrr_save_state(); | |
920 | ||
921 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
922 | ||
cb3c8b90 | 923 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 924 | if (err) { |
cfc1b9a6 | 925 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 926 | return -EIO; |
cb3c8b90 GOC |
927 | } |
928 | ||
929 | /* | |
930 | * Check TSC synchronization with the AP (keep irqs disabled | |
931 | * while doing so): | |
932 | */ | |
933 | local_irq_save(flags); | |
934 | check_tsc_sync_source(cpu); | |
935 | local_irq_restore(flags); | |
936 | ||
7c04e64a | 937 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
938 | cpu_relax(); |
939 | touch_nmi_watchdog(); | |
940 | } | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
8aef135c GOC |
945 | /* |
946 | * Fall back to non SMP mode after errors. | |
947 | * | |
948 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
949 | */ | |
950 | static __init void disable_smp(void) | |
951 | { | |
4f062896 RR |
952 | init_cpu_present(cpumask_of(0)); |
953 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 954 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 955 | |
8aef135c | 956 | if (smp_found_config) |
b6df1b8b | 957 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 958 | else |
b6df1b8b | 959 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 960 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
961 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
962 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
963 | } |
964 | ||
965 | /* | |
966 | * Various sanity checks. | |
967 | */ | |
968 | static int __init smp_sanity_check(unsigned max_cpus) | |
969 | { | |
ac23d4ee | 970 | preempt_disable(); |
a58f03b0 | 971 | |
1ff2f20d | 972 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
973 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
974 | unsigned int cpu; | |
975 | unsigned nr; | |
976 | ||
977 | printk(KERN_WARNING | |
978 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 979 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
980 | |
981 | nr = 0; | |
982 | for_each_present_cpu(cpu) { | |
983 | if (nr >= 8) | |
c2d1cec1 | 984 | set_cpu_present(cpu, false); |
a58f03b0 YL |
985 | nr++; |
986 | } | |
987 | ||
988 | nr = 0; | |
989 | for_each_possible_cpu(cpu) { | |
990 | if (nr >= 8) | |
c2d1cec1 | 991 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
992 | nr++; |
993 | } | |
994 | ||
995 | nr_cpu_ids = 8; | |
996 | } | |
997 | #endif | |
998 | ||
8aef135c | 999 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
1000 | printk(KERN_WARNING |
1001 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1002 | hard_smp_processor_id()); | |
1003 | ||
8aef135c GOC |
1004 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1005 | } | |
1006 | ||
1007 | /* | |
1008 | * If we couldn't find an SMP configuration at boot time, | |
1009 | * get out of here now! | |
1010 | */ | |
1011 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1012 | preempt_enable(); |
8aef135c GOC |
1013 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1014 | disable_smp(); | |
1015 | if (APIC_init_uniprocessor()) | |
1016 | printk(KERN_NOTICE "Local APIC not detected." | |
1017 | " Using dummy APIC emulation.\n"); | |
1018 | return -1; | |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * Should not be necessary because the MP table should list the boot | |
1023 | * CPU too, but we do it for the sake of robustness anyway. | |
1024 | */ | |
a27a6210 | 1025 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
1026 | printk(KERN_NOTICE |
1027 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1028 | boot_cpu_physical_apicid); | |
1029 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1030 | } | |
ac23d4ee | 1031 | preempt_enable(); |
8aef135c GOC |
1032 | |
1033 | /* | |
1034 | * If we couldn't find a local APIC, then get out of here now! | |
1035 | */ | |
1036 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1037 | !cpu_has_apic) { | |
103428e5 CG |
1038 | if (!disable_apic) { |
1039 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1040 | boot_cpu_physical_apicid); | |
1041 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 1042 | "(tell your hw vendor)\n"); |
103428e5 | 1043 | } |
8aef135c | 1044 | smpboot_clear_io_apic(); |
65a4e574 | 1045 | arch_disable_smp_support(); |
8aef135c GOC |
1046 | return -1; |
1047 | } | |
1048 | ||
1049 | verify_local_APIC(); | |
1050 | ||
1051 | /* | |
1052 | * If SMP should be disabled, then really disable it! | |
1053 | */ | |
1054 | if (!max_cpus) { | |
73d08e63 | 1055 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1056 | smpboot_clear_io_apic(); |
d54db1ac | 1057 | |
e90955c2 | 1058 | connect_bsp_APIC(); |
e90955c2 JB |
1059 | setup_local_APIC(); |
1060 | end_local_APIC_setup(); | |
8aef135c GOC |
1061 | return -1; |
1062 | } | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | static void __init smp_cpu_index_default(void) | |
1068 | { | |
1069 | int i; | |
1070 | struct cpuinfo_x86 *c; | |
1071 | ||
7c04e64a | 1072 | for_each_possible_cpu(i) { |
8aef135c GOC |
1073 | c = &cpu_data(i); |
1074 | /* mark all to hotplug */ | |
9628937d | 1075 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1076 | } |
1077 | } | |
1078 | ||
1079 | /* | |
1080 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1081 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1082 | */ | |
1083 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1084 | { | |
7ad728f9 RR |
1085 | unsigned int i; |
1086 | ||
deef3250 | 1087 | preempt_disable(); |
8aef135c GOC |
1088 | smp_cpu_index_default(); |
1089 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1090 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1091 | mb(); |
1092 | /* | |
1093 | * Setup boot CPU information | |
1094 | */ | |
1095 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1096 | #ifdef CONFIG_X86_32 |
8aef135c | 1097 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1098 | #endif |
8aef135c | 1099 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1100 | for_each_possible_cpu(i) { |
79f55997 LZ |
1101 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1102 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
1103 | zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); | |
7ad728f9 | 1104 | } |
8aef135c GOC |
1105 | set_cpu_sibling_map(0); |
1106 | ||
6e1cb38a | 1107 | |
8aef135c GOC |
1108 | if (smp_sanity_check(max_cpus) < 0) { |
1109 | printk(KERN_INFO "SMP disabled\n"); | |
1110 | disable_smp(); | |
deef3250 | 1111 | goto out; |
8aef135c GOC |
1112 | } |
1113 | ||
fa47f7e5 SS |
1114 | default_setup_apic_routing(); |
1115 | ||
ac23d4ee | 1116 | preempt_disable(); |
4c9961d5 | 1117 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1118 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1119 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1120 | /* Or can we switch back to PIC here? */ |
1121 | } | |
ac23d4ee | 1122 | preempt_enable(); |
8aef135c | 1123 | |
8aef135c | 1124 | connect_bsp_APIC(); |
b5841765 | 1125 | |
8aef135c GOC |
1126 | /* |
1127 | * Switch from PIC to APIC mode. | |
1128 | */ | |
1129 | setup_local_APIC(); | |
1130 | ||
8aef135c GOC |
1131 | /* |
1132 | * Enable IO APIC before setting up error vector | |
1133 | */ | |
1134 | if (!skip_ioapic_setup && nr_ioapics) | |
1135 | enable_IO_APIC(); | |
88d0f550 | 1136 | |
8aef135c GOC |
1137 | end_local_APIC_setup(); |
1138 | ||
1139 | map_cpu_to_logical_apicid(); | |
1140 | ||
d83093b5 IM |
1141 | if (apic->setup_portio_remap) |
1142 | apic->setup_portio_remap(); | |
8aef135c GOC |
1143 | |
1144 | smpboot_setup_io_apic(); | |
1145 | /* | |
1146 | * Set up local APIC timer on boot CPU. | |
1147 | */ | |
1148 | ||
1149 | printk(KERN_INFO "CPU%d: ", 0); | |
1150 | print_cpu_info(&cpu_data(0)); | |
736decac | 1151 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1152 | |
1153 | if (is_uv_system()) | |
1154 | uv_system_init(); | |
d0af9eed SS |
1155 | |
1156 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1157 | out: |
1158 | preempt_enable(); | |
8aef135c | 1159 | } |
d0af9eed SS |
1160 | |
1161 | void arch_enable_nonboot_cpus_begin(void) | |
1162 | { | |
1163 | set_mtrr_aps_delayed_init(); | |
1164 | } | |
1165 | ||
1166 | void arch_enable_nonboot_cpus_end(void) | |
1167 | { | |
1168 | mtrr_aps_init(); | |
1169 | } | |
1170 | ||
a8db8453 GOC |
1171 | /* |
1172 | * Early setup to make printk work. | |
1173 | */ | |
1174 | void __init native_smp_prepare_boot_cpu(void) | |
1175 | { | |
1176 | int me = smp_processor_id(); | |
552be871 | 1177 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1178 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1179 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1180 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1181 | } | |
1182 | ||
83f7eb9c GOC |
1183 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1184 | { | |
cfc1b9a6 | 1185 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1186 | |
1187 | impress_friends(); | |
83f7eb9c GOC |
1188 | #ifdef CONFIG_X86_IO_APIC |
1189 | setup_ioapic_dest(); | |
1190 | #endif | |
d0af9eed | 1191 | mtrr_aps_init(); |
83f7eb9c GOC |
1192 | } |
1193 | ||
3b11ce7f MT |
1194 | static int __initdata setup_possible_cpus = -1; |
1195 | static int __init _setup_possible_cpus(char *str) | |
1196 | { | |
1197 | get_option(&str, &setup_possible_cpus); | |
1198 | return 0; | |
1199 | } | |
1200 | early_param("possible_cpus", _setup_possible_cpus); | |
1201 | ||
1202 | ||
68a1c3f8 | 1203 | /* |
4f062896 | 1204 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1205 | * are onlined, or offlined. The reason is per-cpu data-structures |
1206 | * are allocated by some modules at init time, and dont expect to | |
1207 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1208 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1209 | * In case when cpu_hotplug is not compiled, then we resort to current |
1210 | * behaviour, which is cpu_possible == cpu_present. | |
1211 | * - Ashok Raj | |
1212 | * | |
1213 | * Three ways to find out the number of additional hotplug CPUs: | |
1214 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1215 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1216 | * - Otherwise don't reserve additional CPUs. |
1217 | * We do this because additional CPUs waste a lot of memory. | |
1218 | * -AK | |
1219 | */ | |
1220 | __init void prefill_possible_map(void) | |
1221 | { | |
cb48bb59 | 1222 | int i, possible; |
68a1c3f8 | 1223 | |
329513a3 YL |
1224 | /* no processor from mptable or madt */ |
1225 | if (!num_processors) | |
1226 | num_processors = 1; | |
1227 | ||
5f2eb550 JB |
1228 | i = setup_max_cpus ?: 1; |
1229 | if (setup_possible_cpus == -1) { | |
1230 | possible = num_processors; | |
1231 | #ifdef CONFIG_HOTPLUG_CPU | |
1232 | if (setup_max_cpus) | |
1233 | possible += disabled_cpus; | |
1234 | #else | |
1235 | if (possible > i) | |
1236 | possible = i; | |
1237 | #endif | |
1238 | } else | |
3b11ce7f MT |
1239 | possible = setup_possible_cpus; |
1240 | ||
730cf272 MT |
1241 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1242 | ||
2b633e3f YL |
1243 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1244 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1245 | printk(KERN_WARNING |
1246 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1247 | possible, nr_cpu_ids); |
1248 | possible = nr_cpu_ids; | |
3b11ce7f | 1249 | } |
68a1c3f8 | 1250 | |
5f2eb550 JB |
1251 | #ifdef CONFIG_HOTPLUG_CPU |
1252 | if (!setup_max_cpus) | |
1253 | #endif | |
1254 | if (possible > i) { | |
1255 | printk(KERN_WARNING | |
1256 | "%d Processors exceeds max_cpus limit of %u\n", | |
1257 | possible, setup_max_cpus); | |
1258 | possible = i; | |
1259 | } | |
1260 | ||
68a1c3f8 GC |
1261 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1262 | possible, max_t(int, possible - num_processors, 0)); | |
1263 | ||
1264 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1265 | set_cpu_possible(i, true); |
5f2eb550 JB |
1266 | for (; i < NR_CPUS; i++) |
1267 | set_cpu_possible(i, false); | |
3461b0af MT |
1268 | |
1269 | nr_cpu_ids = possible; | |
68a1c3f8 | 1270 | } |
69c18c15 | 1271 | |
14adf855 CE |
1272 | #ifdef CONFIG_HOTPLUG_CPU |
1273 | ||
1274 | static void remove_siblinginfo(int cpu) | |
1275 | { | |
1276 | int sibling; | |
1277 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1278 | ||
c2d1cec1 MT |
1279 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1280 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1281 | /*/ |
1282 | * last thread sibling in this cpu core going down | |
1283 | */ | |
c2d1cec1 | 1284 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1285 | cpu_data(sibling).booted_cores--; |
1286 | } | |
1287 | ||
c2d1cec1 MT |
1288 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1289 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1290 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1291 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1292 | c->phys_proc_id = 0; |
1293 | c->cpu_core_id = 0; | |
c2d1cec1 | 1294 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1295 | } |
1296 | ||
69c18c15 GC |
1297 | static void __ref remove_cpu_from_maps(int cpu) |
1298 | { | |
c2d1cec1 MT |
1299 | set_cpu_online(cpu, false); |
1300 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1301 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1302 | /* was set by cpu_init() */ |
c2d1cec1 | 1303 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1304 | numa_remove_cpu(cpu); |
69c18c15 GC |
1305 | } |
1306 | ||
8227dce7 | 1307 | void cpu_disable_common(void) |
69c18c15 GC |
1308 | { |
1309 | int cpu = smp_processor_id(); | |
69c18c15 | 1310 | |
69c18c15 GC |
1311 | remove_siblinginfo(cpu); |
1312 | ||
1313 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1314 | lock_vector_lock(); |
69c18c15 | 1315 | remove_cpu_from_maps(cpu); |
d388e5fd | 1316 | unlock_vector_lock(); |
d7b381bb | 1317 | fixup_irqs(); |
8227dce7 AN |
1318 | } |
1319 | ||
1320 | int native_cpu_disable(void) | |
1321 | { | |
1322 | int cpu = smp_processor_id(); | |
1323 | ||
1324 | /* | |
1325 | * Perhaps use cpufreq to drop frequency, but that could go | |
1326 | * into generic code. | |
1327 | * | |
1328 | * We won't take down the boot processor on i386 due to some | |
1329 | * interrupts only being able to be serviced by the BSP. | |
1330 | * Especially so if we're not using an IOAPIC -zwane | |
1331 | */ | |
1332 | if (cpu == 0) | |
1333 | return -EBUSY; | |
1334 | ||
8227dce7 AN |
1335 | clear_local_APIC(); |
1336 | ||
1337 | cpu_disable_common(); | |
69c18c15 GC |
1338 | return 0; |
1339 | } | |
1340 | ||
93be71b6 | 1341 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1342 | { |
1343 | /* We don't do anything here: idle task is faking death itself. */ | |
1344 | unsigned int i; | |
1345 | ||
1346 | for (i = 0; i < 10; i++) { | |
1347 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1348 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1349 | if (system_state == SYSTEM_RUNNING) |
1350 | pr_info("CPU %u is now offline\n", cpu); | |
1351 | ||
69c18c15 GC |
1352 | if (1 == num_online_cpus()) |
1353 | alternatives_smp_switch(0); | |
1354 | return; | |
1355 | } | |
1356 | msleep(100); | |
1357 | } | |
2eaad1fd | 1358 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1359 | } |
a21f5d88 AN |
1360 | |
1361 | void play_dead_common(void) | |
1362 | { | |
1363 | idle_task_exit(); | |
1364 | reset_lazy_tlbstate(); | |
07bbc16a | 1365 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1366 | |
1367 | mb(); | |
1368 | /* Ack it */ | |
1369 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1370 | ||
1371 | /* | |
1372 | * With physical CPU hotplug, we should halt the cpu | |
1373 | */ | |
1374 | local_irq_disable(); | |
1375 | } | |
1376 | ||
ea530692 PA |
1377 | /* |
1378 | * We need to flush the caches before going to sleep, lest we have | |
1379 | * dirty data in our caches when we come back up. | |
1380 | */ | |
1381 | static inline void mwait_play_dead(void) | |
1382 | { | |
1383 | unsigned int eax, ebx, ecx, edx; | |
1384 | unsigned int highest_cstate = 0; | |
1385 | unsigned int highest_subcstate = 0; | |
1386 | int i; | |
ce5f6824 | 1387 | void *mwait_ptr; |
ea530692 PA |
1388 | |
1389 | if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT)) | |
1390 | return; | |
ce5f6824 PA |
1391 | if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH)) |
1392 | return; | |
ea530692 PA |
1393 | if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) |
1394 | return; | |
1395 | ||
1396 | eax = CPUID_MWAIT_LEAF; | |
1397 | ecx = 0; | |
1398 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1399 | ||
1400 | /* | |
1401 | * eax will be 0 if EDX enumeration is not valid. | |
1402 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1403 | */ | |
1404 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1405 | eax = 0; | |
1406 | } else { | |
1407 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1408 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1409 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1410 | highest_cstate = i; | |
1411 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1412 | } | |
1413 | } | |
1414 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1415 | (highest_subcstate - 1); | |
1416 | } | |
1417 | ||
ce5f6824 PA |
1418 | /* |
1419 | * This should be a memory location in a cache line which is | |
1420 | * unlikely to be touched by other processors. The actual | |
1421 | * content is immaterial as it is not actually modified in any way. | |
1422 | */ | |
1423 | mwait_ptr = ¤t_thread_info()->flags; | |
1424 | ||
a68e5c94 PA |
1425 | wbinvd(); |
1426 | ||
ea530692 | 1427 | while (1) { |
ce5f6824 PA |
1428 | /* |
1429 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1430 | * the Xeon 7400 series. It's not clear it is actually | |
1431 | * needed, but it should be harmless in either case. | |
1432 | * The WBINVD is insufficient due to the spurious-wakeup | |
1433 | * case where we return around the loop. | |
1434 | */ | |
1435 | clflush(mwait_ptr); | |
1436 | __monitor(mwait_ptr, 0, 0); | |
ea530692 PA |
1437 | mb(); |
1438 | __mwait(eax, 0); | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | static inline void hlt_play_dead(void) | |
1443 | { | |
a68e5c94 PA |
1444 | if (current_cpu_data.x86 >= 4) |
1445 | wbinvd(); | |
1446 | ||
ea530692 | 1447 | while (1) { |
ea530692 PA |
1448 | native_halt(); |
1449 | } | |
1450 | } | |
1451 | ||
a21f5d88 AN |
1452 | void native_play_dead(void) |
1453 | { | |
1454 | play_dead_common(); | |
86886e55 | 1455 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1456 | |
1457 | mwait_play_dead(); /* Only returns on failure */ | |
1458 | hlt_play_dead(); | |
a21f5d88 AN |
1459 | } |
1460 | ||
69c18c15 | 1461 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1462 | int native_cpu_disable(void) |
69c18c15 GC |
1463 | { |
1464 | return -ENOSYS; | |
1465 | } | |
1466 | ||
93be71b6 | 1467 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1468 | { |
1469 | /* We said "no" in __cpu_disable */ | |
1470 | BUG(); | |
1471 | } | |
a21f5d88 AN |
1472 | |
1473 | void native_play_dead(void) | |
1474 | { | |
1475 | BUG(); | |
1476 | } | |
1477 | ||
68a1c3f8 | 1478 | #endif |