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Commit | Line | Data |
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4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
4cedb334 GOC |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
07bbc16a | 55 | #include <asm/idle.h> |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
bbc2ff6a | 62 | #include <asm/vmi.h> |
34d05591 | 63 | #include <asm/genapic.h> |
569712b2 | 64 | #include <asm/setup.h> |
bdbcdd48 | 65 | #include <asm/uv/uv.h> |
cb3c8b90 | 66 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 67 | |
f6bc4029 | 68 | #include <mach_apic.h> |
cb3c8b90 GOC |
69 | #include <mach_wakecpu.h> |
70 | #include <smpboot_hooks.h> | |
71 | ||
16ecf7a4 | 72 | #ifdef CONFIG_X86_32 |
4cedb334 | 73 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 74 | static int low_mappings; |
acbb6734 GOC |
75 | #endif |
76 | ||
a8db8453 GOC |
77 | /* State of each CPU */ |
78 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
79 | ||
cb3c8b90 GOC |
80 | /* Store all idle threads, this can be reused instead of creating |
81 | * a new thread. Also avoids complicated thread destroy functionality | |
82 | * for idle threads. | |
83 | */ | |
84 | #ifdef CONFIG_HOTPLUG_CPU | |
85 | /* | |
86 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
87 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
88 | */ | |
89 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
90 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
91 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
92 | #else | |
f86c9985 | 93 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
94 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
95 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
96 | #endif | |
f6bc4029 | 97 | |
a355352b GC |
98 | /* Number of siblings per CPU package */ |
99 | int smp_num_siblings = 1; | |
100 | EXPORT_SYMBOL(smp_num_siblings); | |
101 | ||
102 | /* Last level cache ID of each logical CPU */ | |
103 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
104 | ||
a355352b GC |
105 | /* representing HT siblings of each logical CPU */ |
106 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
107 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
108 | ||
109 | /* representing HT and core siblings of each logical CPU */ | |
110 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
111 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
112 | ||
113 | /* Per CPU bogomips and other parameters */ | |
114 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
115 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 116 | |
cb3c8b90 GOC |
117 | static atomic_t init_deasserted; |
118 | ||
8aef135c | 119 | |
1d89a7f0 | 120 | /* Set if we find a B stepping CPU */ |
f86c9985 | 121 | static int __cpuinitdata smp_b_stepping; |
1d89a7f0 | 122 | |
7cc3959e GOC |
123 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
124 | ||
125 | /* which logical CPUs are on which nodes */ | |
126 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
127 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
128 | EXPORT_SYMBOL(node_to_cpumask_map); | |
129 | /* which node each logical CPU is on */ | |
130 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
131 | EXPORT_SYMBOL(cpu_to_node_map); | |
132 | ||
133 | /* set up a mapping between cpu and node. */ | |
134 | static void map_cpu_to_node(int cpu, int node) | |
135 | { | |
136 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c2d1cec1 | 137 | cpumask_set_cpu(cpu, &node_to_cpumask_map[node]); |
7cc3959e GOC |
138 | cpu_to_node_map[cpu] = node; |
139 | } | |
140 | ||
141 | /* undo a mapping between cpu and node. */ | |
142 | static void unmap_cpu_to_node(int cpu) | |
143 | { | |
144 | int node; | |
145 | ||
146 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
147 | for (node = 0; node < MAX_NUMNODES; node++) | |
c2d1cec1 | 148 | cpumask_clear_cpu(cpu, &node_to_cpumask_map[node]); |
7cc3959e GOC |
149 | cpu_to_node_map[cpu] = 0; |
150 | } | |
151 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
152 | #define map_cpu_to_node(cpu, node) ({}) | |
153 | #define unmap_cpu_to_node(cpu) ({}) | |
154 | #endif | |
155 | ||
156 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
157 | static int boot_cpu_logical_apicid; |
158 | ||
7cc3959e GOC |
159 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
160 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
161 | ||
a4928cff | 162 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
163 | { |
164 | int cpu = smp_processor_id(); | |
165 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 166 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
167 | |
168 | if (!node_online(node)) | |
169 | node = first_online_node; | |
170 | ||
171 | cpu_2_logical_apicid[cpu] = apicid; | |
172 | map_cpu_to_node(cpu, node); | |
173 | } | |
174 | ||
1481a3dd | 175 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
176 | { |
177 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
178 | unmap_cpu_to_node(cpu); | |
179 | } | |
180 | #else | |
7cc3959e GOC |
181 | #define map_cpu_to_logical_apicid() do {} while (0) |
182 | #endif | |
183 | ||
cb3c8b90 GOC |
184 | /* |
185 | * Report back to the Boot Processor. | |
186 | * Running on AP. | |
187 | */ | |
a4928cff | 188 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
189 | { |
190 | int cpuid, phys_id; | |
191 | unsigned long timeout; | |
192 | ||
193 | /* | |
194 | * If waken up by an INIT in an 82489DX configuration | |
195 | * we may get here before an INIT-deassert IPI reaches | |
196 | * our local APIC. We have to wait for the IPI or we'll | |
197 | * lock up on an APIC access. | |
198 | */ | |
a9659366 IM |
199 | if (apic->wait_for_init_deassert) |
200 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
201 | |
202 | /* | |
203 | * (This works even if the APIC is not enabled.) | |
204 | */ | |
4c9961d5 | 205 | phys_id = read_apic_id(); |
cb3c8b90 | 206 | cpuid = smp_processor_id(); |
c2d1cec1 | 207 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
208 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
209 | phys_id, cpuid); | |
210 | } | |
cfc1b9a6 | 211 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
212 | |
213 | /* | |
214 | * STARTUP IPIs are fragile beasts as they might sometimes | |
215 | * trigger some glue motherboard logic. Complete APIC bus | |
216 | * silence for 1 second, this overestimates the time the | |
217 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
218 | * by a factor of two. This should be enough. | |
219 | */ | |
220 | ||
221 | /* | |
222 | * Waiting 2s total for startup (udelay is not yet working) | |
223 | */ | |
224 | timeout = jiffies + 2*HZ; | |
225 | while (time_before(jiffies, timeout)) { | |
226 | /* | |
227 | * Has the boot CPU finished it's STARTUP sequence? | |
228 | */ | |
c2d1cec1 | 229 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
230 | break; |
231 | cpu_relax(); | |
232 | } | |
233 | ||
234 | if (!time_before(jiffies, timeout)) { | |
235 | panic("%s: CPU%d started up but did not get a callout!\n", | |
236 | __func__, cpuid); | |
237 | } | |
238 | ||
239 | /* | |
240 | * the boot CPU has finished the init stage and is spinning | |
241 | * on callin_map until we finish. We are free to set up this | |
242 | * CPU, first the APIC. (this is probably redundant on most | |
243 | * boards) | |
244 | */ | |
245 | ||
cfc1b9a6 | 246 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
cb3c8b90 GOC |
247 | smp_callin_clear_local_apic(); |
248 | setup_local_APIC(); | |
249 | end_local_APIC_setup(); | |
250 | map_cpu_to_logical_apicid(); | |
251 | ||
e545a614 | 252 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
253 | /* |
254 | * Get our bogomips. | |
255 | * | |
256 | * Need to enable IRQs because it can take longer and then | |
257 | * the NMI watchdog might kill us. | |
258 | */ | |
259 | local_irq_enable(); | |
260 | calibrate_delay(); | |
261 | local_irq_disable(); | |
cfc1b9a6 | 262 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
263 | |
264 | /* | |
265 | * Save our processor parameters | |
266 | */ | |
267 | smp_store_cpu_info(cpuid); | |
268 | ||
269 | /* | |
270 | * Allow the master to continue. | |
271 | */ | |
c2d1cec1 | 272 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
273 | } |
274 | ||
25ddbb18 AK |
275 | static int __cpuinitdata unsafe_smp; |
276 | ||
bbc2ff6a GOC |
277 | /* |
278 | * Activate a secondary processor. | |
279 | */ | |
0ca59dd9 | 280 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
281 | { |
282 | /* | |
283 | * Don't put *anything* before cpu_init(), SMP booting is too | |
284 | * fragile that we want to limit the things done here to the | |
285 | * most necessary things. | |
286 | */ | |
bbc2ff6a | 287 | vmi_bringup(); |
bbc2ff6a GOC |
288 | cpu_init(); |
289 | preempt_disable(); | |
290 | smp_callin(); | |
291 | ||
292 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
293 | barrier(); | |
294 | /* | |
295 | * Check TSC synchronization with the BP: | |
296 | */ | |
297 | check_tsc_sync_target(); | |
298 | ||
299 | if (nmi_watchdog == NMI_IO_APIC) { | |
300 | disable_8259A_irq(0); | |
301 | enable_NMI_through_LVT0(); | |
302 | enable_8259A_irq(0); | |
303 | } | |
304 | ||
61165d7a HD |
305 | #ifdef CONFIG_X86_32 |
306 | while (low_mappings) | |
307 | cpu_relax(); | |
308 | __flush_tlb_all(); | |
309 | #endif | |
310 | ||
bbc2ff6a GOC |
311 | /* This must be done before setting cpu_online_map */ |
312 | set_cpu_sibling_map(raw_smp_processor_id()); | |
313 | wmb(); | |
314 | ||
315 | /* | |
316 | * We need to hold call_lock, so there is no inconsistency | |
317 | * between the time smp_call_function() determines number of | |
318 | * IPI recipients, and the time when the determination is made | |
319 | * for which cpus receive the IPI. Holding this | |
320 | * lock helps us to not include this cpu in a currently in progress | |
321 | * smp_call_function(). | |
d388e5fd EB |
322 | * |
323 | * We need to hold vector_lock so there the set of online cpus | |
324 | * does not change while we are assigning vectors to cpus. Holding | |
325 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 326 | */ |
0cefa5b9 | 327 | ipi_call_lock(); |
d388e5fd EB |
328 | lock_vector_lock(); |
329 | __setup_vector_irq(smp_processor_id()); | |
c2d1cec1 | 330 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 331 | unlock_vector_lock(); |
0cefa5b9 | 332 | ipi_call_unlock(); |
bbc2ff6a GOC |
333 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
334 | ||
0cefa5b9 MS |
335 | /* enable local interrupts */ |
336 | local_irq_enable(); | |
337 | ||
bbc2ff6a GOC |
338 | setup_secondary_clock(); |
339 | ||
340 | wmb(); | |
341 | cpu_idle(); | |
342 | } | |
343 | ||
1d89a7f0 GOC |
344 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
345 | { | |
1d89a7f0 GOC |
346 | /* |
347 | * Mask B, Pentium, but not Pentium MMX | |
348 | */ | |
349 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
350 | c->x86 == 5 && | |
351 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
352 | c->x86_model <= 3) | |
353 | /* | |
354 | * Remember we have B step Pentia with bugs | |
355 | */ | |
356 | smp_b_stepping = 1; | |
357 | ||
358 | /* | |
359 | * Certain Athlons might work (for various values of 'work') in SMP | |
360 | * but they are not certified as MP capable. | |
361 | */ | |
362 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
363 | ||
364 | if (num_possible_cpus() == 1) | |
365 | goto valid_k7; | |
366 | ||
367 | /* Athlon 660/661 is valid. */ | |
368 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
369 | (c->x86_mask == 1))) | |
370 | goto valid_k7; | |
371 | ||
372 | /* Duron 670 is valid */ | |
373 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
374 | goto valid_k7; | |
375 | ||
376 | /* | |
377 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
378 | * bit. It's worth noting that the A5 stepping (662) of some | |
379 | * Athlon XP's have the MP bit set. | |
380 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
381 | * more. | |
382 | */ | |
383 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
384 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
385 | (c->x86_model > 7)) | |
386 | if (cpu_has_mp) | |
387 | goto valid_k7; | |
388 | ||
389 | /* If we get here, not a certified SMP capable AMD system. */ | |
25ddbb18 | 390 | unsafe_smp = 1; |
1d89a7f0 GOC |
391 | } |
392 | ||
393 | valid_k7: | |
394 | ; | |
1d89a7f0 GOC |
395 | } |
396 | ||
a4928cff | 397 | static void __cpuinit smp_checks(void) |
693d4b8a GOC |
398 | { |
399 | if (smp_b_stepping) | |
400 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
401 | "with B stepping processors.\n"); | |
402 | ||
403 | /* | |
404 | * Don't taint if we are running SMP kernel on a single non-MP | |
405 | * approved Athlon | |
406 | */ | |
25ddbb18 AK |
407 | if (unsafe_smp && num_online_cpus() > 1) { |
408 | printk(KERN_INFO "WARNING: This combination of AMD" | |
409 | "processors is not suitable for SMP.\n"); | |
410 | add_taint(TAINT_UNSAFE_SMP); | |
693d4b8a GOC |
411 | } |
412 | } | |
413 | ||
1d89a7f0 GOC |
414 | /* |
415 | * The bootstrap kernel entry code has set these up. Save them for | |
416 | * a given CPU | |
417 | */ | |
418 | ||
419 | void __cpuinit smp_store_cpu_info(int id) | |
420 | { | |
421 | struct cpuinfo_x86 *c = &cpu_data(id); | |
422 | ||
423 | *c = boot_cpu_data; | |
424 | c->cpu_index = id; | |
425 | if (id != 0) | |
426 | identify_secondary_cpu(c); | |
427 | smp_apply_quirks(c); | |
428 | } | |
429 | ||
430 | ||
768d9505 GC |
431 | void __cpuinit set_cpu_sibling_map(int cpu) |
432 | { | |
433 | int i; | |
434 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
435 | ||
c2d1cec1 | 436 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
437 | |
438 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
439 | for_each_cpu(i, cpu_sibling_setup_mask) { |
440 | struct cpuinfo_x86 *o = &cpu_data(i); | |
441 | ||
442 | if (c->phys_proc_id == o->phys_proc_id && | |
443 | c->cpu_core_id == o->cpu_core_id) { | |
444 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
445 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
446 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
447 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
448 | cpumask_set_cpu(i, &c->llc_shared_map); | |
449 | cpumask_set_cpu(cpu, &o->llc_shared_map); | |
768d9505 GC |
450 | } |
451 | } | |
452 | } else { | |
c2d1cec1 | 453 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
454 | } |
455 | ||
c2d1cec1 | 456 | cpumask_set_cpu(cpu, &c->llc_shared_map); |
768d9505 GC |
457 | |
458 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 459 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
460 | c->booted_cores = 1; |
461 | return; | |
462 | } | |
463 | ||
c2d1cec1 | 464 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
465 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
466 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
c2d1cec1 MT |
467 | cpumask_set_cpu(i, &c->llc_shared_map); |
468 | cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map); | |
768d9505 GC |
469 | } |
470 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
471 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
472 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
473 | /* |
474 | * Does this new cpu bringup a new core? | |
475 | */ | |
c2d1cec1 | 476 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
477 | /* |
478 | * for each core in package, increment | |
479 | * the booted_cores for this new cpu | |
480 | */ | |
c2d1cec1 | 481 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
482 | c->booted_cores++; |
483 | /* | |
484 | * increment the core count for all | |
485 | * the other cpus in this package | |
486 | */ | |
487 | if (i != cpu) | |
488 | cpu_data(i).booted_cores++; | |
489 | } else if (i != cpu && !c->booted_cores) | |
490 | c->booted_cores = cpu_data(i).booted_cores; | |
491 | } | |
492 | } | |
493 | } | |
494 | ||
70708a18 | 495 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 496 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
497 | { |
498 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
499 | /* | |
500 | * For perf, we return last level cache shared map. | |
501 | * And for power savings, we return cpu_core_map | |
502 | */ | |
503 | if (sched_mc_power_savings || sched_smt_power_savings) | |
c2d1cec1 | 504 | return cpu_core_mask(cpu); |
70708a18 | 505 | else |
030bb203 RR |
506 | return &c->llc_shared_map; |
507 | } | |
508 | ||
509 | cpumask_t cpu_coregroup_map(int cpu) | |
510 | { | |
511 | return *cpu_coregroup_mask(cpu); | |
70708a18 GC |
512 | } |
513 | ||
a4928cff | 514 | static void impress_friends(void) |
904541e2 GOC |
515 | { |
516 | int cpu; | |
517 | unsigned long bogosum = 0; | |
518 | /* | |
519 | * Allow the user to impress friends. | |
520 | */ | |
cfc1b9a6 | 521 | pr_debug("Before bogomips.\n"); |
904541e2 | 522 | for_each_possible_cpu(cpu) |
c2d1cec1 | 523 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
524 | bogosum += cpu_data(cpu).loops_per_jiffy; |
525 | printk(KERN_INFO | |
526 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 527 | num_online_cpus(), |
904541e2 GOC |
528 | bogosum/(500000/HZ), |
529 | (bogosum/(5000/HZ))%100); | |
530 | ||
cfc1b9a6 | 531 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
532 | } |
533 | ||
569712b2 | 534 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
535 | { |
536 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
537 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
538 | int timeout; | |
539 | u32 status; | |
540 | ||
823b259b | 541 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
542 | |
543 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 544 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
545 | |
546 | /* | |
547 | * Wait for idle. | |
548 | */ | |
549 | status = safe_apic_wait_icr_idle(); | |
550 | if (status) | |
551 | printk(KERN_CONT | |
552 | "a previous APIC delivery may have failed\n"); | |
553 | ||
1b374e4d | 554 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
555 | |
556 | timeout = 0; | |
557 | do { | |
558 | udelay(100); | |
559 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
560 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
561 | ||
562 | switch (status) { | |
563 | case APIC_ICR_RR_VALID: | |
564 | status = apic_read(APIC_RRR); | |
565 | printk(KERN_CONT "%08x\n", status); | |
566 | break; | |
567 | default: | |
568 | printk(KERN_CONT "failed\n"); | |
569 | } | |
570 | } | |
571 | } | |
572 | ||
cb3c8b90 GOC |
573 | /* |
574 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
575 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
576 | * won't ... remember to clear down the APIC, etc later. | |
577 | */ | |
569712b2 YL |
578 | int __devinit |
579 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) | |
cb3c8b90 GOC |
580 | { |
581 | unsigned long send_status, accept_status = 0; | |
582 | int maxlvt; | |
583 | ||
584 | /* Target chip */ | |
cb3c8b90 GOC |
585 | /* Boot on the stack */ |
586 | /* Kick the second */ | |
bdb1a9b6 | 587 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 588 | |
cfc1b9a6 | 589 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
590 | send_status = safe_apic_wait_icr_idle(); |
591 | ||
592 | /* | |
593 | * Give the other CPU some time to accept the IPI. | |
594 | */ | |
595 | udelay(200); | |
569712b2 | 596 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
597 | maxlvt = lapic_get_maxlvt(); |
598 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
599 | apic_write(APIC_ESR, 0); | |
600 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
601 | } | |
cfc1b9a6 | 602 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
603 | |
604 | if (send_status) | |
605 | printk(KERN_ERR "APIC never delivered???\n"); | |
606 | if (accept_status) | |
607 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
608 | ||
609 | return (send_status | accept_status); | |
610 | } | |
cb3c8b90 | 611 | |
54ac14a8 | 612 | int __devinit |
569712b2 | 613 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
614 | { |
615 | unsigned long send_status, accept_status = 0; | |
616 | int maxlvt, num_starts, j; | |
617 | ||
34d05591 JS |
618 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { |
619 | send_status = uv_wakeup_secondary(phys_apicid, start_eip); | |
620 | atomic_set(&init_deasserted, 1); | |
621 | return send_status; | |
622 | } | |
623 | ||
593f4a78 MR |
624 | maxlvt = lapic_get_maxlvt(); |
625 | ||
cb3c8b90 GOC |
626 | /* |
627 | * Be paranoid about clearing APIC errors. | |
628 | */ | |
629 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
630 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
631 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
632 | apic_read(APIC_ESR); |
633 | } | |
634 | ||
cfc1b9a6 | 635 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
636 | |
637 | /* | |
638 | * Turn INIT on target chip | |
639 | */ | |
cb3c8b90 GOC |
640 | /* |
641 | * Send IPI | |
642 | */ | |
1b374e4d SS |
643 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
644 | phys_apicid); | |
cb3c8b90 | 645 | |
cfc1b9a6 | 646 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
647 | send_status = safe_apic_wait_icr_idle(); |
648 | ||
649 | mdelay(10); | |
650 | ||
cfc1b9a6 | 651 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
652 | |
653 | /* Target chip */ | |
cb3c8b90 | 654 | /* Send IPI */ |
1b374e4d | 655 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 656 | |
cfc1b9a6 | 657 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
658 | send_status = safe_apic_wait_icr_idle(); |
659 | ||
660 | mb(); | |
661 | atomic_set(&init_deasserted, 1); | |
662 | ||
663 | /* | |
664 | * Should we send STARTUP IPIs ? | |
665 | * | |
666 | * Determine this based on the APIC version. | |
667 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
668 | */ | |
669 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
670 | num_starts = 2; | |
671 | else | |
672 | num_starts = 0; | |
673 | ||
674 | /* | |
675 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
676 | * target processor state. | |
677 | */ | |
678 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 679 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
680 | |
681 | /* | |
682 | * Run STARTUP IPI loop. | |
683 | */ | |
cfc1b9a6 | 684 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 685 | |
cb3c8b90 | 686 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 687 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
688 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
689 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 690 | apic_read(APIC_ESR); |
cfc1b9a6 | 691 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
692 | |
693 | /* | |
694 | * STARTUP IPI | |
695 | */ | |
696 | ||
697 | /* Target chip */ | |
cb3c8b90 GOC |
698 | /* Boot on the stack */ |
699 | /* Kick the second */ | |
1b374e4d SS |
700 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
701 | phys_apicid); | |
cb3c8b90 GOC |
702 | |
703 | /* | |
704 | * Give the other CPU some time to accept the IPI. | |
705 | */ | |
706 | udelay(300); | |
707 | ||
cfc1b9a6 | 708 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 709 | |
cfc1b9a6 | 710 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
711 | send_status = safe_apic_wait_icr_idle(); |
712 | ||
713 | /* | |
714 | * Give the other CPU some time to accept the IPI. | |
715 | */ | |
716 | udelay(200); | |
593f4a78 | 717 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 718 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
719 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
720 | if (send_status || accept_status) | |
721 | break; | |
722 | } | |
cfc1b9a6 | 723 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
724 | |
725 | if (send_status) | |
726 | printk(KERN_ERR "APIC never delivered???\n"); | |
727 | if (accept_status) | |
728 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
729 | ||
730 | return (send_status | accept_status); | |
731 | } | |
cb3c8b90 GOC |
732 | |
733 | struct create_idle { | |
734 | struct work_struct work; | |
735 | struct task_struct *idle; | |
736 | struct completion done; | |
737 | int cpu; | |
738 | }; | |
739 | ||
740 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
741 | { | |
742 | struct create_idle *c_idle = | |
743 | container_of(work, struct create_idle, work); | |
744 | ||
745 | c_idle->idle = fork_idle(c_idle->cpu); | |
746 | complete(&c_idle->done); | |
747 | } | |
748 | ||
749 | static int __cpuinit do_boot_cpu(int apicid, int cpu) | |
750 | /* | |
751 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
752 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
753 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
754 | */ | |
755 | { | |
756 | unsigned long boot_error = 0; | |
757 | int timeout; | |
758 | unsigned long start_ip; | |
759 | unsigned short nmi_high = 0, nmi_low = 0; | |
760 | struct create_idle c_idle = { | |
761 | .cpu = cpu, | |
762 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
763 | }; | |
764 | INIT_WORK(&c_idle.work, do_fork_idle); | |
cb3c8b90 | 765 | |
cb3c8b90 GOC |
766 | alternatives_smp_switch(1); |
767 | ||
768 | c_idle.idle = get_idle_for_cpu(cpu); | |
769 | ||
770 | /* | |
771 | * We can't use kernel_thread since we must avoid to | |
772 | * reschedule the child. | |
773 | */ | |
774 | if (c_idle.idle) { | |
775 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
776 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
777 | init_idle(c_idle.idle, cpu); | |
778 | goto do_rest; | |
779 | } | |
780 | ||
781 | if (!keventd_up() || current_is_keventd()) | |
782 | c_idle.work.func(&c_idle.work); | |
783 | else { | |
784 | schedule_work(&c_idle.work); | |
785 | wait_for_completion(&c_idle.done); | |
786 | } | |
787 | ||
788 | if (IS_ERR(c_idle.idle)) { | |
789 | printk("failed fork for CPU %d\n", cpu); | |
790 | return PTR_ERR(c_idle.idle); | |
791 | } | |
792 | ||
793 | set_idle_for_cpu(cpu, c_idle.idle); | |
794 | do_rest: | |
cb3c8b90 | 795 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 796 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 797 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
798 | irq_ctx_init(cpu); |
799 | #else | |
cb3c8b90 | 800 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 801 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
802 | per_cpu(kernel_stack, cpu) = |
803 | (unsigned long)task_stack_page(c_idle.idle) - | |
804 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 805 | #endif |
a939098a | 806 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 807 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 808 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
809 | |
810 | /* start_ip had better be page-aligned! */ | |
811 | start_ip = setup_trampoline(); | |
812 | ||
813 | /* So we see what's up */ | |
823b259b | 814 | printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", |
cb3c8b90 GOC |
815 | cpu, apicid, start_ip); |
816 | ||
817 | /* | |
818 | * This grunge runs the startup process for | |
819 | * the targeted processor. | |
820 | */ | |
821 | ||
822 | atomic_set(&init_deasserted, 0); | |
823 | ||
34d05591 | 824 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 825 | |
cfc1b9a6 | 826 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 827 | |
34d05591 JS |
828 | store_NMI_vector(&nmi_high, &nmi_low); |
829 | ||
830 | smpboot_setup_warm_reset_vector(start_ip); | |
831 | /* | |
832 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
833 | */ |
834 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
835 | apic_write(APIC_ESR, 0); | |
836 | apic_read(APIC_ESR); | |
837 | } | |
34d05591 | 838 | } |
cb3c8b90 | 839 | |
cb3c8b90 GOC |
840 | /* |
841 | * Starting actual IPI sequence... | |
842 | */ | |
843 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
844 | ||
845 | if (!boot_error) { | |
846 | /* | |
847 | * allow APs to start initializing. | |
848 | */ | |
cfc1b9a6 | 849 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 850 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 851 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
852 | |
853 | /* | |
854 | * Wait 5s total for a response | |
855 | */ | |
856 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 857 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
858 | break; /* It has booted */ |
859 | udelay(100); | |
860 | } | |
861 | ||
c2d1cec1 | 862 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cb3c8b90 | 863 | /* number CPUs logically, starting from 1 (BSP is 0) */ |
cfc1b9a6 | 864 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
865 | printk(KERN_INFO "CPU%d: ", cpu); |
866 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 867 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
868 | } else { |
869 | boot_error = 1; | |
870 | if (*((volatile unsigned char *)trampoline_base) | |
871 | == 0xA5) | |
872 | /* trampoline started but...? */ | |
873 | printk(KERN_ERR "Stuck ??\n"); | |
874 | else | |
875 | /* trampoline code not run */ | |
876 | printk(KERN_ERR "Not responding.\n"); | |
34d05591 JS |
877 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) |
878 | inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
879 | } |
880 | } | |
1a51e3a0 | 881 | |
cb3c8b90 GOC |
882 | if (boot_error) { |
883 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 884 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
885 | |
886 | /* was set by do_boot_cpu() */ | |
887 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
888 | ||
889 | /* was set by cpu_init() */ | |
890 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
891 | ||
892 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
893 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
894 | } | |
895 | ||
896 | /* mark "stuck" area as not stuck */ | |
897 | *((volatile unsigned long *)trampoline_base) = 0; | |
898 | ||
63d38198 AK |
899 | /* |
900 | * Cleanup possible dangling ends... | |
901 | */ | |
902 | smpboot_restore_warm_reset_vector(); | |
903 | ||
cb3c8b90 GOC |
904 | return boot_error; |
905 | } | |
906 | ||
a21769a4 IM |
907 | #ifdef CONFIG_X86_64 |
908 | int default_cpu_present_to_apicid(int mps_cpu) | |
909 | { | |
910 | return __default_cpu_present_to_apicid(mps_cpu); | |
911 | } | |
a27a6210 IM |
912 | |
913 | int default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
914 | { | |
915 | return __default_check_phys_apicid_present(boot_cpu_physical_apicid); | |
916 | } | |
a21769a4 IM |
917 | #endif |
918 | ||
cb3c8b90 GOC |
919 | int __cpuinit native_cpu_up(unsigned int cpu) |
920 | { | |
a21769a4 | 921 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
922 | unsigned long flags; |
923 | int err; | |
924 | ||
925 | WARN_ON(irqs_disabled()); | |
926 | ||
cfc1b9a6 | 927 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
928 | |
929 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
930 | !physid_isset(apicid, phys_cpu_present_map)) { | |
931 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
932 | return -EINVAL; | |
933 | } | |
934 | ||
935 | /* | |
936 | * Already booted CPU? | |
937 | */ | |
c2d1cec1 | 938 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 939 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
940 | return -ENOSYS; |
941 | } | |
942 | ||
943 | /* | |
944 | * Save current MTRR state in case it was changed since early boot | |
945 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
946 | */ | |
947 | mtrr_save_state(); | |
948 | ||
949 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
950 | ||
951 | #ifdef CONFIG_X86_32 | |
952 | /* init low mem mapping */ | |
68db065c | 953 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 954 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 955 | flush_tlb_all(); |
61165d7a | 956 | low_mappings = 1; |
cb3c8b90 GOC |
957 | |
958 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
959 | |
960 | zap_low_mappings(); | |
961 | low_mappings = 0; | |
962 | #else | |
963 | err = do_boot_cpu(apicid, cpu); | |
964 | #endif | |
965 | if (err) { | |
cfc1b9a6 | 966 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 967 | return -EIO; |
cb3c8b90 GOC |
968 | } |
969 | ||
970 | /* | |
971 | * Check TSC synchronization with the AP (keep irqs disabled | |
972 | * while doing so): | |
973 | */ | |
974 | local_irq_save(flags); | |
975 | check_tsc_sync_source(cpu); | |
976 | local_irq_restore(flags); | |
977 | ||
7c04e64a | 978 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
979 | cpu_relax(); |
980 | touch_nmi_watchdog(); | |
981 | } | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
8aef135c GOC |
986 | /* |
987 | * Fall back to non SMP mode after errors. | |
988 | * | |
989 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
990 | */ | |
991 | static __init void disable_smp(void) | |
992 | { | |
c2d1cec1 MT |
993 | /* use the read/write pointers to the present and possible maps */ |
994 | cpumask_copy(&cpu_present_map, cpumask_of(0)); | |
995 | cpumask_copy(&cpu_possible_map, cpumask_of(0)); | |
8aef135c | 996 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 997 | |
8aef135c | 998 | if (smp_found_config) |
b6df1b8b | 999 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1000 | else |
b6df1b8b | 1001 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 1002 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
1003 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
1004 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
1005 | } |
1006 | ||
1007 | /* | |
1008 | * Various sanity checks. | |
1009 | */ | |
1010 | static int __init smp_sanity_check(unsigned max_cpus) | |
1011 | { | |
ac23d4ee | 1012 | preempt_disable(); |
a58f03b0 YL |
1013 | |
1014 | #if defined(CONFIG_X86_PC) && defined(CONFIG_X86_32) | |
1015 | if (def_to_bigsmp && nr_cpu_ids > 8) { | |
1016 | unsigned int cpu; | |
1017 | unsigned nr; | |
1018 | ||
1019 | printk(KERN_WARNING | |
1020 | "More than 8 CPUs detected - skipping them.\n" | |
1021 | "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n"); | |
1022 | ||
1023 | nr = 0; | |
1024 | for_each_present_cpu(cpu) { | |
1025 | if (nr >= 8) | |
c2d1cec1 | 1026 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1027 | nr++; |
1028 | } | |
1029 | ||
1030 | nr = 0; | |
1031 | for_each_possible_cpu(cpu) { | |
1032 | if (nr >= 8) | |
c2d1cec1 | 1033 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1034 | nr++; |
1035 | } | |
1036 | ||
1037 | nr_cpu_ids = 8; | |
1038 | } | |
1039 | #endif | |
1040 | ||
8aef135c | 1041 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
1042 | printk(KERN_WARNING |
1043 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1044 | hard_smp_processor_id()); | |
1045 | ||
8aef135c GOC |
1046 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1047 | } | |
1048 | ||
1049 | /* | |
1050 | * If we couldn't find an SMP configuration at boot time, | |
1051 | * get out of here now! | |
1052 | */ | |
1053 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1054 | preempt_enable(); |
8aef135c GOC |
1055 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1056 | disable_smp(); | |
1057 | if (APIC_init_uniprocessor()) | |
1058 | printk(KERN_NOTICE "Local APIC not detected." | |
1059 | " Using dummy APIC emulation.\n"); | |
1060 | return -1; | |
1061 | } | |
1062 | ||
1063 | /* | |
1064 | * Should not be necessary because the MP table should list the boot | |
1065 | * CPU too, but we do it for the sake of robustness anyway. | |
1066 | */ | |
a27a6210 | 1067 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
1068 | printk(KERN_NOTICE |
1069 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1070 | boot_cpu_physical_apicid); | |
1071 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1072 | } | |
ac23d4ee | 1073 | preempt_enable(); |
8aef135c GOC |
1074 | |
1075 | /* | |
1076 | * If we couldn't find a local APIC, then get out of here now! | |
1077 | */ | |
1078 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1079 | !cpu_has_apic) { | |
1080 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1081 | boot_cpu_physical_apicid); | |
1082 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1083 | "(tell your hw vendor)\n"); | |
1084 | smpboot_clear_io_apic(); | |
f1182638 | 1085 | disable_ioapic_setup(); |
8aef135c GOC |
1086 | return -1; |
1087 | } | |
1088 | ||
1089 | verify_local_APIC(); | |
1090 | ||
1091 | /* | |
1092 | * If SMP should be disabled, then really disable it! | |
1093 | */ | |
1094 | if (!max_cpus) { | |
73d08e63 | 1095 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1096 | smpboot_clear_io_apic(); |
d54db1ac MR |
1097 | |
1098 | localise_nmi_watchdog(); | |
1099 | ||
e90955c2 | 1100 | connect_bsp_APIC(); |
e90955c2 JB |
1101 | setup_local_APIC(); |
1102 | end_local_APIC_setup(); | |
8aef135c GOC |
1103 | return -1; |
1104 | } | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static void __init smp_cpu_index_default(void) | |
1110 | { | |
1111 | int i; | |
1112 | struct cpuinfo_x86 *c; | |
1113 | ||
7c04e64a | 1114 | for_each_possible_cpu(i) { |
8aef135c GOC |
1115 | c = &cpu_data(i); |
1116 | /* mark all to hotplug */ | |
9628937d | 1117 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1118 | } |
1119 | } | |
1120 | ||
1121 | /* | |
1122 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1123 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1124 | */ | |
1125 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1126 | { | |
deef3250 | 1127 | preempt_disable(); |
8aef135c GOC |
1128 | smp_cpu_index_default(); |
1129 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1130 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1131 | mb(); |
1132 | /* | |
1133 | * Setup boot CPU information | |
1134 | */ | |
1135 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1136 | #ifdef CONFIG_X86_32 |
8aef135c | 1137 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1138 | #endif |
8aef135c GOC |
1139 | current_thread_info()->cpu = 0; /* needed? */ |
1140 | set_cpu_sibling_map(0); | |
1141 | ||
6e1cb38a SS |
1142 | #ifdef CONFIG_X86_64 |
1143 | enable_IR_x2apic(); | |
72ce0165 | 1144 | default_setup_apic_routing(); |
6e1cb38a SS |
1145 | #endif |
1146 | ||
8aef135c GOC |
1147 | if (smp_sanity_check(max_cpus) < 0) { |
1148 | printk(KERN_INFO "SMP disabled\n"); | |
1149 | disable_smp(); | |
deef3250 | 1150 | goto out; |
8aef135c GOC |
1151 | } |
1152 | ||
ac23d4ee | 1153 | preempt_disable(); |
4c9961d5 | 1154 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1155 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1156 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1157 | /* Or can we switch back to PIC here? */ |
1158 | } | |
ac23d4ee | 1159 | preempt_enable(); |
8aef135c | 1160 | |
8aef135c | 1161 | connect_bsp_APIC(); |
b5841765 | 1162 | |
8aef135c GOC |
1163 | /* |
1164 | * Switch from PIC to APIC mode. | |
1165 | */ | |
1166 | setup_local_APIC(); | |
1167 | ||
1168 | #ifdef CONFIG_X86_64 | |
1169 | /* | |
1170 | * Enable IO APIC before setting up error vector | |
1171 | */ | |
1172 | if (!skip_ioapic_setup && nr_ioapics) | |
1173 | enable_IO_APIC(); | |
1174 | #endif | |
1175 | end_local_APIC_setup(); | |
1176 | ||
1177 | map_cpu_to_logical_apicid(); | |
1178 | ||
d83093b5 IM |
1179 | if (apic->setup_portio_remap) |
1180 | apic->setup_portio_remap(); | |
8aef135c GOC |
1181 | |
1182 | smpboot_setup_io_apic(); | |
1183 | /* | |
1184 | * Set up local APIC timer on boot CPU. | |
1185 | */ | |
1186 | ||
1187 | printk(KERN_INFO "CPU%d: ", 0); | |
1188 | print_cpu_info(&cpu_data(0)); | |
1189 | setup_boot_clock(); | |
c4bd1fda MS |
1190 | |
1191 | if (is_uv_system()) | |
1192 | uv_system_init(); | |
deef3250 IM |
1193 | out: |
1194 | preempt_enable(); | |
8aef135c | 1195 | } |
a8db8453 GOC |
1196 | /* |
1197 | * Early setup to make printk work. | |
1198 | */ | |
1199 | void __init native_smp_prepare_boot_cpu(void) | |
1200 | { | |
1201 | int me = smp_processor_id(); | |
a939098a | 1202 | switch_to_new_gdt(); |
c2d1cec1 MT |
1203 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1204 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1205 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1206 | } | |
1207 | ||
83f7eb9c GOC |
1208 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1209 | { | |
cfc1b9a6 | 1210 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1211 | |
1212 | impress_friends(); | |
1213 | smp_checks(); | |
1214 | #ifdef CONFIG_X86_IO_APIC | |
1215 | setup_ioapic_dest(); | |
1216 | #endif | |
1217 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1218 | } |
1219 | ||
3b11ce7f MT |
1220 | static int __initdata setup_possible_cpus = -1; |
1221 | static int __init _setup_possible_cpus(char *str) | |
1222 | { | |
1223 | get_option(&str, &setup_possible_cpus); | |
1224 | return 0; | |
1225 | } | |
1226 | early_param("possible_cpus", _setup_possible_cpus); | |
1227 | ||
1228 | ||
68a1c3f8 GC |
1229 | /* |
1230 | * cpu_possible_map should be static, it cannot change as cpu's | |
1231 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1232 | * are allocated by some modules at init time, and dont expect to | |
1233 | * do this dynamically on cpu arrival/departure. | |
1234 | * cpu_present_map on the other hand can change dynamically. | |
1235 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1236 | * behaviour, which is cpu_possible == cpu_present. | |
1237 | * - Ashok Raj | |
1238 | * | |
1239 | * Three ways to find out the number of additional hotplug CPUs: | |
1240 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1241 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1242 | * - Otherwise don't reserve additional CPUs. |
1243 | * We do this because additional CPUs waste a lot of memory. | |
1244 | * -AK | |
1245 | */ | |
1246 | __init void prefill_possible_map(void) | |
1247 | { | |
cb48bb59 | 1248 | int i, possible; |
68a1c3f8 | 1249 | |
329513a3 YL |
1250 | /* no processor from mptable or madt */ |
1251 | if (!num_processors) | |
1252 | num_processors = 1; | |
1253 | ||
3b11ce7f MT |
1254 | if (setup_possible_cpus == -1) |
1255 | possible = num_processors + disabled_cpus; | |
1256 | else | |
1257 | possible = setup_possible_cpus; | |
1258 | ||
730cf272 MT |
1259 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1260 | ||
3b11ce7f MT |
1261 | if (possible > CONFIG_NR_CPUS) { |
1262 | printk(KERN_WARNING | |
1263 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
1264 | possible, CONFIG_NR_CPUS); | |
1265 | possible = CONFIG_NR_CPUS; | |
1266 | } | |
68a1c3f8 GC |
1267 | |
1268 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1269 | possible, max_t(int, possible - num_processors, 0)); | |
1270 | ||
1271 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1272 | set_cpu_possible(i, true); |
3461b0af MT |
1273 | |
1274 | nr_cpu_ids = possible; | |
68a1c3f8 | 1275 | } |
69c18c15 | 1276 | |
14adf855 CE |
1277 | #ifdef CONFIG_HOTPLUG_CPU |
1278 | ||
1279 | static void remove_siblinginfo(int cpu) | |
1280 | { | |
1281 | int sibling; | |
1282 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1283 | ||
c2d1cec1 MT |
1284 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1285 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1286 | /*/ |
1287 | * last thread sibling in this cpu core going down | |
1288 | */ | |
c2d1cec1 | 1289 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1290 | cpu_data(sibling).booted_cores--; |
1291 | } | |
1292 | ||
c2d1cec1 MT |
1293 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1294 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1295 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1296 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1297 | c->phys_proc_id = 0; |
1298 | c->cpu_core_id = 0; | |
c2d1cec1 | 1299 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1300 | } |
1301 | ||
69c18c15 GC |
1302 | static void __ref remove_cpu_from_maps(int cpu) |
1303 | { | |
c2d1cec1 MT |
1304 | set_cpu_online(cpu, false); |
1305 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1306 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1307 | /* was set by cpu_init() */ |
c2d1cec1 | 1308 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1309 | numa_remove_cpu(cpu); |
69c18c15 GC |
1310 | } |
1311 | ||
8227dce7 | 1312 | void cpu_disable_common(void) |
69c18c15 GC |
1313 | { |
1314 | int cpu = smp_processor_id(); | |
69c18c15 GC |
1315 | /* |
1316 | * HACK: | |
1317 | * Allow any queued timer interrupts to get serviced | |
1318 | * This is only a temporary solution until we cleanup | |
1319 | * fixup_irqs as we do for IA64. | |
1320 | */ | |
1321 | local_irq_enable(); | |
1322 | mdelay(1); | |
1323 | ||
1324 | local_irq_disable(); | |
1325 | remove_siblinginfo(cpu); | |
1326 | ||
1327 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1328 | lock_vector_lock(); |
69c18c15 | 1329 | remove_cpu_from_maps(cpu); |
d388e5fd | 1330 | unlock_vector_lock(); |
d7b381bb | 1331 | fixup_irqs(); |
8227dce7 AN |
1332 | } |
1333 | ||
1334 | int native_cpu_disable(void) | |
1335 | { | |
1336 | int cpu = smp_processor_id(); | |
1337 | ||
1338 | /* | |
1339 | * Perhaps use cpufreq to drop frequency, but that could go | |
1340 | * into generic code. | |
1341 | * | |
1342 | * We won't take down the boot processor on i386 due to some | |
1343 | * interrupts only being able to be serviced by the BSP. | |
1344 | * Especially so if we're not using an IOAPIC -zwane | |
1345 | */ | |
1346 | if (cpu == 0) | |
1347 | return -EBUSY; | |
1348 | ||
1349 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1350 | stop_apic_nmi_watchdog(NULL); | |
1351 | clear_local_APIC(); | |
1352 | ||
1353 | cpu_disable_common(); | |
69c18c15 GC |
1354 | return 0; |
1355 | } | |
1356 | ||
93be71b6 | 1357 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1358 | { |
1359 | /* We don't do anything here: idle task is faking death itself. */ | |
1360 | unsigned int i; | |
1361 | ||
1362 | for (i = 0; i < 10; i++) { | |
1363 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1364 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1365 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1366 | if (1 == num_online_cpus()) | |
1367 | alternatives_smp_switch(0); | |
1368 | return; | |
1369 | } | |
1370 | msleep(100); | |
1371 | } | |
1372 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1373 | } | |
a21f5d88 AN |
1374 | |
1375 | void play_dead_common(void) | |
1376 | { | |
1377 | idle_task_exit(); | |
1378 | reset_lazy_tlbstate(); | |
1379 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1380 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1381 | |
1382 | mb(); | |
1383 | /* Ack it */ | |
1384 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1385 | ||
1386 | /* | |
1387 | * With physical CPU hotplug, we should halt the cpu | |
1388 | */ | |
1389 | local_irq_disable(); | |
1390 | } | |
1391 | ||
1392 | void native_play_dead(void) | |
1393 | { | |
1394 | play_dead_common(); | |
1395 | wbinvd_halt(); | |
1396 | } | |
1397 | ||
69c18c15 | 1398 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1399 | int native_cpu_disable(void) |
69c18c15 GC |
1400 | { |
1401 | return -ENOSYS; | |
1402 | } | |
1403 | ||
93be71b6 | 1404 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1405 | { |
1406 | /* We said "no" in __cpu_disable */ | |
1407 | BUG(); | |
1408 | } | |
a21f5d88 AN |
1409 | |
1410 | void native_play_dead(void) | |
1411 | { | |
1412 | BUG(); | |
1413 | } | |
1414 | ||
68a1c3f8 | 1415 | #endif |