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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
186f4360 | 46 | #include <linux/export.h> |
70708a18 | 47 | #include <linux/sched.h> |
105ab3d8 | 48 | #include <linux/sched/topology.h> |
69c18c15 | 49 | #include <linux/percpu.h> |
91718e8d | 50 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
51 | #include <linux/err.h> |
52 | #include <linux/nmi.h> | |
69575d38 | 53 | #include <linux/tboot.h> |
35f720c5 | 54 | #include <linux/stackprotector.h> |
5a0e3ad6 | 55 | #include <linux/gfp.h> |
1a022e3f | 56 | #include <linux/cpuidle.h> |
69c18c15 | 57 | |
8aef135c | 58 | #include <asm/acpi.h> |
cb3c8b90 | 59 | #include <asm/desc.h> |
69c18c15 GC |
60 | #include <asm/nmi.h> |
61 | #include <asm/irq.h> | |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> |
569712b2 | 72 | #include <asm/setup.h> |
bdbcdd48 | 73 | #include <asm/uv/uv.h> |
cb3c8b90 | 74 | #include <linux/mc146818rtc.h> |
b81bb373 | 75 | #include <asm/i8259.h> |
48927bbb | 76 | #include <asm/realmode.h> |
646e29a1 | 77 | #include <asm/misc.h> |
48927bbb | 78 | |
a355352b GC |
79 | /* Number of siblings per CPU package */ |
80 | int smp_num_siblings = 1; | |
81 | EXPORT_SYMBOL(smp_num_siblings); | |
82 | ||
83 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 84 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 85 | |
a355352b | 86 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 87 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
89 | ||
90 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
93 | ||
0816b0f0 | 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 95 | |
a355352b | 96 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 97 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 98 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 99 | |
1f12e32f TG |
100 | /* Logical package management. We might want to allocate that dynamically */ |
101 | static int *physical_to_logical_pkg __read_mostly; | |
102 | static unsigned long *physical_package_map __read_mostly;; | |
1f12e32f TG |
103 | static unsigned int max_physical_pkg_id __read_mostly; |
104 | unsigned int __max_logical_packages __read_mostly; | |
105 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 106 | static unsigned int logical_packages __read_mostly; |
1f12e32f | 107 | |
70b8301f AK |
108 | /* Maximum number of SMT threads on any online core */ |
109 | int __max_smt_threads __read_mostly; | |
110 | ||
7d25127c TC |
111 | /* Flag to indicate if a complete sched domain rebuild is required */ |
112 | bool x86_topology_update; | |
113 | ||
114 | int arch_update_cpu_topology(void) | |
115 | { | |
116 | int retval = x86_topology_update; | |
117 | ||
118 | x86_topology_update = false; | |
119 | return retval; | |
120 | } | |
121 | ||
f77aa308 TG |
122 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&rtc_lock, flags); | |
127 | CMOS_WRITE(0xa, 0xf); | |
128 | spin_unlock_irqrestore(&rtc_lock, flags); | |
129 | local_flush_tlb(); | |
130 | pr_debug("1.\n"); | |
131 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
132 | start_eip >> 4; | |
133 | pr_debug("2.\n"); | |
134 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
135 | start_eip & 0xf; | |
136 | pr_debug("3.\n"); | |
137 | } | |
138 | ||
139 | static inline void smpboot_restore_warm_reset_vector(void) | |
140 | { | |
141 | unsigned long flags; | |
142 | ||
143 | /* | |
144 | * Install writable page 0 entry to set BIOS data area. | |
145 | */ | |
146 | local_flush_tlb(); | |
147 | ||
148 | /* | |
149 | * Paranoid: Set warm reset code and vector here back | |
150 | * to default values. | |
151 | */ | |
152 | spin_lock_irqsave(&rtc_lock, flags); | |
153 | CMOS_WRITE(0, 0xf); | |
154 | spin_unlock_irqrestore(&rtc_lock, flags); | |
155 | ||
156 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
157 | } | |
158 | ||
cb3c8b90 | 159 | /* |
30106c17 FY |
160 | * Report back to the Boot Processor during boot time or to the caller processor |
161 | * during CPU online. | |
cb3c8b90 | 162 | */ |
148f9bb8 | 163 | static void smp_callin(void) |
cb3c8b90 GOC |
164 | { |
165 | int cpuid, phys_id; | |
cb3c8b90 GOC |
166 | |
167 | /* | |
168 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
169 | * cpu_callout_mask guarantees we don't get here before |
170 | * an INIT_deassert IPI reaches our local APIC, so it is | |
171 | * now safe to touch our local APIC. | |
cb3c8b90 | 172 | */ |
e1c467e6 | 173 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
174 | |
175 | /* | |
176 | * (This works even if the APIC is not enabled.) | |
177 | */ | |
4c9961d5 | 178 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
179 | |
180 | /* | |
181 | * the boot CPU has finished the init stage and is spinning | |
182 | * on callin_map until we finish. We are free to set up this | |
183 | * CPU, first the APIC. (this is probably redundant on most | |
184 | * boards) | |
185 | */ | |
05f7e46d | 186 | apic_ap_setup(); |
cb3c8b90 | 187 | |
b565201c JS |
188 | /* |
189 | * Save our processor parameters. Note: this information | |
190 | * is needed for clock calibration. | |
191 | */ | |
192 | smp_store_cpu_info(cpuid); | |
193 | ||
cb3c8b90 GOC |
194 | /* |
195 | * Get our bogomips. | |
b565201c JS |
196 | * Update loops_per_jiffy in cpu_data. Previous call to |
197 | * smp_store_cpu_info() stored a value that is close but not as | |
198 | * accurate as the value just calculated. | |
cb3c8b90 | 199 | */ |
cb3c8b90 | 200 | calibrate_delay(); |
b565201c | 201 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 202 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 203 | |
5ef428c4 AK |
204 | /* |
205 | * This must be done before setting cpu_online_mask | |
206 | * or calling notify_cpu_starting. | |
207 | */ | |
208 | set_cpu_sibling_map(raw_smp_processor_id()); | |
209 | wmb(); | |
210 | ||
85257024 PZ |
211 | notify_cpu_starting(cpuid); |
212 | ||
cb3c8b90 GOC |
213 | /* |
214 | * Allow the master to continue. | |
215 | */ | |
c2d1cec1 | 216 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
217 | } |
218 | ||
e1c467e6 FY |
219 | static int cpu0_logical_apicid; |
220 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
221 | /* |
222 | * Activate a secondary processor. | |
223 | */ | |
148f9bb8 | 224 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
225 | { |
226 | /* | |
227 | * Don't put *anything* before cpu_init(), SMP booting is too | |
228 | * fragile that we want to limit the things done here to the | |
229 | * most necessary things. | |
230 | */ | |
b40827fa | 231 | cpu_init(); |
df156f90 | 232 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
233 | preempt_disable(); |
234 | smp_callin(); | |
fd89a137 | 235 | |
e1c467e6 FY |
236 | enable_start_cpu0 = 0; |
237 | ||
fd89a137 | 238 | #ifdef CONFIG_X86_32 |
b40827fa | 239 | /* switch away from the initial page table */ |
fd89a137 JR |
240 | load_cr3(swapper_pg_dir); |
241 | __flush_tlb_all(); | |
242 | #endif | |
243 | ||
bbc2ff6a GOC |
244 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
245 | barrier(); | |
246 | /* | |
247 | * Check TSC synchronization with the BP: | |
248 | */ | |
249 | check_tsc_sync_target(); | |
250 | ||
bbc2ff6a | 251 | /* |
5a3f75e3 TG |
252 | * Lock vector_lock and initialize the vectors on this cpu |
253 | * before setting the cpu online. We must set it online with | |
254 | * vector_lock held to prevent a concurrent setup/teardown | |
255 | * from seeing a half valid vector space. | |
bbc2ff6a | 256 | */ |
d388e5fd | 257 | lock_vector_lock(); |
5a3f75e3 | 258 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 259 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 260 | unlock_vector_lock(); |
2a442c9c | 261 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 262 | x86_platform.nmi_init(); |
bbc2ff6a | 263 | |
0cefa5b9 MS |
264 | /* enable local interrupts */ |
265 | local_irq_enable(); | |
266 | ||
35f720c5 JP |
267 | /* to prevent fake stack check failure in clock setup */ |
268 | boot_init_stack_canary(); | |
0cefa5b9 | 269 | |
736decac | 270 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
271 | |
272 | wmb(); | |
fc6d73d6 | 273 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
274 | } |
275 | ||
9d85eb91 TG |
276 | /** |
277 | * topology_update_package_map - Update the physical to logical package map | |
278 | * @pkg: The physical package id as retrieved via CPUID | |
279 | * @cpu: The cpu for which this is updated | |
280 | */ | |
281 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 282 | { |
9d85eb91 | 283 | unsigned int new; |
1f12e32f TG |
284 | |
285 | /* Called from early boot ? */ | |
286 | if (!physical_package_map) | |
287 | return 0; | |
288 | ||
289 | if (pkg >= max_physical_pkg_id) | |
290 | return -EINVAL; | |
291 | ||
292 | /* Set the logical package id */ | |
293 | if (test_and_set_bit(pkg, physical_package_map)) | |
294 | goto found; | |
295 | ||
9d85eb91 TG |
296 | if (logical_packages >= __max_logical_packages) { |
297 | pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", | |
298 | logical_packages, cpu, __max_logical_packages); | |
1f12e32f TG |
299 | return -ENOSPC; |
300 | } | |
7b0501b1 JO |
301 | |
302 | new = logical_packages++; | |
9d85eb91 TG |
303 | if (new != pkg) { |
304 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
305 | cpu, pkg, new); | |
306 | } | |
1f12e32f TG |
307 | physical_to_logical_pkg[pkg] = new; |
308 | ||
309 | found: | |
310 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; | |
311 | return 0; | |
312 | } | |
313 | ||
314 | /** | |
315 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
316 | * | |
317 | * Returns logical package id or -1 if not found | |
318 | */ | |
319 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
320 | { | |
321 | if (phys_pkg >= max_physical_pkg_id) | |
322 | return -1; | |
323 | return physical_to_logical_pkg[phys_pkg]; | |
324 | } | |
325 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
326 | ||
9d85eb91 | 327 | static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) |
1f12e32f | 328 | { |
9d85eb91 | 329 | unsigned int ncpus; |
1f12e32f TG |
330 | size_t size; |
331 | ||
332 | /* | |
333 | * Today neither Intel nor AMD support heterogenous systems. That | |
334 | * might change in the future.... | |
63d1e995 PZ |
335 | * |
336 | * While ideally we'd want '* smp_num_siblings' in the below @ncpus | |
337 | * computation, this won't actually work since some Intel BIOSes | |
338 | * report inconsistent HT data when they disable HT. | |
339 | * | |
340 | * In particular, they reduce the APIC-IDs to only include the cores, | |
341 | * but leave the CPUID topology to say there are (2) siblings. | |
342 | * This means we don't know how many threads there will be until | |
343 | * after the APIC enumeration. | |
344 | * | |
345 | * By not including this we'll sometimes over-estimate the number of | |
346 | * logical packages by the amount of !present siblings, but this is | |
347 | * still better than MAX_LOCAL_APIC. | |
3e8db224 TG |
348 | * |
349 | * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited | |
350 | * on the command line leading to a similar issue as the HT disable | |
351 | * problem because the hyperthreads are usually enumerated after the | |
352 | * primary cores. | |
1f12e32f | 353 | */ |
63d1e995 | 354 | ncpus = boot_cpu_data.x86_max_cores; |
56402d63 TG |
355 | if (!ncpus) { |
356 | pr_warn("x86_max_cores == zero !?!?"); | |
357 | ncpus = 1; | |
358 | } | |
359 | ||
3e8db224 | 360 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
7b0501b1 | 361 | logical_packages = 0; |
1f12e32f TG |
362 | |
363 | /* | |
364 | * Possibly larger than what we need as the number of apic ids per | |
365 | * package can be smaller than the actual used apic ids. | |
366 | */ | |
367 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); | |
368 | size = max_physical_pkg_id * sizeof(unsigned int); | |
369 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); | |
370 | memset(physical_to_logical_pkg, 0xff, size); | |
371 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); | |
372 | physical_package_map = kzalloc(size, GFP_KERNEL); | |
1f12e32f | 373 | |
7b0501b1 | 374 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
9d85eb91 TG |
375 | |
376 | topology_update_package_map(c->phys_proc_id, cpu); | |
1f12e32f TG |
377 | } |
378 | ||
30106c17 FY |
379 | void __init smp_store_boot_cpu_info(void) |
380 | { | |
381 | int id = 0; /* CPU 0 */ | |
382 | struct cpuinfo_x86 *c = &cpu_data(id); | |
383 | ||
384 | *c = boot_cpu_data; | |
385 | c->cpu_index = id; | |
9d85eb91 | 386 | smp_init_package_map(c, id); |
30106c17 FY |
387 | } |
388 | ||
1d89a7f0 GOC |
389 | /* |
390 | * The bootstrap kernel entry code has set these up. Save them for | |
391 | * a given CPU | |
392 | */ | |
148f9bb8 | 393 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
394 | { |
395 | struct cpuinfo_x86 *c = &cpu_data(id); | |
396 | ||
b3d7336d | 397 | *c = boot_cpu_data; |
1d89a7f0 | 398 | c->cpu_index = id; |
30106c17 FY |
399 | /* |
400 | * During boot time, CPU0 has this setup already. Save the info when | |
401 | * bringing up AP or offlined CPU0. | |
402 | */ | |
403 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
404 | } |
405 | ||
cebf15eb DH |
406 | static bool |
407 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
408 | { | |
409 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
410 | ||
411 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
412 | } | |
413 | ||
148f9bb8 | 414 | static bool |
316ad248 | 415 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 416 | { |
316ad248 PZ |
417 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
418 | ||
cebf15eb | 419 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
420 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
421 | "[node: %d != %d]. Ignoring dependency.\n", | |
422 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
423 | } | |
424 | ||
7d79a7bd | 425 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 426 | do { \ |
7d79a7bd BG |
427 | cpumask_set_cpu((c1), mfunc(c2)); \ |
428 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
429 | } while (0) |
430 | ||
148f9bb8 | 431 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 432 | { |
362f924b | 433 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
434 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
435 | ||
436 | if (c->phys_proc_id == o->phys_proc_id && | |
79a8b9aa BP |
437 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
438 | if (c->cpu_core_id == o->cpu_core_id) | |
439 | return topology_sane(c, o, "smt"); | |
440 | ||
441 | if ((c->cu_id != 0xff) && | |
442 | (o->cu_id != 0xff) && | |
443 | (c->cu_id == o->cu_id)) | |
444 | return topology_sane(c, o, "smt"); | |
445 | } | |
316ad248 PZ |
446 | |
447 | } else if (c->phys_proc_id == o->phys_proc_id && | |
448 | c->cpu_core_id == o->cpu_core_id) { | |
449 | return topology_sane(c, o, "smt"); | |
450 | } | |
451 | ||
452 | return false; | |
453 | } | |
454 | ||
148f9bb8 | 455 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
456 | { |
457 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
458 | ||
459 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
460 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
461 | return topology_sane(c, o, "llc"); | |
462 | ||
463 | return false; | |
d4fbe4f0 AH |
464 | } |
465 | ||
cebf15eb DH |
466 | /* |
467 | * Unlike the other levels, we do not enforce keeping a | |
468 | * multicore group inside a NUMA node. If this happens, we will | |
469 | * discard the MC level of the topology later. | |
470 | */ | |
471 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 472 | { |
cebf15eb DH |
473 | if (c->phys_proc_id == o->phys_proc_id) |
474 | return true; | |
316ad248 PZ |
475 | return false; |
476 | } | |
1d89a7f0 | 477 | |
d3d37d85 TC |
478 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
479 | static inline int x86_sched_itmt_flags(void) | |
480 | { | |
481 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
482 | } | |
483 | ||
484 | #ifdef CONFIG_SCHED_MC | |
485 | static int x86_core_flags(void) | |
486 | { | |
487 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
488 | } | |
489 | #endif | |
490 | #ifdef CONFIG_SCHED_SMT | |
491 | static int x86_smt_flags(void) | |
492 | { | |
493 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
494 | } | |
495 | #endif | |
496 | #endif | |
497 | ||
8f37961c | 498 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 499 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 500 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
501 | #endif |
502 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 503 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
504 | #endif |
505 | { NULL, }, | |
506 | }; | |
8f37961c TC |
507 | |
508 | static struct sched_domain_topology_level x86_topology[] = { | |
509 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 510 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
511 | #endif |
512 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 513 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
514 | #endif |
515 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
516 | { NULL, }, | |
517 | }; | |
518 | ||
cebf15eb | 519 | /* |
8f37961c TC |
520 | * Set if a package/die has multiple NUMA nodes inside. |
521 | * AMD Magny-Cours and Intel Cluster-on-Die have this. | |
cebf15eb | 522 | */ |
8f37961c | 523 | static bool x86_has_numa_in_package; |
cebf15eb | 524 | |
148f9bb8 | 525 | void set_cpu_sibling_map(int cpu) |
768d9505 | 526 | { |
316ad248 | 527 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 528 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 529 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 530 | struct cpuinfo_x86 *o; |
70b8301f | 531 | int i, threads; |
768d9505 | 532 | |
c2d1cec1 | 533 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 534 | |
b0bc225d | 535 | if (!has_mp) { |
7d79a7bd | 536 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 537 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 538 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
539 | c->booted_cores = 1; |
540 | return; | |
541 | } | |
542 | ||
c2d1cec1 | 543 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
544 | o = &cpu_data(i); |
545 | ||
546 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 547 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 548 | |
b0bc225d | 549 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 550 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 551 | |
ceb1cbac KB |
552 | } |
553 | ||
554 | /* | |
555 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 556 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
557 | */ |
558 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
559 | o = &cpu_data(i); | |
560 | ||
cebf15eb | 561 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 562 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 563 | |
768d9505 GC |
564 | /* |
565 | * Does this new cpu bringup a new core? | |
566 | */ | |
7d79a7bd BG |
567 | if (cpumask_weight( |
568 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
569 | /* |
570 | * for each core in package, increment | |
571 | * the booted_cores for this new cpu | |
572 | */ | |
7d79a7bd BG |
573 | if (cpumask_first( |
574 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
575 | c->booted_cores++; |
576 | /* | |
577 | * increment the core count for all | |
578 | * the other cpus in this package | |
579 | */ | |
580 | if (i != cpu) | |
581 | cpu_data(i).booted_cores++; | |
582 | } else if (i != cpu && !c->booted_cores) | |
583 | c->booted_cores = cpu_data(i).booted_cores; | |
584 | } | |
728e5653 | 585 | if (match_die(c, o) && !topology_same_node(c, o)) |
8f37961c | 586 | x86_has_numa_in_package = true; |
768d9505 | 587 | } |
70b8301f AK |
588 | |
589 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
590 | if (threads > __max_smt_threads) | |
591 | __max_smt_threads = threads; | |
768d9505 GC |
592 | } |
593 | ||
70708a18 | 594 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 595 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 596 | { |
9f646389 | 597 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
598 | } |
599 | ||
a4928cff | 600 | static void impress_friends(void) |
904541e2 GOC |
601 | { |
602 | int cpu; | |
603 | unsigned long bogosum = 0; | |
604 | /* | |
605 | * Allow the user to impress friends. | |
606 | */ | |
c767a54b | 607 | pr_debug("Before bogomips\n"); |
904541e2 | 608 | for_each_possible_cpu(cpu) |
c2d1cec1 | 609 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 610 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 611 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 612 | num_online_cpus(), |
904541e2 GOC |
613 | bogosum/(500000/HZ), |
614 | (bogosum/(5000/HZ))%100); | |
615 | ||
c767a54b | 616 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
617 | } |
618 | ||
569712b2 | 619 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
620 | { |
621 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 622 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
623 | int timeout; |
624 | u32 status; | |
625 | ||
c767a54b | 626 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
627 | |
628 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 629 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
630 | |
631 | /* | |
632 | * Wait for idle. | |
633 | */ | |
634 | status = safe_apic_wait_icr_idle(); | |
635 | if (status) | |
c767a54b | 636 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 637 | |
1b374e4d | 638 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
639 | |
640 | timeout = 0; | |
641 | do { | |
642 | udelay(100); | |
643 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
644 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
645 | ||
646 | switch (status) { | |
647 | case APIC_ICR_RR_VALID: | |
648 | status = apic_read(APIC_RRR); | |
c767a54b | 649 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
650 | break; |
651 | default: | |
c767a54b | 652 | pr_cont("failed\n"); |
cb3c8b90 GOC |
653 | } |
654 | } | |
655 | } | |
656 | ||
d68921f9 LB |
657 | /* |
658 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
659 | * that there should be a 10ms delay between the BSP asserting INIT | |
660 | * and de-asserting INIT, when starting a remote processor. | |
661 | * But that slows boot and resume on modern processors, which include | |
662 | * many cores and don't require that delay. | |
663 | * | |
664 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 665 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
666 | */ |
667 | #define UDELAY_10MS_DEFAULT 10000 | |
668 | ||
656279a1 | 669 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
670 | |
671 | static int __init cpu_init_udelay(char *str) | |
672 | { | |
673 | get_option(&str, &init_udelay); | |
674 | ||
675 | return 0; | |
676 | } | |
677 | early_param("cpu_init_udelay", cpu_init_udelay); | |
678 | ||
1a744cb3 LB |
679 | static void __init smp_quirk_init_udelay(void) |
680 | { | |
681 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 682 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
683 | return; |
684 | ||
685 | /* if modern processor, use no delay */ | |
686 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 687 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 688 | init_udelay = 0; |
656279a1 LB |
689 | return; |
690 | } | |
f1ccd249 LB |
691 | /* else, use legacy delay */ |
692 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
693 | } |
694 | ||
cb3c8b90 GOC |
695 | /* |
696 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
697 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
698 | * won't ... remember to clear down the APIC, etc later. | |
699 | */ | |
148f9bb8 | 700 | int |
e1c467e6 | 701 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
702 | { |
703 | unsigned long send_status, accept_status = 0; | |
704 | int maxlvt; | |
705 | ||
706 | /* Target chip */ | |
cb3c8b90 GOC |
707 | /* Boot on the stack */ |
708 | /* Kick the second */ | |
e1c467e6 | 709 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 710 | |
cfc1b9a6 | 711 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
712 | send_status = safe_apic_wait_icr_idle(); |
713 | ||
714 | /* | |
715 | * Give the other CPU some time to accept the IPI. | |
716 | */ | |
717 | udelay(200); | |
cff9ab2b | 718 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
719 | maxlvt = lapic_get_maxlvt(); |
720 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
721 | apic_write(APIC_ESR, 0); | |
722 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
723 | } | |
c767a54b | 724 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
725 | |
726 | if (send_status) | |
c767a54b | 727 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 728 | if (accept_status) |
c767a54b | 729 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
730 | |
731 | return (send_status | accept_status); | |
732 | } | |
cb3c8b90 | 733 | |
148f9bb8 | 734 | static int |
569712b2 | 735 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 736 | { |
f5d6a52f | 737 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
738 | int maxlvt, num_starts, j; |
739 | ||
593f4a78 MR |
740 | maxlvt = lapic_get_maxlvt(); |
741 | ||
cb3c8b90 GOC |
742 | /* |
743 | * Be paranoid about clearing APIC errors. | |
744 | */ | |
cff9ab2b | 745 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
746 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
747 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
748 | apic_read(APIC_ESR); |
749 | } | |
750 | ||
c767a54b | 751 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
752 | |
753 | /* | |
754 | * Turn INIT on target chip | |
755 | */ | |
cb3c8b90 GOC |
756 | /* |
757 | * Send IPI | |
758 | */ | |
1b374e4d SS |
759 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
760 | phys_apicid); | |
cb3c8b90 | 761 | |
cfc1b9a6 | 762 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
763 | send_status = safe_apic_wait_icr_idle(); |
764 | ||
7cb68598 | 765 | udelay(init_udelay); |
cb3c8b90 | 766 | |
c767a54b | 767 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
768 | |
769 | /* Target chip */ | |
cb3c8b90 | 770 | /* Send IPI */ |
1b374e4d | 771 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 772 | |
cfc1b9a6 | 773 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
774 | send_status = safe_apic_wait_icr_idle(); |
775 | ||
776 | mb(); | |
cb3c8b90 GOC |
777 | |
778 | /* | |
779 | * Should we send STARTUP IPIs ? | |
780 | * | |
781 | * Determine this based on the APIC version. | |
782 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
783 | */ | |
cff9ab2b | 784 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
785 | num_starts = 2; |
786 | else | |
787 | num_starts = 0; | |
788 | ||
cb3c8b90 GOC |
789 | /* |
790 | * Run STARTUP IPI loop. | |
791 | */ | |
c767a54b | 792 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 793 | |
cb3c8b90 | 794 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 795 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
796 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
797 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 798 | apic_read(APIC_ESR); |
c767a54b | 799 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
800 | |
801 | /* | |
802 | * STARTUP IPI | |
803 | */ | |
804 | ||
805 | /* Target chip */ | |
cb3c8b90 GOC |
806 | /* Boot on the stack */ |
807 | /* Kick the second */ | |
1b374e4d SS |
808 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
809 | phys_apicid); | |
cb3c8b90 GOC |
810 | |
811 | /* | |
812 | * Give the other CPU some time to accept the IPI. | |
813 | */ | |
fcafddec LB |
814 | if (init_udelay == 0) |
815 | udelay(10); | |
816 | else | |
a9bcaa02 | 817 | udelay(300); |
cb3c8b90 | 818 | |
c767a54b | 819 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 820 | |
cfc1b9a6 | 821 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
822 | send_status = safe_apic_wait_icr_idle(); |
823 | ||
824 | /* | |
825 | * Give the other CPU some time to accept the IPI. | |
826 | */ | |
fcafddec LB |
827 | if (init_udelay == 0) |
828 | udelay(10); | |
829 | else | |
a9bcaa02 | 830 | udelay(200); |
cb3c8b90 | 831 | |
593f4a78 | 832 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 833 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
834 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
835 | if (send_status || accept_status) | |
836 | break; | |
837 | } | |
c767a54b | 838 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
839 | |
840 | if (send_status) | |
c767a54b | 841 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 842 | if (accept_status) |
c767a54b | 843 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
844 | |
845 | return (send_status | accept_status); | |
846 | } | |
cb3c8b90 | 847 | |
2eaad1fd | 848 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 849 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
850 | { |
851 | static int current_node = -1; | |
4adc8b71 | 852 | int node = early_cpu_to_node(cpu); |
a17bce4d | 853 | static int width, node_width; |
646e29a1 BP |
854 | |
855 | if (!width) | |
856 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 857 | |
a17bce4d BP |
858 | if (!node_width) |
859 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
860 | ||
861 | if (cpu == 1) | |
862 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
863 | ||
2eaad1fd MT |
864 | if (system_state == SYSTEM_BOOTING) { |
865 | if (node != current_node) { | |
866 | if (current_node > (-1)) | |
a17bce4d | 867 | pr_cont("\n"); |
2eaad1fd | 868 | current_node = node; |
a17bce4d BP |
869 | |
870 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
871 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 872 | } |
646e29a1 BP |
873 | |
874 | /* Add padding for the BSP */ | |
875 | if (cpu == 1) | |
876 | pr_cont("%*s", width + 1, " "); | |
877 | ||
878 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
879 | ||
2eaad1fd MT |
880 | } else |
881 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
882 | node, cpu, apicid); | |
883 | } | |
884 | ||
e1c467e6 FY |
885 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
886 | { | |
887 | int cpu; | |
888 | ||
889 | cpu = smp_processor_id(); | |
890 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
891 | return NMI_HANDLED; | |
892 | ||
893 | return NMI_DONE; | |
894 | } | |
895 | ||
896 | /* | |
897 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
898 | * | |
899 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
900 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
901 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
902 | * | |
903 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
904 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
905 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
906 | * real platform and request are available. | |
907 | */ | |
148f9bb8 | 908 | static int |
e1c467e6 FY |
909 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
910 | int *cpu0_nmi_registered) | |
911 | { | |
912 | int id; | |
913 | int boot_error; | |
914 | ||
ea7bdc65 JK |
915 | preempt_disable(); |
916 | ||
e1c467e6 FY |
917 | /* |
918 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
919 | */ | |
ea7bdc65 JK |
920 | if (cpu) { |
921 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
922 | goto out; | |
923 | } | |
e1c467e6 FY |
924 | |
925 | /* | |
926 | * Wake up BSP by nmi. | |
927 | * | |
928 | * Register a NMI handler to help wake up CPU0. | |
929 | */ | |
930 | boot_error = register_nmi_handler(NMI_LOCAL, | |
931 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
932 | ||
933 | if (!boot_error) { | |
934 | enable_start_cpu0 = 1; | |
935 | *cpu0_nmi_registered = 1; | |
936 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
937 | id = cpu0_logical_apicid; | |
938 | else | |
939 | id = apicid; | |
940 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
941 | } | |
ea7bdc65 JK |
942 | |
943 | out: | |
944 | preempt_enable(); | |
e1c467e6 FY |
945 | |
946 | return boot_error; | |
947 | } | |
948 | ||
3f85483b BO |
949 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
950 | { | |
951 | /* Just in case we booted with a single CPU. */ | |
952 | alternatives_enable_smp(); | |
953 | ||
954 | per_cpu(current_task, cpu) = idle; | |
955 | ||
956 | #ifdef CONFIG_X86_32 | |
957 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
958 | irq_ctx_init(cpu); | |
959 | per_cpu(cpu_current_top_of_stack, cpu) = | |
960 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
961 | #else | |
3f85483b BO |
962 | initial_gs = per_cpu_offset(cpu); |
963 | #endif | |
3f85483b BO |
964 | } |
965 | ||
cb3c8b90 GOC |
966 | /* |
967 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
968 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
969 | * Returns zero if CPU booted OK, else error code from |
970 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 971 | */ |
148f9bb8 | 972 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 973 | { |
48927bbb | 974 | volatile u32 *trampoline_status = |
b429dbf6 | 975 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 976 | /* start_ip had better be page-aligned! */ |
f37240f1 | 977 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 978 | |
cb3c8b90 | 979 | unsigned long boot_error = 0; |
e1c467e6 | 980 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 981 | unsigned long timeout; |
cb3c8b90 | 982 | |
b9b1a9c3 | 983 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
a939098a | 984 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 985 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 986 | initial_stack = idle->thread.sp; |
cb3c8b90 | 987 | |
20d5e4a9 ZG |
988 | /* |
989 | * Enable the espfix hack for this CPU | |
990 | */ | |
991 | #ifdef CONFIG_X86_ESPFIX64 | |
992 | init_espfix_ap(cpu); | |
993 | #endif | |
994 | ||
2eaad1fd MT |
995 | /* So we see what's up */ |
996 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
997 | |
998 | /* | |
999 | * This grunge runs the startup process for | |
1000 | * the targeted processor. | |
1001 | */ | |
1002 | ||
34d05591 | 1003 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 1004 | |
cfc1b9a6 | 1005 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 1006 | |
34d05591 JS |
1007 | smpboot_setup_warm_reset_vector(start_ip); |
1008 | /* | |
1009 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1010 | */ |
cff9ab2b | 1011 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1012 | apic_write(APIC_ESR, 0); |
1013 | apic_read(APIC_ESR); | |
1014 | } | |
34d05591 | 1015 | } |
cb3c8b90 | 1016 | |
ce4b1b16 IM |
1017 | /* |
1018 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1019 | * cpu_initialized_mask set if previous attempt to online | |
1020 | * it timed-out. Clear cpu_initialized_mask so that after | |
1021 | * INIT/SIPI it could start with a clean state. | |
1022 | */ | |
1023 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1024 | smp_mb(); | |
1025 | ||
cb3c8b90 | 1026 | /* |
e1c467e6 FY |
1027 | * Wake up a CPU in difference cases: |
1028 | * - Use the method in the APIC driver if it's defined | |
1029 | * Otherwise, | |
1030 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1031 | */ |
1f5bcabf IM |
1032 | if (apic->wakeup_secondary_cpu) |
1033 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1034 | else | |
e1c467e6 FY |
1035 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
1036 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
1037 | |
1038 | if (!boot_error) { | |
1039 | /* | |
6e38f1e7 | 1040 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1041 | */ |
ce4b1b16 IM |
1042 | boot_error = -1; |
1043 | timeout = jiffies + 10*HZ; | |
1044 | while (time_before(jiffies, timeout)) { | |
1045 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1046 | /* | |
1047 | * Tell AP to proceed with initialization | |
1048 | */ | |
1049 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1050 | boot_error = 0; | |
1051 | break; | |
1052 | } | |
ce4b1b16 IM |
1053 | schedule(); |
1054 | } | |
1055 | } | |
cb3c8b90 | 1056 | |
ce4b1b16 | 1057 | if (!boot_error) { |
cb3c8b90 | 1058 | /* |
ce4b1b16 | 1059 | * Wait till AP completes initial initialization |
cb3c8b90 | 1060 | */ |
ce4b1b16 | 1061 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1062 | /* |
1063 | * Allow other tasks to run while we wait for the | |
1064 | * AP to come online. This also gives a chance | |
1065 | * for the MTRR work(triggered by the AP coming online) | |
1066 | * to be completed in the stop machine context. | |
1067 | */ | |
1068 | schedule(); | |
cb3c8b90 | 1069 | } |
cb3c8b90 GOC |
1070 | } |
1071 | ||
1072 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1073 | *trampoline_status = 0; |
cb3c8b90 | 1074 | |
02421f98 YL |
1075 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1076 | /* | |
1077 | * Cleanup possible dangling ends... | |
1078 | */ | |
1079 | smpboot_restore_warm_reset_vector(); | |
1080 | } | |
e1c467e6 FY |
1081 | /* |
1082 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1083 | * to avoid impact of possible long unregister time. | |
1084 | */ | |
1085 | if (cpu0_nmi_registered) | |
1086 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1087 | ||
cb3c8b90 GOC |
1088 | return boot_error; |
1089 | } | |
1090 | ||
148f9bb8 | 1091 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1092 | { |
a21769a4 | 1093 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
1094 | unsigned long flags; |
1095 | int err; | |
1096 | ||
1097 | WARN_ON(irqs_disabled()); | |
1098 | ||
cfc1b9a6 | 1099 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1100 | |
30106c17 | 1101 | if (apicid == BAD_APICID || |
c284b42a | 1102 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1103 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1104 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1105 | return -EINVAL; |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * Already booted CPU? | |
1110 | */ | |
c2d1cec1 | 1111 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1112 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1113 | return -ENOSYS; |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * Save current MTRR state in case it was changed since early boot | |
1118 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1119 | */ | |
1120 | mtrr_save_state(); | |
1121 | ||
2a442c9c PM |
1122 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1123 | err = cpu_check_up_prepare(cpu); | |
1124 | if (err && err != -EBUSY) | |
1125 | return err; | |
cb3c8b90 | 1126 | |
644c1541 | 1127 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1128 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1129 | |
3f85483b BO |
1130 | common_cpu_up(cpu, tidle); |
1131 | ||
7eb43a6d | 1132 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 1133 | if (err) { |
feef1e8e | 1134 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 1135 | return -EIO; |
cb3c8b90 GOC |
1136 | } |
1137 | ||
1138 | /* | |
1139 | * Check TSC synchronization with the AP (keep irqs disabled | |
1140 | * while doing so): | |
1141 | */ | |
1142 | local_irq_save(flags); | |
1143 | check_tsc_sync_source(cpu); | |
1144 | local_irq_restore(flags); | |
1145 | ||
7c04e64a | 1146 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1147 | cpu_relax(); |
1148 | touch_nmi_watchdog(); | |
1149 | } | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
7167d08e HK |
1154 | /** |
1155 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1156 | */ | |
1157 | void arch_disable_smp_support(void) | |
1158 | { | |
1159 | disable_ioapic_support(); | |
1160 | } | |
1161 | ||
8aef135c GOC |
1162 | /* |
1163 | * Fall back to non SMP mode after errors. | |
1164 | * | |
1165 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1166 | */ | |
1167 | static __init void disable_smp(void) | |
1168 | { | |
613c25ef TG |
1169 | pr_info("SMP disabled\n"); |
1170 | ||
ef4c59a4 TG |
1171 | disable_ioapic_support(); |
1172 | ||
4f062896 RR |
1173 | init_cpu_present(cpumask_of(0)); |
1174 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1175 | |
8aef135c | 1176 | if (smp_found_config) |
b6df1b8b | 1177 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1178 | else |
b6df1b8b | 1179 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1180 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1181 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1182 | } |
1183 | ||
613c25ef TG |
1184 | enum { |
1185 | SMP_OK, | |
1186 | SMP_NO_CONFIG, | |
1187 | SMP_NO_APIC, | |
1188 | SMP_FORCE_UP, | |
1189 | }; | |
1190 | ||
8aef135c GOC |
1191 | /* |
1192 | * Various sanity checks. | |
1193 | */ | |
1194 | static int __init smp_sanity_check(unsigned max_cpus) | |
1195 | { | |
ac23d4ee | 1196 | preempt_disable(); |
a58f03b0 | 1197 | |
1ff2f20d | 1198 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1199 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1200 | unsigned int cpu; | |
1201 | unsigned nr; | |
1202 | ||
c767a54b JP |
1203 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1204 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1205 | |
1206 | nr = 0; | |
1207 | for_each_present_cpu(cpu) { | |
1208 | if (nr >= 8) | |
c2d1cec1 | 1209 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1210 | nr++; |
1211 | } | |
1212 | ||
1213 | nr = 0; | |
1214 | for_each_possible_cpu(cpu) { | |
1215 | if (nr >= 8) | |
c2d1cec1 | 1216 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1217 | nr++; |
1218 | } | |
1219 | ||
1220 | nr_cpu_ids = 8; | |
1221 | } | |
1222 | #endif | |
1223 | ||
8aef135c | 1224 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1225 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1226 | hard_smp_processor_id()); |
1227 | ||
8aef135c GOC |
1228 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1229 | } | |
1230 | ||
1231 | /* | |
1232 | * If we couldn't find an SMP configuration at boot time, | |
1233 | * get out of here now! | |
1234 | */ | |
1235 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1236 | preempt_enable(); |
c767a54b | 1237 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1238 | return SMP_NO_CONFIG; |
8aef135c GOC |
1239 | } |
1240 | ||
1241 | /* | |
1242 | * Should not be necessary because the MP table should list the boot | |
1243 | * CPU too, but we do it for the sake of robustness anyway. | |
1244 | */ | |
a27a6210 | 1245 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1246 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1247 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1248 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1249 | } | |
ac23d4ee | 1250 | preempt_enable(); |
8aef135c GOC |
1251 | |
1252 | /* | |
1253 | * If we couldn't find a local APIC, then get out of here now! | |
1254 | */ | |
cff9ab2b | 1255 | if (APIC_INTEGRATED(boot_cpu_apic_version) && |
93984fbd | 1256 | !boot_cpu_has(X86_FEATURE_APIC)) { |
103428e5 CG |
1257 | if (!disable_apic) { |
1258 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1259 | boot_cpu_physical_apicid); | |
c767a54b | 1260 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1261 | } |
613c25ef | 1262 | return SMP_NO_APIC; |
8aef135c GOC |
1263 | } |
1264 | ||
8aef135c GOC |
1265 | /* |
1266 | * If SMP should be disabled, then really disable it! | |
1267 | */ | |
1268 | if (!max_cpus) { | |
c767a54b | 1269 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1270 | return SMP_FORCE_UP; |
8aef135c GOC |
1271 | } |
1272 | ||
613c25ef | 1273 | return SMP_OK; |
8aef135c GOC |
1274 | } |
1275 | ||
1276 | static void __init smp_cpu_index_default(void) | |
1277 | { | |
1278 | int i; | |
1279 | struct cpuinfo_x86 *c; | |
1280 | ||
7c04e64a | 1281 | for_each_possible_cpu(i) { |
8aef135c GOC |
1282 | c = &cpu_data(i); |
1283 | /* mark all to hotplug */ | |
9628937d | 1284 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1285 | } |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1290 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1291 | */ | |
1292 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1293 | { | |
7ad728f9 RR |
1294 | unsigned int i; |
1295 | ||
8aef135c | 1296 | smp_cpu_index_default(); |
792363d2 | 1297 | |
8aef135c GOC |
1298 | /* |
1299 | * Setup boot CPU information | |
1300 | */ | |
30106c17 | 1301 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1302 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1303 | mb(); | |
bd22a2f1 | 1304 | |
7ad728f9 | 1305 | for_each_possible_cpu(i) { |
79f55997 LZ |
1306 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1307 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1308 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1309 | } |
8f37961c TC |
1310 | |
1311 | /* | |
1312 | * Set 'default' x86 topology, this matches default_topology() in that | |
1313 | * it has NUMA nodes as a topology level. See also | |
1314 | * native_smp_cpus_done(). | |
1315 | * | |
1316 | * Must be done before set_cpus_sibling_map() is ran. | |
1317 | */ | |
1318 | set_sched_topology(x86_topology); | |
1319 | ||
8aef135c GOC |
1320 | set_cpu_sibling_map(0); |
1321 | ||
613c25ef TG |
1322 | switch (smp_sanity_check(max_cpus)) { |
1323 | case SMP_NO_CONFIG: | |
8aef135c | 1324 | disable_smp(); |
613c25ef TG |
1325 | if (APIC_init_uniprocessor()) |
1326 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1327 | return; | |
1328 | case SMP_NO_APIC: | |
1329 | disable_smp(); | |
1330 | return; | |
1331 | case SMP_FORCE_UP: | |
1332 | disable_smp(); | |
374aab33 | 1333 | apic_bsp_setup(false); |
250a1ac6 | 1334 | return; |
613c25ef TG |
1335 | case SMP_OK: |
1336 | break; | |
8aef135c GOC |
1337 | } |
1338 | ||
4c9961d5 | 1339 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1340 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1341 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1342 | /* Or can we switch back to PIC here? */ |
1343 | } | |
1344 | ||
384d9fe3 | 1345 | default_setup_apic_routing(); |
374aab33 | 1346 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1347 | |
d54ff31d | 1348 | pr_info("CPU0: "); |
8aef135c | 1349 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1350 | |
9ec808a0 | 1351 | uv_system_init(); |
d0af9eed SS |
1352 | |
1353 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1354 | |
1355 | smp_quirk_init_udelay(); | |
8aef135c | 1356 | } |
d0af9eed SS |
1357 | |
1358 | void arch_enable_nonboot_cpus_begin(void) | |
1359 | { | |
1360 | set_mtrr_aps_delayed_init(); | |
1361 | } | |
1362 | ||
1363 | void arch_enable_nonboot_cpus_end(void) | |
1364 | { | |
1365 | mtrr_aps_init(); | |
1366 | } | |
1367 | ||
a8db8453 GOC |
1368 | /* |
1369 | * Early setup to make printk work. | |
1370 | */ | |
1371 | void __init native_smp_prepare_boot_cpu(void) | |
1372 | { | |
1373 | int me = smp_processor_id(); | |
552be871 | 1374 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1375 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1376 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1377 | cpu_set_state_online(me); |
a8db8453 GOC |
1378 | } |
1379 | ||
83f7eb9c GOC |
1380 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1381 | { | |
c767a54b | 1382 | pr_debug("Boot done\n"); |
83f7eb9c | 1383 | |
8f37961c TC |
1384 | if (x86_has_numa_in_package) |
1385 | set_sched_topology(x86_numa_in_package_topology); | |
1386 | ||
99e8b9ca | 1387 | nmi_selftest(); |
83f7eb9c | 1388 | impress_friends(); |
83f7eb9c | 1389 | setup_ioapic_dest(); |
d0af9eed | 1390 | mtrr_aps_init(); |
83f7eb9c GOC |
1391 | } |
1392 | ||
3b11ce7f MT |
1393 | static int __initdata setup_possible_cpus = -1; |
1394 | static int __init _setup_possible_cpus(char *str) | |
1395 | { | |
1396 | get_option(&str, &setup_possible_cpus); | |
1397 | return 0; | |
1398 | } | |
1399 | early_param("possible_cpus", _setup_possible_cpus); | |
1400 | ||
1401 | ||
68a1c3f8 | 1402 | /* |
4f062896 | 1403 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1404 | * are onlined, or offlined. The reason is per-cpu data-structures |
1405 | * are allocated by some modules at init time, and dont expect to | |
1406 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1407 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1408 | * In case when cpu_hotplug is not compiled, then we resort to current |
1409 | * behaviour, which is cpu_possible == cpu_present. | |
1410 | * - Ashok Raj | |
1411 | * | |
1412 | * Three ways to find out the number of additional hotplug CPUs: | |
1413 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1414 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1415 | * - Otherwise don't reserve additional CPUs. |
1416 | * We do this because additional CPUs waste a lot of memory. | |
1417 | * -AK | |
1418 | */ | |
1419 | __init void prefill_possible_map(void) | |
1420 | { | |
cb48bb59 | 1421 | int i, possible; |
68a1c3f8 | 1422 | |
2a51fe08 PB |
1423 | /* No boot processor was found in mptable or ACPI MADT */ |
1424 | if (!num_processors) { | |
ff856051 VS |
1425 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1426 | int apicid = boot_cpu_physical_apicid; | |
1427 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1428 | |
ff856051 | 1429 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1430 | |
ff856051 VS |
1431 | /* Make sure boot cpu is enumerated */ |
1432 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1433 | apic->apic_id_valid(apicid)) | |
1434 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1435 | } | |
2a51fe08 PB |
1436 | |
1437 | if (!num_processors) | |
1438 | num_processors = 1; | |
1439 | } | |
329513a3 | 1440 | |
5f2eb550 JB |
1441 | i = setup_max_cpus ?: 1; |
1442 | if (setup_possible_cpus == -1) { | |
1443 | possible = num_processors; | |
1444 | #ifdef CONFIG_HOTPLUG_CPU | |
1445 | if (setup_max_cpus) | |
1446 | possible += disabled_cpus; | |
1447 | #else | |
1448 | if (possible > i) | |
1449 | possible = i; | |
1450 | #endif | |
1451 | } else | |
3b11ce7f MT |
1452 | possible = setup_possible_cpus; |
1453 | ||
730cf272 MT |
1454 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1455 | ||
2b633e3f YL |
1456 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1457 | if (possible > nr_cpu_ids) { | |
c767a54b | 1458 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1459 | possible, nr_cpu_ids); |
1460 | possible = nr_cpu_ids; | |
3b11ce7f | 1461 | } |
68a1c3f8 | 1462 | |
5f2eb550 JB |
1463 | #ifdef CONFIG_HOTPLUG_CPU |
1464 | if (!setup_max_cpus) | |
1465 | #endif | |
1466 | if (possible > i) { | |
c767a54b | 1467 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1468 | possible, setup_max_cpus); |
1469 | possible = i; | |
1470 | } | |
1471 | ||
427d77a3 TG |
1472 | nr_cpu_ids = possible; |
1473 | ||
c767a54b | 1474 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1475 | possible, max_t(int, possible - num_processors, 0)); |
1476 | ||
427d77a3 TG |
1477 | reset_cpu_possible_mask(); |
1478 | ||
68a1c3f8 | 1479 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1480 | set_cpu_possible(i, true); |
68a1c3f8 | 1481 | } |
69c18c15 | 1482 | |
14adf855 CE |
1483 | #ifdef CONFIG_HOTPLUG_CPU |
1484 | ||
70b8301f AK |
1485 | /* Recompute SMT state for all CPUs on offline */ |
1486 | static void recompute_smt_state(void) | |
1487 | { | |
1488 | int max_threads, cpu; | |
1489 | ||
1490 | max_threads = 0; | |
1491 | for_each_online_cpu (cpu) { | |
1492 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1493 | ||
1494 | if (threads > max_threads) | |
1495 | max_threads = threads; | |
1496 | } | |
1497 | __max_smt_threads = max_threads; | |
1498 | } | |
1499 | ||
14adf855 CE |
1500 | static void remove_siblinginfo(int cpu) |
1501 | { | |
1502 | int sibling; | |
1503 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1504 | ||
7d79a7bd BG |
1505 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1506 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1507 | /*/ |
1508 | * last thread sibling in this cpu core going down | |
1509 | */ | |
7d79a7bd | 1510 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1511 | cpu_data(sibling).booted_cores--; |
1512 | } | |
1513 | ||
7d79a7bd BG |
1514 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1515 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1516 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1517 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1518 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1519 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1520 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1521 | c->phys_proc_id = 0; |
1522 | c->cpu_core_id = 0; | |
c2d1cec1 | 1523 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1524 | recompute_smt_state(); |
14adf855 CE |
1525 | } |
1526 | ||
4daa832d | 1527 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1528 | { |
c2d1cec1 MT |
1529 | set_cpu_online(cpu, false); |
1530 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1531 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1532 | /* was set by cpu_init() */ |
c2d1cec1 | 1533 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1534 | numa_remove_cpu(cpu); |
69c18c15 GC |
1535 | } |
1536 | ||
8227dce7 | 1537 | void cpu_disable_common(void) |
69c18c15 GC |
1538 | { |
1539 | int cpu = smp_processor_id(); | |
69c18c15 | 1540 | |
69c18c15 GC |
1541 | remove_siblinginfo(cpu); |
1542 | ||
1543 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1544 | lock_vector_lock(); |
69c18c15 | 1545 | remove_cpu_from_maps(cpu); |
d388e5fd | 1546 | unlock_vector_lock(); |
d7b381bb | 1547 | fixup_irqs(); |
8227dce7 AN |
1548 | } |
1549 | ||
1550 | int native_cpu_disable(void) | |
1551 | { | |
da6139e4 PB |
1552 | int ret; |
1553 | ||
1554 | ret = check_irq_vectors_for_cpu_disable(); | |
1555 | if (ret) | |
1556 | return ret; | |
1557 | ||
8227dce7 | 1558 | clear_local_APIC(); |
8227dce7 | 1559 | cpu_disable_common(); |
2ed53c0d | 1560 | |
69c18c15 GC |
1561 | return 0; |
1562 | } | |
1563 | ||
2a442c9c | 1564 | int common_cpu_die(unsigned int cpu) |
54279552 | 1565 | { |
2a442c9c | 1566 | int ret = 0; |
54279552 | 1567 | |
69c18c15 | 1568 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1569 | |
2ed53c0d | 1570 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1571 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1572 | if (system_state == SYSTEM_RUNNING) |
1573 | pr_info("CPU %u is now offline\n", cpu); | |
1574 | } else { | |
1575 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1576 | ret = -1; |
69c18c15 | 1577 | } |
2a442c9c PM |
1578 | |
1579 | return ret; | |
1580 | } | |
1581 | ||
1582 | void native_cpu_die(unsigned int cpu) | |
1583 | { | |
1584 | common_cpu_die(cpu); | |
69c18c15 | 1585 | } |
a21f5d88 AN |
1586 | |
1587 | void play_dead_common(void) | |
1588 | { | |
1589 | idle_task_exit(); | |
1590 | reset_lazy_tlbstate(); | |
a21f5d88 | 1591 | |
a21f5d88 | 1592 | /* Ack it */ |
2a442c9c | 1593 | (void)cpu_report_death(); |
a21f5d88 AN |
1594 | |
1595 | /* | |
1596 | * With physical CPU hotplug, we should halt the cpu | |
1597 | */ | |
1598 | local_irq_disable(); | |
1599 | } | |
1600 | ||
e1c467e6 FY |
1601 | static bool wakeup_cpu0(void) |
1602 | { | |
1603 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1604 | return true; | |
1605 | ||
1606 | return false; | |
1607 | } | |
1608 | ||
ea530692 PA |
1609 | /* |
1610 | * We need to flush the caches before going to sleep, lest we have | |
1611 | * dirty data in our caches when we come back up. | |
1612 | */ | |
1613 | static inline void mwait_play_dead(void) | |
1614 | { | |
1615 | unsigned int eax, ebx, ecx, edx; | |
1616 | unsigned int highest_cstate = 0; | |
1617 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1618 | void *mwait_ptr; |
576cfb40 | 1619 | int i; |
ea530692 | 1620 | |
69fb3676 | 1621 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1622 | return; |
840d2830 | 1623 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1624 | return; |
7b543a53 | 1625 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1626 | return; |
1627 | ||
1628 | eax = CPUID_MWAIT_LEAF; | |
1629 | ecx = 0; | |
1630 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1631 | ||
1632 | /* | |
1633 | * eax will be 0 if EDX enumeration is not valid. | |
1634 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1635 | */ | |
1636 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1637 | eax = 0; | |
1638 | } else { | |
1639 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1640 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1641 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1642 | highest_cstate = i; | |
1643 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1644 | } | |
1645 | } | |
1646 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1647 | (highest_subcstate - 1); | |
1648 | } | |
1649 | ||
ce5f6824 PA |
1650 | /* |
1651 | * This should be a memory location in a cache line which is | |
1652 | * unlikely to be touched by other processors. The actual | |
1653 | * content is immaterial as it is not actually modified in any way. | |
1654 | */ | |
1655 | mwait_ptr = ¤t_thread_info()->flags; | |
1656 | ||
a68e5c94 PA |
1657 | wbinvd(); |
1658 | ||
ea530692 | 1659 | while (1) { |
ce5f6824 PA |
1660 | /* |
1661 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1662 | * the Xeon 7400 series. It's not clear it is actually | |
1663 | * needed, but it should be harmless in either case. | |
1664 | * The WBINVD is insufficient due to the spurious-wakeup | |
1665 | * case where we return around the loop. | |
1666 | */ | |
7d590cca | 1667 | mb(); |
ce5f6824 | 1668 | clflush(mwait_ptr); |
7d590cca | 1669 | mb(); |
ce5f6824 | 1670 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1671 | mb(); |
1672 | __mwait(eax, 0); | |
e1c467e6 FY |
1673 | /* |
1674 | * If NMI wants to wake up CPU0, start CPU0. | |
1675 | */ | |
1676 | if (wakeup_cpu0()) | |
1677 | start_cpu0(); | |
ea530692 PA |
1678 | } |
1679 | } | |
1680 | ||
406f992e | 1681 | void hlt_play_dead(void) |
ea530692 | 1682 | { |
7b543a53 | 1683 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1684 | wbinvd(); |
1685 | ||
ea530692 | 1686 | while (1) { |
ea530692 | 1687 | native_halt(); |
e1c467e6 FY |
1688 | /* |
1689 | * If NMI wants to wake up CPU0, start CPU0. | |
1690 | */ | |
1691 | if (wakeup_cpu0()) | |
1692 | start_cpu0(); | |
ea530692 PA |
1693 | } |
1694 | } | |
1695 | ||
a21f5d88 AN |
1696 | void native_play_dead(void) |
1697 | { | |
1698 | play_dead_common(); | |
86886e55 | 1699 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1700 | |
1701 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1702 | if (cpuidle_play_dead()) |
1703 | hlt_play_dead(); | |
a21f5d88 AN |
1704 | } |
1705 | ||
69c18c15 | 1706 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1707 | int native_cpu_disable(void) |
69c18c15 GC |
1708 | { |
1709 | return -ENOSYS; | |
1710 | } | |
1711 | ||
93be71b6 | 1712 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1713 | { |
1714 | /* We said "no" in __cpu_disable */ | |
1715 | BUG(); | |
1716 | } | |
a21f5d88 AN |
1717 | |
1718 | void native_play_dead(void) | |
1719 | { | |
1720 | BUG(); | |
1721 | } | |
1722 | ||
68a1c3f8 | 1723 | #endif |