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Commit | Line | Data |
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4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
69c18c15 | 53 | |
8aef135c | 54 | #include <asm/acpi.h> |
cb3c8b90 | 55 | #include <asm/desc.h> |
69c18c15 GC |
56 | #include <asm/nmi.h> |
57 | #include <asm/irq.h> | |
07bbc16a | 58 | #include <asm/idle.h> |
e44b7b75 | 59 | #include <asm/trampoline.h> |
69c18c15 GC |
60 | #include <asm/cpu.h> |
61 | #include <asm/numa.h> | |
cb3c8b90 GOC |
62 | #include <asm/pgtable.h> |
63 | #include <asm/tlbflush.h> | |
64 | #include <asm/mtrr.h> | |
ea530692 | 65 | #include <asm/mwait.h> |
7b6aa335 | 66 | #include <asm/apic.h> |
569712b2 | 67 | #include <asm/setup.h> |
bdbcdd48 | 68 | #include <asm/uv/uv.h> |
cb3c8b90 | 69 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 70 | |
1164dd00 | 71 | #include <asm/smpboot_hooks.h> |
b81bb373 | 72 | #include <asm/i8259.h> |
cb3c8b90 | 73 | |
16ecf7a4 | 74 | #ifdef CONFIG_X86_32 |
4cedb334 | 75 | u8 apicid_2_node[MAX_APICID]; |
acbb6734 GOC |
76 | #endif |
77 | ||
a8db8453 GOC |
78 | /* State of each CPU */ |
79 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
80 | ||
cb3c8b90 GOC |
81 | /* Store all idle threads, this can be reused instead of creating |
82 | * a new thread. Also avoids complicated thread destroy functionality | |
83 | * for idle threads. | |
84 | */ | |
85 | #ifdef CONFIG_HOTPLUG_CPU | |
86 | /* | |
87 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
88 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
89 | */ | |
90 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
91 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
92 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
93 | |
94 | /* | |
95 | * We need this for trampoline_base protection from concurrent accesses when | |
96 | * off- and onlining cores wildly. | |
97 | */ | |
98 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
99 | ||
91d88ce2 | 100 | void cpu_hotplug_driver_lock(void) |
d7c53c9e BP |
101 | { |
102 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
103 | } | |
104 | ||
91d88ce2 | 105 | void cpu_hotplug_driver_unlock(void) |
d7c53c9e BP |
106 | { |
107 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
108 | } | |
109 | ||
110 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
111 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 112 | #else |
f86c9985 | 113 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
114 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
115 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
116 | #endif | |
f6bc4029 | 117 | |
a355352b GC |
118 | /* Number of siblings per CPU package */ |
119 | int smp_num_siblings = 1; | |
120 | EXPORT_SYMBOL(smp_num_siblings); | |
121 | ||
122 | /* Last level cache ID of each logical CPU */ | |
123 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
124 | ||
a355352b | 125 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 126 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
127 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
128 | ||
129 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 130 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
131 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
132 | ||
b3d7336d YL |
133 | DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); |
134 | ||
a355352b GC |
135 | /* Per CPU bogomips and other parameters */ |
136 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
137 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 138 | |
2b6163bf | 139 | atomic_t init_deasserted; |
cb3c8b90 | 140 | |
7cc3959e | 141 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
142 | /* which node each logical CPU is on */ |
143 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
144 | EXPORT_SYMBOL(cpu_to_node_map); | |
145 | ||
146 | /* set up a mapping between cpu and node. */ | |
147 | static void map_cpu_to_node(int cpu, int node) | |
148 | { | |
149 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 150 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
151 | cpu_to_node_map[cpu] = node; |
152 | } | |
153 | ||
154 | /* undo a mapping between cpu and node. */ | |
155 | static void unmap_cpu_to_node(int cpu) | |
156 | { | |
157 | int node; | |
158 | ||
159 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
160 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 161 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
162 | cpu_to_node_map[cpu] = 0; |
163 | } | |
164 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
165 | #define map_cpu_to_node(cpu, node) ({}) | |
166 | #define unmap_cpu_to_node(cpu) ({}) | |
167 | #endif | |
168 | ||
169 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
170 | static int boot_cpu_logical_apicid; |
171 | ||
7cc3959e GOC |
172 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
173 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
174 | ||
a4928cff | 175 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
176 | { |
177 | int cpu = smp_processor_id(); | |
178 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 179 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
180 | |
181 | if (!node_online(node)) | |
182 | node = first_online_node; | |
183 | ||
184 | cpu_2_logical_apicid[cpu] = apicid; | |
185 | map_cpu_to_node(cpu, node); | |
186 | } | |
187 | ||
1481a3dd | 188 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
189 | { |
190 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
191 | unmap_cpu_to_node(cpu); | |
192 | } | |
193 | #else | |
7cc3959e GOC |
194 | #define map_cpu_to_logical_apicid() do {} while (0) |
195 | #endif | |
196 | ||
cb3c8b90 GOC |
197 | /* |
198 | * Report back to the Boot Processor. | |
199 | * Running on AP. | |
200 | */ | |
a4928cff | 201 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
202 | { |
203 | int cpuid, phys_id; | |
204 | unsigned long timeout; | |
205 | ||
206 | /* | |
207 | * If waken up by an INIT in an 82489DX configuration | |
208 | * we may get here before an INIT-deassert IPI reaches | |
209 | * our local APIC. We have to wait for the IPI or we'll | |
210 | * lock up on an APIC access. | |
211 | */ | |
a9659366 IM |
212 | if (apic->wait_for_init_deassert) |
213 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
214 | |
215 | /* | |
216 | * (This works even if the APIC is not enabled.) | |
217 | */ | |
4c9961d5 | 218 | phys_id = read_apic_id(); |
cb3c8b90 | 219 | cpuid = smp_processor_id(); |
c2d1cec1 | 220 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
221 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
222 | phys_id, cpuid); | |
223 | } | |
cfc1b9a6 | 224 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
225 | |
226 | /* | |
227 | * STARTUP IPIs are fragile beasts as they might sometimes | |
228 | * trigger some glue motherboard logic. Complete APIC bus | |
229 | * silence for 1 second, this overestimates the time the | |
230 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
231 | * by a factor of two. This should be enough. | |
232 | */ | |
233 | ||
234 | /* | |
235 | * Waiting 2s total for startup (udelay is not yet working) | |
236 | */ | |
237 | timeout = jiffies + 2*HZ; | |
238 | while (time_before(jiffies, timeout)) { | |
239 | /* | |
240 | * Has the boot CPU finished it's STARTUP sequence? | |
241 | */ | |
c2d1cec1 | 242 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
243 | break; |
244 | cpu_relax(); | |
245 | } | |
246 | ||
247 | if (!time_before(jiffies, timeout)) { | |
248 | panic("%s: CPU%d started up but did not get a callout!\n", | |
249 | __func__, cpuid); | |
250 | } | |
251 | ||
252 | /* | |
253 | * the boot CPU has finished the init stage and is spinning | |
254 | * on callin_map until we finish. We are free to set up this | |
255 | * CPU, first the APIC. (this is probably redundant on most | |
256 | * boards) | |
257 | */ | |
258 | ||
cfc1b9a6 | 259 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
260 | if (apic->smp_callin_clear_local_apic) |
261 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
262 | setup_local_APIC(); |
263 | end_local_APIC_setup(); | |
264 | map_cpu_to_logical_apicid(); | |
265 | ||
9d133e5d SS |
266 | /* |
267 | * Need to setup vector mappings before we enable interrupts. | |
268 | */ | |
36e9e1ea | 269 | setup_vector_irq(smp_processor_id()); |
cb3c8b90 GOC |
270 | /* |
271 | * Get our bogomips. | |
272 | * | |
273 | * Need to enable IRQs because it can take longer and then | |
274 | * the NMI watchdog might kill us. | |
275 | */ | |
276 | local_irq_enable(); | |
277 | calibrate_delay(); | |
278 | local_irq_disable(); | |
cfc1b9a6 | 279 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
280 | |
281 | /* | |
282 | * Save our processor parameters | |
283 | */ | |
284 | smp_store_cpu_info(cpuid); | |
285 | ||
5ef428c4 AK |
286 | /* |
287 | * This must be done before setting cpu_online_mask | |
288 | * or calling notify_cpu_starting. | |
289 | */ | |
290 | set_cpu_sibling_map(raw_smp_processor_id()); | |
291 | wmb(); | |
292 | ||
85257024 PZ |
293 | notify_cpu_starting(cpuid); |
294 | ||
cb3c8b90 GOC |
295 | /* |
296 | * Allow the master to continue. | |
297 | */ | |
c2d1cec1 | 298 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
299 | } |
300 | ||
bbc2ff6a GOC |
301 | /* |
302 | * Activate a secondary processor. | |
303 | */ | |
0ca59dd9 | 304 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
305 | { |
306 | /* | |
307 | * Don't put *anything* before cpu_init(), SMP booting is too | |
308 | * fragile that we want to limit the things done here to the | |
309 | * most necessary things. | |
310 | */ | |
b40827fa BP |
311 | cpu_init(); |
312 | preempt_disable(); | |
313 | smp_callin(); | |
fd89a137 JR |
314 | |
315 | #ifdef CONFIG_X86_32 | |
b40827fa | 316 | /* switch away from the initial page table */ |
fd89a137 JR |
317 | load_cr3(swapper_pg_dir); |
318 | __flush_tlb_all(); | |
319 | #endif | |
320 | ||
bbc2ff6a GOC |
321 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
322 | barrier(); | |
323 | /* | |
324 | * Check TSC synchronization with the BP: | |
325 | */ | |
326 | check_tsc_sync_target(); | |
327 | ||
bbc2ff6a GOC |
328 | /* |
329 | * We need to hold call_lock, so there is no inconsistency | |
330 | * between the time smp_call_function() determines number of | |
331 | * IPI recipients, and the time when the determination is made | |
332 | * for which cpus receive the IPI. Holding this | |
333 | * lock helps us to not include this cpu in a currently in progress | |
334 | * smp_call_function(). | |
d388e5fd EB |
335 | * |
336 | * We need to hold vector_lock so there the set of online cpus | |
337 | * does not change while we are assigning vectors to cpus. Holding | |
338 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 339 | */ |
0cefa5b9 | 340 | ipi_call_lock(); |
d388e5fd | 341 | lock_vector_lock(); |
c2d1cec1 | 342 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 343 | unlock_vector_lock(); |
0cefa5b9 | 344 | ipi_call_unlock(); |
bbc2ff6a | 345 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 346 | x86_platform.nmi_init(); |
bbc2ff6a | 347 | |
0cefa5b9 MS |
348 | /* enable local interrupts */ |
349 | local_irq_enable(); | |
350 | ||
35f720c5 JP |
351 | /* to prevent fake stack check failure in clock setup */ |
352 | boot_init_stack_canary(); | |
0cefa5b9 | 353 | |
736decac | 354 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
355 | |
356 | wmb(); | |
357 | cpu_idle(); | |
358 | } | |
359 | ||
1d89a7f0 GOC |
360 | /* |
361 | * The bootstrap kernel entry code has set these up. Save them for | |
362 | * a given CPU | |
363 | */ | |
364 | ||
365 | void __cpuinit smp_store_cpu_info(int id) | |
366 | { | |
367 | struct cpuinfo_x86 *c = &cpu_data(id); | |
368 | ||
b3d7336d | 369 | *c = boot_cpu_data; |
1d89a7f0 GOC |
370 | c->cpu_index = id; |
371 | if (id != 0) | |
372 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
373 | } |
374 | ||
d4fbe4f0 AH |
375 | static void __cpuinit link_thread_siblings(int cpu1, int cpu2) |
376 | { | |
d4fbe4f0 AH |
377 | cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); |
378 | cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); | |
379 | cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); | |
380 | cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); | |
b3d7336d YL |
381 | cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); |
382 | cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); | |
d4fbe4f0 AH |
383 | } |
384 | ||
1d89a7f0 | 385 | |
768d9505 GC |
386 | void __cpuinit set_cpu_sibling_map(int cpu) |
387 | { | |
388 | int i; | |
389 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
390 | ||
c2d1cec1 | 391 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
392 | |
393 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
394 | for_each_cpu(i, cpu_sibling_setup_mask) { |
395 | struct cpuinfo_x86 *o = &cpu_data(i); | |
396 | ||
d4fbe4f0 AH |
397 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
398 | if (c->phys_proc_id == o->phys_proc_id && | |
399 | c->compute_unit_id == o->compute_unit_id) | |
400 | link_thread_siblings(cpu, i); | |
401 | } else if (c->phys_proc_id == o->phys_proc_id && | |
402 | c->cpu_core_id == o->cpu_core_id) { | |
403 | link_thread_siblings(cpu, i); | |
768d9505 GC |
404 | } |
405 | } | |
406 | } else { | |
c2d1cec1 | 407 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
408 | } |
409 | ||
b3d7336d | 410 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
768d9505 | 411 | |
7b543a53 | 412 | if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { |
c2d1cec1 | 413 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
414 | c->booted_cores = 1; |
415 | return; | |
416 | } | |
417 | ||
c2d1cec1 | 418 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
419 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
420 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
b3d7336d YL |
421 | cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); |
422 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); | |
768d9505 GC |
423 | } |
424 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
425 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
426 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
427 | /* |
428 | * Does this new cpu bringup a new core? | |
429 | */ | |
c2d1cec1 | 430 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
431 | /* |
432 | * for each core in package, increment | |
433 | * the booted_cores for this new cpu | |
434 | */ | |
c2d1cec1 | 435 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
436 | c->booted_cores++; |
437 | /* | |
438 | * increment the core count for all | |
439 | * the other cpus in this package | |
440 | */ | |
441 | if (i != cpu) | |
442 | cpu_data(i).booted_cores++; | |
443 | } else if (i != cpu && !c->booted_cores) | |
444 | c->booted_cores = cpu_data(i).booted_cores; | |
445 | } | |
446 | } | |
447 | } | |
448 | ||
70708a18 | 449 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 450 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
451 | { |
452 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
453 | /* | |
454 | * For perf, we return last level cache shared map. | |
455 | * And for power savings, we return cpu_core_map | |
456 | */ | |
5a925b42 AH |
457 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
458 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 459 | return cpu_core_mask(cpu); |
70708a18 | 460 | else |
b3d7336d | 461 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
462 | } |
463 | ||
a4928cff | 464 | static void impress_friends(void) |
904541e2 GOC |
465 | { |
466 | int cpu; | |
467 | unsigned long bogosum = 0; | |
468 | /* | |
469 | * Allow the user to impress friends. | |
470 | */ | |
cfc1b9a6 | 471 | pr_debug("Before bogomips.\n"); |
904541e2 | 472 | for_each_possible_cpu(cpu) |
c2d1cec1 | 473 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
474 | bogosum += cpu_data(cpu).loops_per_jiffy; |
475 | printk(KERN_INFO | |
476 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 477 | num_online_cpus(), |
904541e2 GOC |
478 | bogosum/(500000/HZ), |
479 | (bogosum/(5000/HZ))%100); | |
480 | ||
cfc1b9a6 | 481 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
482 | } |
483 | ||
569712b2 | 484 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
485 | { |
486 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
487 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
488 | int timeout; | |
489 | u32 status; | |
490 | ||
823b259b | 491 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
492 | |
493 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 494 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
495 | |
496 | /* | |
497 | * Wait for idle. | |
498 | */ | |
499 | status = safe_apic_wait_icr_idle(); | |
500 | if (status) | |
501 | printk(KERN_CONT | |
502 | "a previous APIC delivery may have failed\n"); | |
503 | ||
1b374e4d | 504 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
505 | |
506 | timeout = 0; | |
507 | do { | |
508 | udelay(100); | |
509 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
510 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
511 | ||
512 | switch (status) { | |
513 | case APIC_ICR_RR_VALID: | |
514 | status = apic_read(APIC_RRR); | |
515 | printk(KERN_CONT "%08x\n", status); | |
516 | break; | |
517 | default: | |
518 | printk(KERN_CONT "failed\n"); | |
519 | } | |
520 | } | |
521 | } | |
522 | ||
cb3c8b90 GOC |
523 | /* |
524 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
525 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
526 | * won't ... remember to clear down the APIC, etc later. | |
527 | */ | |
cece3155 | 528 | int __cpuinit |
569712b2 | 529 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
530 | { |
531 | unsigned long send_status, accept_status = 0; | |
532 | int maxlvt; | |
533 | ||
534 | /* Target chip */ | |
cb3c8b90 GOC |
535 | /* Boot on the stack */ |
536 | /* Kick the second */ | |
bdb1a9b6 | 537 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 538 | |
cfc1b9a6 | 539 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
540 | send_status = safe_apic_wait_icr_idle(); |
541 | ||
542 | /* | |
543 | * Give the other CPU some time to accept the IPI. | |
544 | */ | |
545 | udelay(200); | |
569712b2 | 546 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
547 | maxlvt = lapic_get_maxlvt(); |
548 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
549 | apic_write(APIC_ESR, 0); | |
550 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
551 | } | |
cfc1b9a6 | 552 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
553 | |
554 | if (send_status) | |
555 | printk(KERN_ERR "APIC never delivered???\n"); | |
556 | if (accept_status) | |
557 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
558 | ||
559 | return (send_status | accept_status); | |
560 | } | |
cb3c8b90 | 561 | |
cece3155 | 562 | static int __cpuinit |
569712b2 | 563 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
564 | { |
565 | unsigned long send_status, accept_status = 0; | |
566 | int maxlvt, num_starts, j; | |
567 | ||
593f4a78 MR |
568 | maxlvt = lapic_get_maxlvt(); |
569 | ||
cb3c8b90 GOC |
570 | /* |
571 | * Be paranoid about clearing APIC errors. | |
572 | */ | |
573 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
574 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
575 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
576 | apic_read(APIC_ESR); |
577 | } | |
578 | ||
cfc1b9a6 | 579 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
580 | |
581 | /* | |
582 | * Turn INIT on target chip | |
583 | */ | |
cb3c8b90 GOC |
584 | /* |
585 | * Send IPI | |
586 | */ | |
1b374e4d SS |
587 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
588 | phys_apicid); | |
cb3c8b90 | 589 | |
cfc1b9a6 | 590 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
591 | send_status = safe_apic_wait_icr_idle(); |
592 | ||
593 | mdelay(10); | |
594 | ||
cfc1b9a6 | 595 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
596 | |
597 | /* Target chip */ | |
cb3c8b90 | 598 | /* Send IPI */ |
1b374e4d | 599 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 600 | |
cfc1b9a6 | 601 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
602 | send_status = safe_apic_wait_icr_idle(); |
603 | ||
604 | mb(); | |
605 | atomic_set(&init_deasserted, 1); | |
606 | ||
607 | /* | |
608 | * Should we send STARTUP IPIs ? | |
609 | * | |
610 | * Determine this based on the APIC version. | |
611 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
612 | */ | |
613 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
614 | num_starts = 2; | |
615 | else | |
616 | num_starts = 0; | |
617 | ||
618 | /* | |
619 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
620 | * target processor state. | |
621 | */ | |
622 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 623 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
624 | |
625 | /* | |
626 | * Run STARTUP IPI loop. | |
627 | */ | |
cfc1b9a6 | 628 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 629 | |
cb3c8b90 | 630 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 631 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
632 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
633 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 634 | apic_read(APIC_ESR); |
cfc1b9a6 | 635 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
636 | |
637 | /* | |
638 | * STARTUP IPI | |
639 | */ | |
640 | ||
641 | /* Target chip */ | |
cb3c8b90 GOC |
642 | /* Boot on the stack */ |
643 | /* Kick the second */ | |
1b374e4d SS |
644 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
645 | phys_apicid); | |
cb3c8b90 GOC |
646 | |
647 | /* | |
648 | * Give the other CPU some time to accept the IPI. | |
649 | */ | |
650 | udelay(300); | |
651 | ||
cfc1b9a6 | 652 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 653 | |
cfc1b9a6 | 654 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
655 | send_status = safe_apic_wait_icr_idle(); |
656 | ||
657 | /* | |
658 | * Give the other CPU some time to accept the IPI. | |
659 | */ | |
660 | udelay(200); | |
593f4a78 | 661 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 662 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
663 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
664 | if (send_status || accept_status) | |
665 | break; | |
666 | } | |
cfc1b9a6 | 667 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
668 | |
669 | if (send_status) | |
670 | printk(KERN_ERR "APIC never delivered???\n"); | |
671 | if (accept_status) | |
672 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
673 | ||
674 | return (send_status | accept_status); | |
675 | } | |
cb3c8b90 GOC |
676 | |
677 | struct create_idle { | |
678 | struct work_struct work; | |
679 | struct task_struct *idle; | |
680 | struct completion done; | |
681 | int cpu; | |
682 | }; | |
683 | ||
684 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
685 | { | |
686 | struct create_idle *c_idle = | |
687 | container_of(work, struct create_idle, work); | |
688 | ||
689 | c_idle->idle = fork_idle(c_idle->cpu); | |
690 | complete(&c_idle->done); | |
691 | } | |
692 | ||
2eaad1fd MT |
693 | /* reduce the number of lines printed when booting a large cpu count system */ |
694 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
695 | { | |
696 | static int current_node = -1; | |
4adc8b71 | 697 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
698 | |
699 | if (system_state == SYSTEM_BOOTING) { | |
700 | if (node != current_node) { | |
701 | if (current_node > (-1)) | |
702 | pr_cont(" Ok.\n"); | |
703 | current_node = node; | |
704 | pr_info("Booting Node %3d, Processors ", node); | |
705 | } | |
706 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
707 | return; | |
708 | } else | |
709 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
710 | node, cpu, apicid); | |
711 | } | |
712 | ||
cb3c8b90 GOC |
713 | /* |
714 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
715 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
716 | * Returns zero if CPU booted OK, else error code from |
717 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 718 | */ |
ab6fb7c0 | 719 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
720 | { |
721 | unsigned long boot_error = 0; | |
cb3c8b90 | 722 | unsigned long start_ip; |
ab6fb7c0 | 723 | int timeout; |
cb3c8b90 | 724 | struct create_idle c_idle = { |
ab6fb7c0 IM |
725 | .cpu = cpu, |
726 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 727 | }; |
ab6fb7c0 | 728 | |
ca1cab37 | 729 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 730 | |
cb3c8b90 GOC |
731 | alternatives_smp_switch(1); |
732 | ||
733 | c_idle.idle = get_idle_for_cpu(cpu); | |
734 | ||
735 | /* | |
736 | * We can't use kernel_thread since we must avoid to | |
737 | * reschedule the child. | |
738 | */ | |
739 | if (c_idle.idle) { | |
740 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
741 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
742 | init_idle(c_idle.idle, cpu); | |
743 | goto do_rest; | |
744 | } | |
745 | ||
d7a7c573 SS |
746 | schedule_work(&c_idle.work); |
747 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
748 | |
749 | if (IS_ERR(c_idle.idle)) { | |
750 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 751 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
752 | return PTR_ERR(c_idle.idle); |
753 | } | |
754 | ||
755 | set_idle_for_cpu(cpu, c_idle.idle); | |
756 | do_rest: | |
cb3c8b90 | 757 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 758 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 759 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
760 | irq_ctx_init(cpu); |
761 | #else | |
cb3c8b90 | 762 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 763 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
764 | per_cpu(kernel_stack, cpu) = |
765 | (unsigned long)task_stack_page(c_idle.idle) - | |
766 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 767 | #endif |
a939098a | 768 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 769 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 770 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
771 | |
772 | /* start_ip had better be page-aligned! */ | |
773 | start_ip = setup_trampoline(); | |
774 | ||
2eaad1fd MT |
775 | /* So we see what's up */ |
776 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
777 | |
778 | /* | |
779 | * This grunge runs the startup process for | |
780 | * the targeted processor. | |
781 | */ | |
782 | ||
783 | atomic_set(&init_deasserted, 0); | |
784 | ||
34d05591 | 785 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 786 | |
cfc1b9a6 | 787 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 788 | |
34d05591 JS |
789 | smpboot_setup_warm_reset_vector(start_ip); |
790 | /* | |
791 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
792 | */ |
793 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
794 | apic_write(APIC_ESR, 0); | |
795 | apic_read(APIC_ESR); | |
796 | } | |
34d05591 | 797 | } |
cb3c8b90 | 798 | |
cb3c8b90 | 799 | /* |
1f5bcabf IM |
800 | * Kick the secondary CPU. Use the method in the APIC driver |
801 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 802 | */ |
1f5bcabf IM |
803 | if (apic->wakeup_secondary_cpu) |
804 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
805 | else | |
806 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
807 | |
808 | if (!boot_error) { | |
809 | /* | |
810 | * allow APs to start initializing. | |
811 | */ | |
cfc1b9a6 | 812 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 813 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 814 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
815 | |
816 | /* | |
817 | * Wait 5s total for a response | |
818 | */ | |
819 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 820 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
821 | break; /* It has booted */ |
822 | udelay(100); | |
68f202e4 SS |
823 | /* |
824 | * Allow other tasks to run while we wait for the | |
825 | * AP to come online. This also gives a chance | |
826 | * for the MTRR work(triggered by the AP coming online) | |
827 | * to be completed in the stop machine context. | |
828 | */ | |
829 | schedule(); | |
cb3c8b90 GOC |
830 | } |
831 | ||
2eaad1fd MT |
832 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
833 | pr_debug("CPU%d: has booted.\n", cpu); | |
834 | else { | |
cb3c8b90 GOC |
835 | boot_error = 1; |
836 | if (*((volatile unsigned char *)trampoline_base) | |
837 | == 0xA5) | |
838 | /* trampoline started but...? */ | |
2eaad1fd | 839 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
840 | else |
841 | /* trampoline code not run */ | |
2eaad1fd | 842 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
843 | if (apic->inquire_remote_apic) |
844 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
845 | } |
846 | } | |
1a51e3a0 | 847 | |
cb3c8b90 GOC |
848 | if (boot_error) { |
849 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 850 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
851 | |
852 | /* was set by do_boot_cpu() */ | |
853 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
854 | ||
855 | /* was set by cpu_init() */ | |
856 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
857 | ||
858 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
859 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
860 | } | |
861 | ||
862 | /* mark "stuck" area as not stuck */ | |
863 | *((volatile unsigned long *)trampoline_base) = 0; | |
864 | ||
02421f98 YL |
865 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
866 | /* | |
867 | * Cleanup possible dangling ends... | |
868 | */ | |
869 | smpboot_restore_warm_reset_vector(); | |
870 | } | |
63d38198 | 871 | |
dc186ad7 | 872 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
873 | return boot_error; |
874 | } | |
875 | ||
876 | int __cpuinit native_cpu_up(unsigned int cpu) | |
877 | { | |
a21769a4 | 878 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
879 | unsigned long flags; |
880 | int err; | |
881 | ||
882 | WARN_ON(irqs_disabled()); | |
883 | ||
cfc1b9a6 | 884 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
885 | |
886 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
887 | !physid_isset(apicid, phys_cpu_present_map)) { | |
888 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
889 | return -EINVAL; | |
890 | } | |
891 | ||
892 | /* | |
893 | * Already booted CPU? | |
894 | */ | |
c2d1cec1 | 895 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 896 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
897 | return -ENOSYS; |
898 | } | |
899 | ||
900 | /* | |
901 | * Save current MTRR state in case it was changed since early boot | |
902 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
903 | */ | |
904 | mtrr_save_state(); | |
905 | ||
906 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
907 | ||
cb3c8b90 | 908 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 909 | if (err) { |
cfc1b9a6 | 910 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 911 | return -EIO; |
cb3c8b90 GOC |
912 | } |
913 | ||
914 | /* | |
915 | * Check TSC synchronization with the AP (keep irqs disabled | |
916 | * while doing so): | |
917 | */ | |
918 | local_irq_save(flags); | |
919 | check_tsc_sync_source(cpu); | |
920 | local_irq_restore(flags); | |
921 | ||
7c04e64a | 922 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
923 | cpu_relax(); |
924 | touch_nmi_watchdog(); | |
925 | } | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
8aef135c GOC |
930 | /* |
931 | * Fall back to non SMP mode after errors. | |
932 | * | |
933 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
934 | */ | |
935 | static __init void disable_smp(void) | |
936 | { | |
4f062896 RR |
937 | init_cpu_present(cpumask_of(0)); |
938 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 939 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 940 | |
8aef135c | 941 | if (smp_found_config) |
b6df1b8b | 942 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 943 | else |
b6df1b8b | 944 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 945 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
946 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
947 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
948 | } |
949 | ||
950 | /* | |
951 | * Various sanity checks. | |
952 | */ | |
953 | static int __init smp_sanity_check(unsigned max_cpus) | |
954 | { | |
ac23d4ee | 955 | preempt_disable(); |
a58f03b0 | 956 | |
1ff2f20d | 957 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
958 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
959 | unsigned int cpu; | |
960 | unsigned nr; | |
961 | ||
962 | printk(KERN_WARNING | |
963 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 964 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
965 | |
966 | nr = 0; | |
967 | for_each_present_cpu(cpu) { | |
968 | if (nr >= 8) | |
c2d1cec1 | 969 | set_cpu_present(cpu, false); |
a58f03b0 YL |
970 | nr++; |
971 | } | |
972 | ||
973 | nr = 0; | |
974 | for_each_possible_cpu(cpu) { | |
975 | if (nr >= 8) | |
c2d1cec1 | 976 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
977 | nr++; |
978 | } | |
979 | ||
980 | nr_cpu_ids = 8; | |
981 | } | |
982 | #endif | |
983 | ||
8aef135c | 984 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
985 | printk(KERN_WARNING |
986 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
987 | hard_smp_processor_id()); | |
988 | ||
8aef135c GOC |
989 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
990 | } | |
991 | ||
992 | /* | |
993 | * If we couldn't find an SMP configuration at boot time, | |
994 | * get out of here now! | |
995 | */ | |
996 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 997 | preempt_enable(); |
8aef135c GOC |
998 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
999 | disable_smp(); | |
1000 | if (APIC_init_uniprocessor()) | |
1001 | printk(KERN_NOTICE "Local APIC not detected." | |
1002 | " Using dummy APIC emulation.\n"); | |
1003 | return -1; | |
1004 | } | |
1005 | ||
1006 | /* | |
1007 | * Should not be necessary because the MP table should list the boot | |
1008 | * CPU too, but we do it for the sake of robustness anyway. | |
1009 | */ | |
a27a6210 | 1010 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
1011 | printk(KERN_NOTICE |
1012 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1013 | boot_cpu_physical_apicid); | |
1014 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1015 | } | |
ac23d4ee | 1016 | preempt_enable(); |
8aef135c GOC |
1017 | |
1018 | /* | |
1019 | * If we couldn't find a local APIC, then get out of here now! | |
1020 | */ | |
1021 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1022 | !cpu_has_apic) { | |
103428e5 CG |
1023 | if (!disable_apic) { |
1024 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1025 | boot_cpu_physical_apicid); | |
1026 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 1027 | "(tell your hw vendor)\n"); |
103428e5 | 1028 | } |
8aef135c | 1029 | smpboot_clear_io_apic(); |
65a4e574 | 1030 | arch_disable_smp_support(); |
8aef135c GOC |
1031 | return -1; |
1032 | } | |
1033 | ||
1034 | verify_local_APIC(); | |
1035 | ||
1036 | /* | |
1037 | * If SMP should be disabled, then really disable it! | |
1038 | */ | |
1039 | if (!max_cpus) { | |
73d08e63 | 1040 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1041 | smpboot_clear_io_apic(); |
d54db1ac | 1042 | |
e90955c2 | 1043 | connect_bsp_APIC(); |
e90955c2 JB |
1044 | setup_local_APIC(); |
1045 | end_local_APIC_setup(); | |
8aef135c GOC |
1046 | return -1; |
1047 | } | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | static void __init smp_cpu_index_default(void) | |
1053 | { | |
1054 | int i; | |
1055 | struct cpuinfo_x86 *c; | |
1056 | ||
7c04e64a | 1057 | for_each_possible_cpu(i) { |
8aef135c GOC |
1058 | c = &cpu_data(i); |
1059 | /* mark all to hotplug */ | |
9628937d | 1060 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1061 | } |
1062 | } | |
1063 | ||
1064 | /* | |
1065 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1066 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1067 | */ | |
1068 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1069 | { | |
7ad728f9 RR |
1070 | unsigned int i; |
1071 | ||
deef3250 | 1072 | preempt_disable(); |
8aef135c | 1073 | smp_cpu_index_default(); |
7b543a53 | 1074 | memcpy(__this_cpu_ptr(&cpu_info), &boot_cpu_data, sizeof(cpu_info)); |
c2d1cec1 | 1075 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1076 | mb(); |
1077 | /* | |
1078 | * Setup boot CPU information | |
1079 | */ | |
1080 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1081 | #ifdef CONFIG_X86_32 |
8aef135c | 1082 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1083 | #endif |
8aef135c | 1084 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1085 | for_each_possible_cpu(i) { |
79f55997 LZ |
1086 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1087 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1088 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1089 | } |
8aef135c GOC |
1090 | set_cpu_sibling_map(0); |
1091 | ||
6e1cb38a | 1092 | |
8aef135c GOC |
1093 | if (smp_sanity_check(max_cpus) < 0) { |
1094 | printk(KERN_INFO "SMP disabled\n"); | |
1095 | disable_smp(); | |
deef3250 | 1096 | goto out; |
8aef135c GOC |
1097 | } |
1098 | ||
fa47f7e5 SS |
1099 | default_setup_apic_routing(); |
1100 | ||
ac23d4ee | 1101 | preempt_disable(); |
4c9961d5 | 1102 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1103 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1104 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1105 | /* Or can we switch back to PIC here? */ |
1106 | } | |
ac23d4ee | 1107 | preempt_enable(); |
8aef135c | 1108 | |
8aef135c | 1109 | connect_bsp_APIC(); |
b5841765 | 1110 | |
8aef135c GOC |
1111 | /* |
1112 | * Switch from PIC to APIC mode. | |
1113 | */ | |
1114 | setup_local_APIC(); | |
1115 | ||
8aef135c GOC |
1116 | /* |
1117 | * Enable IO APIC before setting up error vector | |
1118 | */ | |
1119 | if (!skip_ioapic_setup && nr_ioapics) | |
1120 | enable_IO_APIC(); | |
88d0f550 | 1121 | |
8aef135c GOC |
1122 | end_local_APIC_setup(); |
1123 | ||
1124 | map_cpu_to_logical_apicid(); | |
1125 | ||
d83093b5 IM |
1126 | if (apic->setup_portio_remap) |
1127 | apic->setup_portio_remap(); | |
8aef135c GOC |
1128 | |
1129 | smpboot_setup_io_apic(); | |
1130 | /* | |
1131 | * Set up local APIC timer on boot CPU. | |
1132 | */ | |
1133 | ||
1134 | printk(KERN_INFO "CPU%d: ", 0); | |
1135 | print_cpu_info(&cpu_data(0)); | |
736decac | 1136 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1137 | |
1138 | if (is_uv_system()) | |
1139 | uv_system_init(); | |
d0af9eed SS |
1140 | |
1141 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1142 | out: |
1143 | preempt_enable(); | |
8aef135c | 1144 | } |
d0af9eed | 1145 | |
3fb82d56 SS |
1146 | void arch_disable_nonboot_cpus_begin(void) |
1147 | { | |
1148 | /* | |
1149 | * Avoid the smp alternatives switch during the disable_nonboot_cpus(). | |
1150 | * In the suspend path, we will be back in the SMP mode shortly anyways. | |
1151 | */ | |
1152 | skip_smp_alternatives = true; | |
1153 | } | |
1154 | ||
1155 | void arch_disable_nonboot_cpus_end(void) | |
1156 | { | |
1157 | skip_smp_alternatives = false; | |
1158 | } | |
1159 | ||
d0af9eed SS |
1160 | void arch_enable_nonboot_cpus_begin(void) |
1161 | { | |
1162 | set_mtrr_aps_delayed_init(); | |
1163 | } | |
1164 | ||
1165 | void arch_enable_nonboot_cpus_end(void) | |
1166 | { | |
1167 | mtrr_aps_init(); | |
1168 | } | |
1169 | ||
a8db8453 GOC |
1170 | /* |
1171 | * Early setup to make printk work. | |
1172 | */ | |
1173 | void __init native_smp_prepare_boot_cpu(void) | |
1174 | { | |
1175 | int me = smp_processor_id(); | |
552be871 | 1176 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1177 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1178 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1179 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1180 | } | |
1181 | ||
83f7eb9c GOC |
1182 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1183 | { | |
cfc1b9a6 | 1184 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1185 | |
1186 | impress_friends(); | |
83f7eb9c GOC |
1187 | #ifdef CONFIG_X86_IO_APIC |
1188 | setup_ioapic_dest(); | |
1189 | #endif | |
d0af9eed | 1190 | mtrr_aps_init(); |
83f7eb9c GOC |
1191 | } |
1192 | ||
3b11ce7f MT |
1193 | static int __initdata setup_possible_cpus = -1; |
1194 | static int __init _setup_possible_cpus(char *str) | |
1195 | { | |
1196 | get_option(&str, &setup_possible_cpus); | |
1197 | return 0; | |
1198 | } | |
1199 | early_param("possible_cpus", _setup_possible_cpus); | |
1200 | ||
1201 | ||
68a1c3f8 | 1202 | /* |
4f062896 | 1203 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1204 | * are onlined, or offlined. The reason is per-cpu data-structures |
1205 | * are allocated by some modules at init time, and dont expect to | |
1206 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1207 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1208 | * In case when cpu_hotplug is not compiled, then we resort to current |
1209 | * behaviour, which is cpu_possible == cpu_present. | |
1210 | * - Ashok Raj | |
1211 | * | |
1212 | * Three ways to find out the number of additional hotplug CPUs: | |
1213 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1214 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1215 | * - Otherwise don't reserve additional CPUs. |
1216 | * We do this because additional CPUs waste a lot of memory. | |
1217 | * -AK | |
1218 | */ | |
1219 | __init void prefill_possible_map(void) | |
1220 | { | |
cb48bb59 | 1221 | int i, possible; |
68a1c3f8 | 1222 | |
329513a3 YL |
1223 | /* no processor from mptable or madt */ |
1224 | if (!num_processors) | |
1225 | num_processors = 1; | |
1226 | ||
5f2eb550 JB |
1227 | i = setup_max_cpus ?: 1; |
1228 | if (setup_possible_cpus == -1) { | |
1229 | possible = num_processors; | |
1230 | #ifdef CONFIG_HOTPLUG_CPU | |
1231 | if (setup_max_cpus) | |
1232 | possible += disabled_cpus; | |
1233 | #else | |
1234 | if (possible > i) | |
1235 | possible = i; | |
1236 | #endif | |
1237 | } else | |
3b11ce7f MT |
1238 | possible = setup_possible_cpus; |
1239 | ||
730cf272 MT |
1240 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1241 | ||
2b633e3f YL |
1242 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1243 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1244 | printk(KERN_WARNING |
1245 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1246 | possible, nr_cpu_ids); |
1247 | possible = nr_cpu_ids; | |
3b11ce7f | 1248 | } |
68a1c3f8 | 1249 | |
5f2eb550 JB |
1250 | #ifdef CONFIG_HOTPLUG_CPU |
1251 | if (!setup_max_cpus) | |
1252 | #endif | |
1253 | if (possible > i) { | |
1254 | printk(KERN_WARNING | |
1255 | "%d Processors exceeds max_cpus limit of %u\n", | |
1256 | possible, setup_max_cpus); | |
1257 | possible = i; | |
1258 | } | |
1259 | ||
68a1c3f8 GC |
1260 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1261 | possible, max_t(int, possible - num_processors, 0)); | |
1262 | ||
1263 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1264 | set_cpu_possible(i, true); |
5f2eb550 JB |
1265 | for (; i < NR_CPUS; i++) |
1266 | set_cpu_possible(i, false); | |
3461b0af MT |
1267 | |
1268 | nr_cpu_ids = possible; | |
68a1c3f8 | 1269 | } |
69c18c15 | 1270 | |
14adf855 CE |
1271 | #ifdef CONFIG_HOTPLUG_CPU |
1272 | ||
1273 | static void remove_siblinginfo(int cpu) | |
1274 | { | |
1275 | int sibling; | |
1276 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1277 | ||
c2d1cec1 MT |
1278 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1279 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1280 | /*/ |
1281 | * last thread sibling in this cpu core going down | |
1282 | */ | |
c2d1cec1 | 1283 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1284 | cpu_data(sibling).booted_cores--; |
1285 | } | |
1286 | ||
c2d1cec1 MT |
1287 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1288 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1289 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1290 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1291 | c->phys_proc_id = 0; |
1292 | c->cpu_core_id = 0; | |
c2d1cec1 | 1293 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1294 | } |
1295 | ||
69c18c15 GC |
1296 | static void __ref remove_cpu_from_maps(int cpu) |
1297 | { | |
c2d1cec1 MT |
1298 | set_cpu_online(cpu, false); |
1299 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1300 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1301 | /* was set by cpu_init() */ |
c2d1cec1 | 1302 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1303 | numa_remove_cpu(cpu); |
69c18c15 GC |
1304 | } |
1305 | ||
8227dce7 | 1306 | void cpu_disable_common(void) |
69c18c15 GC |
1307 | { |
1308 | int cpu = smp_processor_id(); | |
69c18c15 | 1309 | |
69c18c15 GC |
1310 | remove_siblinginfo(cpu); |
1311 | ||
1312 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1313 | lock_vector_lock(); |
69c18c15 | 1314 | remove_cpu_from_maps(cpu); |
d388e5fd | 1315 | unlock_vector_lock(); |
d7b381bb | 1316 | fixup_irqs(); |
8227dce7 AN |
1317 | } |
1318 | ||
1319 | int native_cpu_disable(void) | |
1320 | { | |
1321 | int cpu = smp_processor_id(); | |
1322 | ||
1323 | /* | |
1324 | * Perhaps use cpufreq to drop frequency, but that could go | |
1325 | * into generic code. | |
1326 | * | |
1327 | * We won't take down the boot processor on i386 due to some | |
1328 | * interrupts only being able to be serviced by the BSP. | |
1329 | * Especially so if we're not using an IOAPIC -zwane | |
1330 | */ | |
1331 | if (cpu == 0) | |
1332 | return -EBUSY; | |
1333 | ||
8227dce7 AN |
1334 | clear_local_APIC(); |
1335 | ||
1336 | cpu_disable_common(); | |
69c18c15 GC |
1337 | return 0; |
1338 | } | |
1339 | ||
93be71b6 | 1340 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1341 | { |
1342 | /* We don't do anything here: idle task is faking death itself. */ | |
1343 | unsigned int i; | |
1344 | ||
1345 | for (i = 0; i < 10; i++) { | |
1346 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1347 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1348 | if (system_state == SYSTEM_RUNNING) |
1349 | pr_info("CPU %u is now offline\n", cpu); | |
1350 | ||
69c18c15 GC |
1351 | if (1 == num_online_cpus()) |
1352 | alternatives_smp_switch(0); | |
1353 | return; | |
1354 | } | |
1355 | msleep(100); | |
1356 | } | |
2eaad1fd | 1357 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1358 | } |
a21f5d88 AN |
1359 | |
1360 | void play_dead_common(void) | |
1361 | { | |
1362 | idle_task_exit(); | |
1363 | reset_lazy_tlbstate(); | |
07bbc16a | 1364 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1365 | |
1366 | mb(); | |
1367 | /* Ack it */ | |
0a3aee0d | 1368 | __this_cpu_write(cpu_state, CPU_DEAD); |
a21f5d88 AN |
1369 | |
1370 | /* | |
1371 | * With physical CPU hotplug, we should halt the cpu | |
1372 | */ | |
1373 | local_irq_disable(); | |
1374 | } | |
1375 | ||
ea530692 PA |
1376 | /* |
1377 | * We need to flush the caches before going to sleep, lest we have | |
1378 | * dirty data in our caches when we come back up. | |
1379 | */ | |
1380 | static inline void mwait_play_dead(void) | |
1381 | { | |
1382 | unsigned int eax, ebx, ecx, edx; | |
1383 | unsigned int highest_cstate = 0; | |
1384 | unsigned int highest_subcstate = 0; | |
1385 | int i; | |
ce5f6824 | 1386 | void *mwait_ptr; |
93789b32 | 1387 | struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); |
ea530692 | 1388 | |
93789b32 | 1389 | if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c))) |
ea530692 | 1390 | return; |
7b543a53 | 1391 | if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH)) |
ce5f6824 | 1392 | return; |
7b543a53 | 1393 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1394 | return; |
1395 | ||
1396 | eax = CPUID_MWAIT_LEAF; | |
1397 | ecx = 0; | |
1398 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1399 | ||
1400 | /* | |
1401 | * eax will be 0 if EDX enumeration is not valid. | |
1402 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1403 | */ | |
1404 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1405 | eax = 0; | |
1406 | } else { | |
1407 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1408 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1409 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1410 | highest_cstate = i; | |
1411 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1412 | } | |
1413 | } | |
1414 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1415 | (highest_subcstate - 1); | |
1416 | } | |
1417 | ||
ce5f6824 PA |
1418 | /* |
1419 | * This should be a memory location in a cache line which is | |
1420 | * unlikely to be touched by other processors. The actual | |
1421 | * content is immaterial as it is not actually modified in any way. | |
1422 | */ | |
1423 | mwait_ptr = ¤t_thread_info()->flags; | |
1424 | ||
a68e5c94 PA |
1425 | wbinvd(); |
1426 | ||
ea530692 | 1427 | while (1) { |
ce5f6824 PA |
1428 | /* |
1429 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1430 | * the Xeon 7400 series. It's not clear it is actually | |
1431 | * needed, but it should be harmless in either case. | |
1432 | * The WBINVD is insufficient due to the spurious-wakeup | |
1433 | * case where we return around the loop. | |
1434 | */ | |
1435 | clflush(mwait_ptr); | |
1436 | __monitor(mwait_ptr, 0, 0); | |
ea530692 PA |
1437 | mb(); |
1438 | __mwait(eax, 0); | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | static inline void hlt_play_dead(void) | |
1443 | { | |
7b543a53 | 1444 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1445 | wbinvd(); |
1446 | ||
ea530692 | 1447 | while (1) { |
ea530692 PA |
1448 | native_halt(); |
1449 | } | |
1450 | } | |
1451 | ||
a21f5d88 AN |
1452 | void native_play_dead(void) |
1453 | { | |
1454 | play_dead_common(); | |
86886e55 | 1455 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1456 | |
1457 | mwait_play_dead(); /* Only returns on failure */ | |
1458 | hlt_play_dead(); | |
a21f5d88 AN |
1459 | } |
1460 | ||
69c18c15 | 1461 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1462 | int native_cpu_disable(void) |
69c18c15 GC |
1463 | { |
1464 | return -ENOSYS; | |
1465 | } | |
1466 | ||
93be71b6 | 1467 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1468 | { |
1469 | /* We said "no" in __cpu_disable */ | |
1470 | BUG(); | |
1471 | } | |
a21f5d88 AN |
1472 | |
1473 | void native_play_dead(void) | |
1474 | { | |
1475 | BUG(); | |
1476 | } | |
1477 | ||
68a1c3f8 | 1478 | #endif |