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Commit | Line | Data |
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4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
55 | #include <asm/smp.h> | |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
62 | #include <asm/nmi.h> | |
bbc2ff6a | 63 | #include <asm/vmi.h> |
34d05591 | 64 | #include <asm/genapic.h> |
cb3c8b90 | 65 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 66 | |
f6bc4029 | 67 | #include <mach_apic.h> |
cb3c8b90 GOC |
68 | #include <mach_wakecpu.h> |
69 | #include <smpboot_hooks.h> | |
70 | ||
acbb6734 GOC |
71 | /* |
72 | * FIXME: For x86_64, those are defined in other files. But moving them here, | |
73 | * would make the setup areas dependent on smp, which is a loss. When we | |
74 | * integrate apic between arches, we can probably do a better job, but | |
75 | * right now, they'll stay here -- glommer | |
76 | */ | |
708650af | 77 | |
acbb6734 GOC |
78 | /* which logical CPU number maps to which CPU (physical APIC ID) */ |
79 | u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata = | |
80 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
81 | void *x86_cpu_to_apicid_early_ptr; | |
acbb6734 GOC |
82 | |
83 | u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata | |
84 | = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
85 | void *x86_bios_cpu_apicid_early_ptr; | |
40014bac | 86 | |
16ecf7a4 | 87 | #ifdef CONFIG_X86_32 |
4cedb334 | 88 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 89 | static int low_mappings; |
acbb6734 GOC |
90 | #endif |
91 | ||
a8db8453 GOC |
92 | /* State of each CPU */ |
93 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
94 | ||
cb3c8b90 GOC |
95 | /* Store all idle threads, this can be reused instead of creating |
96 | * a new thread. Also avoids complicated thread destroy functionality | |
97 | * for idle threads. | |
98 | */ | |
99 | #ifdef CONFIG_HOTPLUG_CPU | |
100 | /* | |
101 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
102 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
103 | */ | |
104 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
105 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
106 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
107 | #else | |
108 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
109 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
110 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
111 | #endif | |
f6bc4029 | 112 | |
a355352b GC |
113 | /* Number of siblings per CPU package */ |
114 | int smp_num_siblings = 1; | |
115 | EXPORT_SYMBOL(smp_num_siblings); | |
116 | ||
117 | /* Last level cache ID of each logical CPU */ | |
118 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
119 | ||
120 | /* bitmap of online cpus */ | |
121 | cpumask_t cpu_online_map __read_mostly; | |
122 | EXPORT_SYMBOL(cpu_online_map); | |
123 | ||
124 | cpumask_t cpu_callin_map; | |
125 | cpumask_t cpu_callout_map; | |
126 | cpumask_t cpu_possible_map; | |
127 | EXPORT_SYMBOL(cpu_possible_map); | |
128 | ||
129 | /* representing HT siblings of each logical CPU */ | |
130 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
131 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
132 | ||
133 | /* representing HT and core siblings of each logical CPU */ | |
134 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
135 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
136 | ||
137 | /* Per CPU bogomips and other parameters */ | |
138 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
139 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 140 | |
cb3c8b90 GOC |
141 | static atomic_t init_deasserted; |
142 | ||
8aef135c GOC |
143 | static int boot_cpu_logical_apicid; |
144 | ||
768d9505 GC |
145 | /* representing cpus for which sibling maps can be computed */ |
146 | static cpumask_t cpu_sibling_setup_map; | |
147 | ||
1d89a7f0 GOC |
148 | /* Set if we find a B stepping CPU */ |
149 | int __cpuinitdata smp_b_stepping; | |
1d89a7f0 | 150 | |
7cc3959e GOC |
151 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
152 | ||
153 | /* which logical CPUs are on which nodes */ | |
154 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
155 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
156 | EXPORT_SYMBOL(node_to_cpumask_map); | |
157 | /* which node each logical CPU is on */ | |
158 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
159 | EXPORT_SYMBOL(cpu_to_node_map); | |
160 | ||
161 | /* set up a mapping between cpu and node. */ | |
162 | static void map_cpu_to_node(int cpu, int node) | |
163 | { | |
164 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
165 | cpu_set(cpu, node_to_cpumask_map[node]); | |
166 | cpu_to_node_map[cpu] = node; | |
167 | } | |
168 | ||
169 | /* undo a mapping between cpu and node. */ | |
170 | static void unmap_cpu_to_node(int cpu) | |
171 | { | |
172 | int node; | |
173 | ||
174 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
175 | for (node = 0; node < MAX_NUMNODES; node++) | |
176 | cpu_clear(cpu, node_to_cpumask_map[node]); | |
177 | cpu_to_node_map[cpu] = 0; | |
178 | } | |
179 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
180 | #define map_cpu_to_node(cpu, node) ({}) | |
181 | #define unmap_cpu_to_node(cpu) ({}) | |
182 | #endif | |
183 | ||
184 | #ifdef CONFIG_X86_32 | |
185 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = | |
186 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
187 | ||
a4928cff | 188 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
189 | { |
190 | int cpu = smp_processor_id(); | |
191 | int apicid = logical_smp_processor_id(); | |
192 | int node = apicid_to_node(apicid); | |
193 | ||
194 | if (!node_online(node)) | |
195 | node = first_online_node; | |
196 | ||
197 | cpu_2_logical_apicid[cpu] = apicid; | |
198 | map_cpu_to_node(cpu, node); | |
199 | } | |
200 | ||
a4928cff | 201 | static void unmap_cpu_to_logical_apicid(int cpu) |
7cc3959e GOC |
202 | { |
203 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
204 | unmap_cpu_to_node(cpu); | |
205 | } | |
206 | #else | |
207 | #define unmap_cpu_to_logical_apicid(cpu) do {} while (0) | |
208 | #define map_cpu_to_logical_apicid() do {} while (0) | |
209 | #endif | |
210 | ||
cb3c8b90 GOC |
211 | /* |
212 | * Report back to the Boot Processor. | |
213 | * Running on AP. | |
214 | */ | |
a4928cff | 215 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
216 | { |
217 | int cpuid, phys_id; | |
218 | unsigned long timeout; | |
219 | ||
220 | /* | |
221 | * If waken up by an INIT in an 82489DX configuration | |
222 | * we may get here before an INIT-deassert IPI reaches | |
223 | * our local APIC. We have to wait for the IPI or we'll | |
224 | * lock up on an APIC access. | |
225 | */ | |
226 | wait_for_init_deassert(&init_deasserted); | |
227 | ||
228 | /* | |
229 | * (This works even if the APIC is not enabled.) | |
230 | */ | |
05f2d12c | 231 | phys_id = GET_APIC_ID(read_apic_id()); |
cb3c8b90 GOC |
232 | cpuid = smp_processor_id(); |
233 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
234 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, | |
235 | phys_id, cpuid); | |
236 | } | |
237 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
238 | ||
239 | /* | |
240 | * STARTUP IPIs are fragile beasts as they might sometimes | |
241 | * trigger some glue motherboard logic. Complete APIC bus | |
242 | * silence for 1 second, this overestimates the time the | |
243 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
244 | * by a factor of two. This should be enough. | |
245 | */ | |
246 | ||
247 | /* | |
248 | * Waiting 2s total for startup (udelay is not yet working) | |
249 | */ | |
250 | timeout = jiffies + 2*HZ; | |
251 | while (time_before(jiffies, timeout)) { | |
252 | /* | |
253 | * Has the boot CPU finished it's STARTUP sequence? | |
254 | */ | |
255 | if (cpu_isset(cpuid, cpu_callout_map)) | |
256 | break; | |
257 | cpu_relax(); | |
258 | } | |
259 | ||
260 | if (!time_before(jiffies, timeout)) { | |
261 | panic("%s: CPU%d started up but did not get a callout!\n", | |
262 | __func__, cpuid); | |
263 | } | |
264 | ||
265 | /* | |
266 | * the boot CPU has finished the init stage and is spinning | |
267 | * on callin_map until we finish. We are free to set up this | |
268 | * CPU, first the APIC. (this is probably redundant on most | |
269 | * boards) | |
270 | */ | |
271 | ||
272 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
273 | smp_callin_clear_local_apic(); | |
274 | setup_local_APIC(); | |
275 | end_local_APIC_setup(); | |
276 | map_cpu_to_logical_apicid(); | |
277 | ||
278 | /* | |
279 | * Get our bogomips. | |
280 | * | |
281 | * Need to enable IRQs because it can take longer and then | |
282 | * the NMI watchdog might kill us. | |
283 | */ | |
284 | local_irq_enable(); | |
285 | calibrate_delay(); | |
286 | local_irq_disable(); | |
287 | Dprintk("Stack at about %p\n", &cpuid); | |
288 | ||
289 | /* | |
290 | * Save our processor parameters | |
291 | */ | |
292 | smp_store_cpu_info(cpuid); | |
293 | ||
294 | /* | |
295 | * Allow the master to continue. | |
296 | */ | |
297 | cpu_set(cpuid, cpu_callin_map); | |
298 | } | |
299 | ||
bbc2ff6a GOC |
300 | /* |
301 | * Activate a secondary processor. | |
302 | */ | |
dbe55f47 | 303 | static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
304 | { |
305 | /* | |
306 | * Don't put *anything* before cpu_init(), SMP booting is too | |
307 | * fragile that we want to limit the things done here to the | |
308 | * most necessary things. | |
309 | */ | |
310 | #ifdef CONFIG_VMI | |
311 | vmi_bringup(); | |
312 | #endif | |
313 | cpu_init(); | |
314 | preempt_disable(); | |
315 | smp_callin(); | |
316 | ||
317 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
318 | barrier(); | |
319 | /* | |
320 | * Check TSC synchronization with the BP: | |
321 | */ | |
322 | check_tsc_sync_target(); | |
323 | ||
324 | if (nmi_watchdog == NMI_IO_APIC) { | |
325 | disable_8259A_irq(0); | |
326 | enable_NMI_through_LVT0(); | |
327 | enable_8259A_irq(0); | |
328 | } | |
329 | ||
61165d7a HD |
330 | #ifdef CONFIG_X86_32 |
331 | while (low_mappings) | |
332 | cpu_relax(); | |
333 | __flush_tlb_all(); | |
334 | #endif | |
335 | ||
bbc2ff6a GOC |
336 | /* This must be done before setting cpu_online_map */ |
337 | set_cpu_sibling_map(raw_smp_processor_id()); | |
338 | wmb(); | |
339 | ||
340 | /* | |
341 | * We need to hold call_lock, so there is no inconsistency | |
342 | * between the time smp_call_function() determines number of | |
343 | * IPI recipients, and the time when the determination is made | |
344 | * for which cpus receive the IPI. Holding this | |
345 | * lock helps us to not include this cpu in a currently in progress | |
346 | * smp_call_function(). | |
347 | */ | |
348 | lock_ipi_call_lock(); | |
349 | #ifdef CONFIG_X86_64 | |
350 | spin_lock(&vector_lock); | |
351 | ||
352 | /* Setup the per cpu irq handling data structures */ | |
353 | __setup_vector_irq(smp_processor_id()); | |
354 | /* | |
355 | * Allow the master to continue. | |
356 | */ | |
357 | spin_unlock(&vector_lock); | |
358 | #endif | |
359 | cpu_set(smp_processor_id(), cpu_online_map); | |
360 | unlock_ipi_call_lock(); | |
361 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; | |
362 | ||
363 | setup_secondary_clock(); | |
364 | ||
365 | wmb(); | |
366 | cpu_idle(); | |
367 | } | |
368 | ||
369 | #ifdef CONFIG_X86_32 | |
370 | /* | |
371 | * Everything has been set up for the secondary | |
372 | * CPUs - they just need to reload everything | |
373 | * from the task structure | |
374 | * This function must not return. | |
375 | */ | |
376 | void __devinit initialize_secondary(void) | |
377 | { | |
378 | /* | |
379 | * We don't actually need to load the full TSS, | |
380 | * basically just the stack pointer and the ip. | |
381 | */ | |
382 | ||
383 | asm volatile( | |
384 | "movl %0,%%esp\n\t" | |
385 | "jmp *%1" | |
386 | : | |
387 | :"m" (current->thread.sp), "m" (current->thread.ip)); | |
388 | } | |
389 | #endif | |
cb3c8b90 | 390 | |
1d89a7f0 GOC |
391 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
392 | { | |
393 | #ifdef CONFIG_X86_32 | |
394 | /* | |
395 | * Mask B, Pentium, but not Pentium MMX | |
396 | */ | |
397 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
398 | c->x86 == 5 && | |
399 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
400 | c->x86_model <= 3) | |
401 | /* | |
402 | * Remember we have B step Pentia with bugs | |
403 | */ | |
404 | smp_b_stepping = 1; | |
405 | ||
406 | /* | |
407 | * Certain Athlons might work (for various values of 'work') in SMP | |
408 | * but they are not certified as MP capable. | |
409 | */ | |
410 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
411 | ||
412 | if (num_possible_cpus() == 1) | |
413 | goto valid_k7; | |
414 | ||
415 | /* Athlon 660/661 is valid. */ | |
416 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
417 | (c->x86_mask == 1))) | |
418 | goto valid_k7; | |
419 | ||
420 | /* Duron 670 is valid */ | |
421 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
422 | goto valid_k7; | |
423 | ||
424 | /* | |
425 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
426 | * bit. It's worth noting that the A5 stepping (662) of some | |
427 | * Athlon XP's have the MP bit set. | |
428 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
429 | * more. | |
430 | */ | |
431 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
432 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
433 | (c->x86_model > 7)) | |
434 | if (cpu_has_mp) | |
435 | goto valid_k7; | |
436 | ||
437 | /* If we get here, not a certified SMP capable AMD system. */ | |
438 | add_taint(TAINT_UNSAFE_SMP); | |
439 | } | |
440 | ||
441 | valid_k7: | |
442 | ; | |
443 | #endif | |
444 | } | |
445 | ||
a4928cff | 446 | static void __cpuinit smp_checks(void) |
693d4b8a GOC |
447 | { |
448 | if (smp_b_stepping) | |
449 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
450 | "with B stepping processors.\n"); | |
451 | ||
452 | /* | |
453 | * Don't taint if we are running SMP kernel on a single non-MP | |
454 | * approved Athlon | |
455 | */ | |
456 | if (tainted & TAINT_UNSAFE_SMP) { | |
f68e00a3 | 457 | if (num_online_cpus()) |
693d4b8a GOC |
458 | printk(KERN_INFO "WARNING: This combination of AMD" |
459 | "processors is not suitable for SMP.\n"); | |
460 | else | |
461 | tainted &= ~TAINT_UNSAFE_SMP; | |
462 | } | |
463 | } | |
464 | ||
1d89a7f0 GOC |
465 | /* |
466 | * The bootstrap kernel entry code has set these up. Save them for | |
467 | * a given CPU | |
468 | */ | |
469 | ||
470 | void __cpuinit smp_store_cpu_info(int id) | |
471 | { | |
472 | struct cpuinfo_x86 *c = &cpu_data(id); | |
473 | ||
474 | *c = boot_cpu_data; | |
475 | c->cpu_index = id; | |
476 | if (id != 0) | |
477 | identify_secondary_cpu(c); | |
478 | smp_apply_quirks(c); | |
479 | } | |
480 | ||
481 | ||
768d9505 GC |
482 | void __cpuinit set_cpu_sibling_map(int cpu) |
483 | { | |
484 | int i; | |
485 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
486 | ||
487 | cpu_set(cpu, cpu_sibling_setup_map); | |
488 | ||
489 | if (smp_num_siblings > 1) { | |
490 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
491 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && | |
492 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
493 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); | |
494 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
495 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
496 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
497 | cpu_set(i, c->llc_shared_map); | |
498 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
499 | } | |
500 | } | |
501 | } else { | |
502 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); | |
503 | } | |
504 | ||
505 | cpu_set(cpu, c->llc_shared_map); | |
506 | ||
507 | if (current_cpu_data.x86_max_cores == 1) { | |
508 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); | |
509 | c->booted_cores = 1; | |
510 | return; | |
511 | } | |
512 | ||
513 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
514 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && | |
515 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
516 | cpu_set(i, c->llc_shared_map); | |
517 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
518 | } | |
519 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
520 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
521 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
522 | /* | |
523 | * Does this new cpu bringup a new core? | |
524 | */ | |
525 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { | |
526 | /* | |
527 | * for each core in package, increment | |
528 | * the booted_cores for this new cpu | |
529 | */ | |
530 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) | |
531 | c->booted_cores++; | |
532 | /* | |
533 | * increment the core count for all | |
534 | * the other cpus in this package | |
535 | */ | |
536 | if (i != cpu) | |
537 | cpu_data(i).booted_cores++; | |
538 | } else if (i != cpu && !c->booted_cores) | |
539 | c->booted_cores = cpu_data(i).booted_cores; | |
540 | } | |
541 | } | |
542 | } | |
543 | ||
70708a18 GC |
544 | /* maps the cpu to the sched domain representing multi-core */ |
545 | cpumask_t cpu_coregroup_map(int cpu) | |
546 | { | |
547 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
548 | /* | |
549 | * For perf, we return last level cache shared map. | |
550 | * And for power savings, we return cpu_core_map | |
551 | */ | |
552 | if (sched_mc_power_savings || sched_smt_power_savings) | |
553 | return per_cpu(cpu_core_map, cpu); | |
554 | else | |
555 | return c->llc_shared_map; | |
556 | } | |
557 | ||
91718e8d GC |
558 | #ifdef CONFIG_X86_32 |
559 | /* | |
560 | * We are called very early to get the low memory for the | |
561 | * SMP bootup trampoline page. | |
562 | */ | |
563 | void __init smp_alloc_memory(void) | |
564 | { | |
565 | trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE); | |
566 | /* | |
567 | * Has to be in very low memory so we can execute | |
568 | * real-mode AP code. | |
569 | */ | |
570 | if (__pa(trampoline_base) >= 0x9F000) | |
571 | BUG(); | |
572 | } | |
573 | #endif | |
70708a18 | 574 | |
a4928cff | 575 | static void impress_friends(void) |
904541e2 GOC |
576 | { |
577 | int cpu; | |
578 | unsigned long bogosum = 0; | |
579 | /* | |
580 | * Allow the user to impress friends. | |
581 | */ | |
582 | Dprintk("Before bogomips.\n"); | |
583 | for_each_possible_cpu(cpu) | |
584 | if (cpu_isset(cpu, cpu_callout_map)) | |
585 | bogosum += cpu_data(cpu).loops_per_jiffy; | |
586 | printk(KERN_INFO | |
587 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 588 | num_online_cpus(), |
904541e2 GOC |
589 | bogosum/(500000/HZ), |
590 | (bogosum/(5000/HZ))%100); | |
591 | ||
592 | Dprintk("Before bogocount - setting activated=1.\n"); | |
593 | } | |
594 | ||
cb3c8b90 GOC |
595 | static inline void __inquire_remote_apic(int apicid) |
596 | { | |
597 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
598 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
599 | int timeout; | |
600 | u32 status; | |
601 | ||
602 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
603 | ||
604 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
605 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); | |
606 | ||
607 | /* | |
608 | * Wait for idle. | |
609 | */ | |
610 | status = safe_apic_wait_icr_idle(); | |
611 | if (status) | |
612 | printk(KERN_CONT | |
613 | "a previous APIC delivery may have failed\n"); | |
614 | ||
615 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
616 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
617 | ||
618 | timeout = 0; | |
619 | do { | |
620 | udelay(100); | |
621 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
622 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
623 | ||
624 | switch (status) { | |
625 | case APIC_ICR_RR_VALID: | |
626 | status = apic_read(APIC_RRR); | |
627 | printk(KERN_CONT "%08x\n", status); | |
628 | break; | |
629 | default: | |
630 | printk(KERN_CONT "failed\n"); | |
631 | } | |
632 | } | |
633 | } | |
634 | ||
635 | #ifdef WAKE_SECONDARY_VIA_NMI | |
636 | /* | |
637 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
638 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
639 | * won't ... remember to clear down the APIC, etc later. | |
640 | */ | |
641 | static int __devinit | |
642 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) | |
643 | { | |
644 | unsigned long send_status, accept_status = 0; | |
645 | int maxlvt; | |
646 | ||
647 | /* Target chip */ | |
648 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
649 | ||
650 | /* Boot on the stack */ | |
651 | /* Kick the second */ | |
652 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
653 | ||
654 | Dprintk("Waiting for send to finish...\n"); | |
655 | send_status = safe_apic_wait_icr_idle(); | |
656 | ||
657 | /* | |
658 | * Give the other CPU some time to accept the IPI. | |
659 | */ | |
660 | udelay(200); | |
661 | /* | |
662 | * Due to the Pentium erratum 3AP. | |
663 | */ | |
664 | maxlvt = lapic_get_maxlvt(); | |
665 | if (maxlvt > 3) { | |
666 | apic_read_around(APIC_SPIV); | |
667 | apic_write(APIC_ESR, 0); | |
668 | } | |
669 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
670 | Dprintk("NMI sent.\n"); | |
671 | ||
672 | if (send_status) | |
673 | printk(KERN_ERR "APIC never delivered???\n"); | |
674 | if (accept_status) | |
675 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
676 | ||
677 | return (send_status | accept_status); | |
678 | } | |
679 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
680 | ||
cb3c8b90 GOC |
681 | #ifdef WAKE_SECONDARY_VIA_INIT |
682 | static int __devinit | |
683 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) | |
684 | { | |
685 | unsigned long send_status, accept_status = 0; | |
686 | int maxlvt, num_starts, j; | |
687 | ||
34d05591 JS |
688 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { |
689 | send_status = uv_wakeup_secondary(phys_apicid, start_eip); | |
690 | atomic_set(&init_deasserted, 1); | |
691 | return send_status; | |
692 | } | |
693 | ||
cb3c8b90 GOC |
694 | /* |
695 | * Be paranoid about clearing APIC errors. | |
696 | */ | |
697 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
698 | apic_read_around(APIC_SPIV); | |
699 | apic_write(APIC_ESR, 0); | |
700 | apic_read(APIC_ESR); | |
701 | } | |
702 | ||
703 | Dprintk("Asserting INIT.\n"); | |
704 | ||
705 | /* | |
706 | * Turn INIT on target chip | |
707 | */ | |
708 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
709 | ||
710 | /* | |
711 | * Send IPI | |
712 | */ | |
713 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
714 | | APIC_DM_INIT); | |
715 | ||
716 | Dprintk("Waiting for send to finish...\n"); | |
717 | send_status = safe_apic_wait_icr_idle(); | |
718 | ||
719 | mdelay(10); | |
720 | ||
721 | Dprintk("Deasserting INIT.\n"); | |
722 | ||
723 | /* Target chip */ | |
724 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
725 | ||
726 | /* Send IPI */ | |
727 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
728 | ||
729 | Dprintk("Waiting for send to finish...\n"); | |
730 | send_status = safe_apic_wait_icr_idle(); | |
731 | ||
732 | mb(); | |
733 | atomic_set(&init_deasserted, 1); | |
734 | ||
735 | /* | |
736 | * Should we send STARTUP IPIs ? | |
737 | * | |
738 | * Determine this based on the APIC version. | |
739 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
740 | */ | |
741 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
742 | num_starts = 2; | |
743 | else | |
744 | num_starts = 0; | |
745 | ||
746 | /* | |
747 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
748 | * target processor state. | |
749 | */ | |
750 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
751 | #ifdef CONFIG_X86_64 | |
752 | (unsigned long)init_rsp); | |
753 | #else | |
754 | (unsigned long)stack_start.sp); | |
755 | #endif | |
756 | ||
757 | /* | |
758 | * Run STARTUP IPI loop. | |
759 | */ | |
760 | Dprintk("#startup loops: %d.\n", num_starts); | |
761 | ||
762 | maxlvt = lapic_get_maxlvt(); | |
763 | ||
764 | for (j = 1; j <= num_starts; j++) { | |
765 | Dprintk("Sending STARTUP #%d.\n", j); | |
766 | apic_read_around(APIC_SPIV); | |
767 | apic_write(APIC_ESR, 0); | |
768 | apic_read(APIC_ESR); | |
769 | Dprintk("After apic_write.\n"); | |
770 | ||
771 | /* | |
772 | * STARTUP IPI | |
773 | */ | |
774 | ||
775 | /* Target chip */ | |
776 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
777 | ||
778 | /* Boot on the stack */ | |
779 | /* Kick the second */ | |
780 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
781 | | (start_eip >> 12)); | |
782 | ||
783 | /* | |
784 | * Give the other CPU some time to accept the IPI. | |
785 | */ | |
786 | udelay(300); | |
787 | ||
788 | Dprintk("Startup point 1.\n"); | |
789 | ||
790 | Dprintk("Waiting for send to finish...\n"); | |
791 | send_status = safe_apic_wait_icr_idle(); | |
792 | ||
793 | /* | |
794 | * Give the other CPU some time to accept the IPI. | |
795 | */ | |
796 | udelay(200); | |
797 | /* | |
798 | * Due to the Pentium erratum 3AP. | |
799 | */ | |
800 | if (maxlvt > 3) { | |
801 | apic_read_around(APIC_SPIV); | |
802 | apic_write(APIC_ESR, 0); | |
803 | } | |
804 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
805 | if (send_status || accept_status) | |
806 | break; | |
807 | } | |
808 | Dprintk("After Startup.\n"); | |
809 | ||
810 | if (send_status) | |
811 | printk(KERN_ERR "APIC never delivered???\n"); | |
812 | if (accept_status) | |
813 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
814 | ||
815 | return (send_status | accept_status); | |
816 | } | |
817 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
818 | ||
819 | struct create_idle { | |
820 | struct work_struct work; | |
821 | struct task_struct *idle; | |
822 | struct completion done; | |
823 | int cpu; | |
824 | }; | |
825 | ||
826 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
827 | { | |
828 | struct create_idle *c_idle = | |
829 | container_of(work, struct create_idle, work); | |
830 | ||
831 | c_idle->idle = fork_idle(c_idle->cpu); | |
832 | complete(&c_idle->done); | |
833 | } | |
834 | ||
835 | static int __cpuinit do_boot_cpu(int apicid, int cpu) | |
836 | /* | |
837 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
838 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
839 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
840 | */ | |
841 | { | |
842 | unsigned long boot_error = 0; | |
843 | int timeout; | |
844 | unsigned long start_ip; | |
845 | unsigned short nmi_high = 0, nmi_low = 0; | |
846 | struct create_idle c_idle = { | |
847 | .cpu = cpu, | |
848 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
849 | }; | |
850 | INIT_WORK(&c_idle.work, do_fork_idle); | |
851 | #ifdef CONFIG_X86_64 | |
852 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ | |
853 | if (!cpu_gdt_descr[cpu].address && | |
854 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
855 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
856 | return -1; | |
857 | } | |
858 | ||
859 | /* Allocate node local memory for AP pdas */ | |
860 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
861 | struct x8664_pda *newpda, *pda; | |
862 | int node = cpu_to_node(cpu); | |
863 | pda = cpu_pda(cpu); | |
864 | newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC, | |
865 | node); | |
866 | if (newpda) { | |
867 | memcpy(newpda, pda, sizeof(struct x8664_pda)); | |
868 | cpu_pda(cpu) = newpda; | |
869 | } else | |
870 | printk(KERN_ERR | |
871 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
872 | cpu, node); | |
873 | } | |
874 | #endif | |
875 | ||
876 | alternatives_smp_switch(1); | |
877 | ||
878 | c_idle.idle = get_idle_for_cpu(cpu); | |
879 | ||
880 | /* | |
881 | * We can't use kernel_thread since we must avoid to | |
882 | * reschedule the child. | |
883 | */ | |
884 | if (c_idle.idle) { | |
885 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
886 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
887 | init_idle(c_idle.idle, cpu); | |
888 | goto do_rest; | |
889 | } | |
890 | ||
891 | if (!keventd_up() || current_is_keventd()) | |
892 | c_idle.work.func(&c_idle.work); | |
893 | else { | |
894 | schedule_work(&c_idle.work); | |
895 | wait_for_completion(&c_idle.done); | |
896 | } | |
897 | ||
898 | if (IS_ERR(c_idle.idle)) { | |
899 | printk("failed fork for CPU %d\n", cpu); | |
900 | return PTR_ERR(c_idle.idle); | |
901 | } | |
902 | ||
903 | set_idle_for_cpu(cpu, c_idle.idle); | |
904 | do_rest: | |
905 | #ifdef CONFIG_X86_32 | |
906 | per_cpu(current_task, cpu) = c_idle.idle; | |
907 | init_gdt(cpu); | |
908 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); | |
909 | c_idle.idle->thread.ip = (unsigned long) start_secondary; | |
910 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
911 | stack_start.sp = (void *) c_idle.idle->thread.sp; | |
912 | irq_ctx_init(cpu); | |
913 | #else | |
914 | cpu_pda(cpu)->pcurrent = c_idle.idle; | |
915 | init_rsp = c_idle.idle->thread.sp; | |
916 | load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread); | |
917 | initial_code = (unsigned long)start_secondary; | |
918 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); | |
919 | #endif | |
920 | ||
921 | /* start_ip had better be page-aligned! */ | |
922 | start_ip = setup_trampoline(); | |
923 | ||
924 | /* So we see what's up */ | |
925 | printk(KERN_INFO "Booting processor %d/%d ip %lx\n", | |
926 | cpu, apicid, start_ip); | |
927 | ||
928 | /* | |
929 | * This grunge runs the startup process for | |
930 | * the targeted processor. | |
931 | */ | |
932 | ||
933 | atomic_set(&init_deasserted, 0); | |
934 | ||
34d05591 | 935 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 936 | |
34d05591 | 937 | Dprintk("Setting warm reset code and vector.\n"); |
cb3c8b90 | 938 | |
34d05591 JS |
939 | store_NMI_vector(&nmi_high, &nmi_low); |
940 | ||
941 | smpboot_setup_warm_reset_vector(start_ip); | |
942 | /* | |
943 | * Be paranoid about clearing APIC errors. | |
944 | */ | |
945 | apic_write(APIC_ESR, 0); | |
946 | apic_read(APIC_ESR); | |
947 | } | |
cb3c8b90 | 948 | |
cb3c8b90 GOC |
949 | /* |
950 | * Starting actual IPI sequence... | |
951 | */ | |
952 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
953 | ||
954 | if (!boot_error) { | |
955 | /* | |
956 | * allow APs to start initializing. | |
957 | */ | |
958 | Dprintk("Before Callout %d.\n", cpu); | |
959 | cpu_set(cpu, cpu_callout_map); | |
960 | Dprintk("After Callout %d.\n", cpu); | |
961 | ||
962 | /* | |
963 | * Wait 5s total for a response | |
964 | */ | |
965 | for (timeout = 0; timeout < 50000; timeout++) { | |
966 | if (cpu_isset(cpu, cpu_callin_map)) | |
967 | break; /* It has booted */ | |
968 | udelay(100); | |
969 | } | |
970 | ||
971 | if (cpu_isset(cpu, cpu_callin_map)) { | |
972 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
973 | Dprintk("OK.\n"); | |
974 | printk(KERN_INFO "CPU%d: ", cpu); | |
975 | print_cpu_info(&cpu_data(cpu)); | |
976 | Dprintk("CPU has booted.\n"); | |
977 | } else { | |
978 | boot_error = 1; | |
979 | if (*((volatile unsigned char *)trampoline_base) | |
980 | == 0xA5) | |
981 | /* trampoline started but...? */ | |
982 | printk(KERN_ERR "Stuck ??\n"); | |
983 | else | |
984 | /* trampoline code not run */ | |
985 | printk(KERN_ERR "Not responding.\n"); | |
34d05591 JS |
986 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) |
987 | inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
988 | } |
989 | } | |
990 | ||
991 | if (boot_error) { | |
992 | /* Try to put things back the way they were before ... */ | |
993 | unmap_cpu_to_logical_apicid(cpu); | |
994 | #ifdef CONFIG_X86_64 | |
995 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ | |
996 | #endif | |
997 | cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ | |
998 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
cb3c8b90 GOC |
999 | cpu_clear(cpu, cpu_present_map); |
1000 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; | |
1001 | } | |
1002 | ||
1003 | /* mark "stuck" area as not stuck */ | |
1004 | *((volatile unsigned long *)trampoline_base) = 0; | |
1005 | ||
63d38198 AK |
1006 | /* |
1007 | * Cleanup possible dangling ends... | |
1008 | */ | |
1009 | smpboot_restore_warm_reset_vector(); | |
1010 | ||
cb3c8b90 GOC |
1011 | return boot_error; |
1012 | } | |
1013 | ||
1014 | int __cpuinit native_cpu_up(unsigned int cpu) | |
1015 | { | |
1016 | int apicid = cpu_present_to_apicid(cpu); | |
1017 | unsigned long flags; | |
1018 | int err; | |
1019 | ||
1020 | WARN_ON(irqs_disabled()); | |
1021 | ||
1022 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); | |
1023 | ||
1024 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
1025 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1026 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
1027 | return -EINVAL; | |
1028 | } | |
1029 | ||
1030 | /* | |
1031 | * Already booted CPU? | |
1032 | */ | |
1033 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1034 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1035 | return -ENOSYS; | |
1036 | } | |
1037 | ||
1038 | /* | |
1039 | * Save current MTRR state in case it was changed since early boot | |
1040 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1041 | */ | |
1042 | mtrr_save_state(); | |
1043 | ||
1044 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
1045 | ||
1046 | #ifdef CONFIG_X86_32 | |
1047 | /* init low mem mapping */ | |
68db065c | 1048 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 1049 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 1050 | flush_tlb_all(); |
61165d7a | 1051 | low_mappings = 1; |
cb3c8b90 GOC |
1052 | |
1053 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
1054 | |
1055 | zap_low_mappings(); | |
1056 | low_mappings = 0; | |
1057 | #else | |
1058 | err = do_boot_cpu(apicid, cpu); | |
1059 | #endif | |
1060 | if (err) { | |
cb3c8b90 | 1061 | Dprintk("do_boot_cpu failed %d\n", err); |
61165d7a | 1062 | return -EIO; |
cb3c8b90 GOC |
1063 | } |
1064 | ||
1065 | /* | |
1066 | * Check TSC synchronization with the AP (keep irqs disabled | |
1067 | * while doing so): | |
1068 | */ | |
1069 | local_irq_save(flags); | |
1070 | check_tsc_sync_source(cpu); | |
1071 | local_irq_restore(flags); | |
1072 | ||
7c04e64a | 1073 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1074 | cpu_relax(); |
1075 | touch_nmi_watchdog(); | |
1076 | } | |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
8aef135c GOC |
1081 | /* |
1082 | * Fall back to non SMP mode after errors. | |
1083 | * | |
1084 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1085 | */ | |
1086 | static __init void disable_smp(void) | |
1087 | { | |
1088 | cpu_present_map = cpumask_of_cpu(0); | |
1089 | cpu_possible_map = cpumask_of_cpu(0); | |
1090 | #ifdef CONFIG_X86_32 | |
1091 | smpboot_clear_io_apic_irqs(); | |
1092 | #endif | |
1093 | if (smp_found_config) | |
b6df1b8b | 1094 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1095 | else |
b6df1b8b | 1096 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c GOC |
1097 | map_cpu_to_logical_apicid(); |
1098 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
1099 | cpu_set(0, per_cpu(cpu_core_map, 0)); | |
1100 | } | |
1101 | ||
1102 | /* | |
1103 | * Various sanity checks. | |
1104 | */ | |
1105 | static int __init smp_sanity_check(unsigned max_cpus) | |
1106 | { | |
ac23d4ee | 1107 | preempt_disable(); |
8aef135c GOC |
1108 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1109 | printk(KERN_WARNING "weird, boot CPU (#%d) not listed" | |
1110 | "by the BIOS.\n", hard_smp_processor_id()); | |
1111 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * If we couldn't find an SMP configuration at boot time, | |
1116 | * get out of here now! | |
1117 | */ | |
1118 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1119 | preempt_enable(); |
8aef135c GOC |
1120 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1121 | disable_smp(); | |
1122 | if (APIC_init_uniprocessor()) | |
1123 | printk(KERN_NOTICE "Local APIC not detected." | |
1124 | " Using dummy APIC emulation.\n"); | |
1125 | return -1; | |
1126 | } | |
1127 | ||
1128 | /* | |
1129 | * Should not be necessary because the MP table should list the boot | |
1130 | * CPU too, but we do it for the sake of robustness anyway. | |
1131 | */ | |
1132 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1133 | printk(KERN_NOTICE | |
1134 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1135 | boot_cpu_physical_apicid); | |
1136 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1137 | } | |
ac23d4ee | 1138 | preempt_enable(); |
8aef135c GOC |
1139 | |
1140 | /* | |
1141 | * If we couldn't find a local APIC, then get out of here now! | |
1142 | */ | |
1143 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1144 | !cpu_has_apic) { | |
1145 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1146 | boot_cpu_physical_apicid); | |
1147 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1148 | "(tell your hw vendor)\n"); | |
1149 | smpboot_clear_io_apic(); | |
1150 | return -1; | |
1151 | } | |
1152 | ||
1153 | verify_local_APIC(); | |
1154 | ||
1155 | /* | |
1156 | * If SMP should be disabled, then really disable it! | |
1157 | */ | |
1158 | if (!max_cpus) { | |
1159 | printk(KERN_INFO "SMP mode deactivated," | |
1160 | "forcing use of dummy APIC emulation.\n"); | |
1161 | smpboot_clear_io_apic(); | |
1162 | #ifdef CONFIG_X86_32 | |
e90955c2 | 1163 | connect_bsp_APIC(); |
8aef135c | 1164 | #endif |
e90955c2 JB |
1165 | setup_local_APIC(); |
1166 | end_local_APIC_setup(); | |
8aef135c GOC |
1167 | return -1; |
1168 | } | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | static void __init smp_cpu_index_default(void) | |
1174 | { | |
1175 | int i; | |
1176 | struct cpuinfo_x86 *c; | |
1177 | ||
7c04e64a | 1178 | for_each_possible_cpu(i) { |
8aef135c GOC |
1179 | c = &cpu_data(i); |
1180 | /* mark all to hotplug */ | |
1181 | c->cpu_index = NR_CPUS; | |
1182 | } | |
1183 | } | |
1184 | ||
1185 | /* | |
1186 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1187 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1188 | */ | |
1189 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1190 | { | |
deef3250 | 1191 | preempt_disable(); |
8aef135c GOC |
1192 | nmi_watchdog_default(); |
1193 | smp_cpu_index_default(); | |
1194 | current_cpu_data = boot_cpu_data; | |
1195 | cpu_callin_map = cpumask_of_cpu(0); | |
1196 | mb(); | |
1197 | /* | |
1198 | * Setup boot CPU information | |
1199 | */ | |
1200 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1201 | boot_cpu_logical_apicid = logical_smp_processor_id(); | |
1202 | current_thread_info()->cpu = 0; /* needed? */ | |
1203 | set_cpu_sibling_map(0); | |
1204 | ||
1205 | if (smp_sanity_check(max_cpus) < 0) { | |
1206 | printk(KERN_INFO "SMP disabled\n"); | |
1207 | disable_smp(); | |
deef3250 | 1208 | goto out; |
8aef135c GOC |
1209 | } |
1210 | ||
ac23d4ee | 1211 | preempt_disable(); |
05f2d12c | 1212 | if (GET_APIC_ID(read_apic_id()) != boot_cpu_physical_apicid) { |
8aef135c | 1213 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
05f2d12c | 1214 | GET_APIC_ID(read_apic_id()), boot_cpu_physical_apicid); |
8aef135c GOC |
1215 | /* Or can we switch back to PIC here? */ |
1216 | } | |
ac23d4ee | 1217 | preempt_enable(); |
8aef135c GOC |
1218 | |
1219 | #ifdef CONFIG_X86_32 | |
1220 | connect_bsp_APIC(); | |
1221 | #endif | |
1222 | /* | |
1223 | * Switch from PIC to APIC mode. | |
1224 | */ | |
1225 | setup_local_APIC(); | |
1226 | ||
1227 | #ifdef CONFIG_X86_64 | |
1228 | /* | |
1229 | * Enable IO APIC before setting up error vector | |
1230 | */ | |
1231 | if (!skip_ioapic_setup && nr_ioapics) | |
1232 | enable_IO_APIC(); | |
1233 | #endif | |
1234 | end_local_APIC_setup(); | |
1235 | ||
1236 | map_cpu_to_logical_apicid(); | |
1237 | ||
1238 | setup_portio_remap(); | |
1239 | ||
1240 | smpboot_setup_io_apic(); | |
1241 | /* | |
1242 | * Set up local APIC timer on boot CPU. | |
1243 | */ | |
1244 | ||
1245 | printk(KERN_INFO "CPU%d: ", 0); | |
1246 | print_cpu_info(&cpu_data(0)); | |
1247 | setup_boot_clock(); | |
deef3250 IM |
1248 | out: |
1249 | preempt_enable(); | |
8aef135c | 1250 | } |
a8db8453 GOC |
1251 | /* |
1252 | * Early setup to make printk work. | |
1253 | */ | |
1254 | void __init native_smp_prepare_boot_cpu(void) | |
1255 | { | |
1256 | int me = smp_processor_id(); | |
1257 | #ifdef CONFIG_X86_32 | |
1258 | init_gdt(me); | |
1259 | switch_to_new_gdt(); | |
1260 | #endif | |
1261 | /* already set me in cpu_online_map in boot_cpu_init() */ | |
1262 | cpu_set(me, cpu_callout_map); | |
1263 | per_cpu(cpu_state, me) = CPU_ONLINE; | |
1264 | } | |
1265 | ||
83f7eb9c GOC |
1266 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1267 | { | |
83f7eb9c GOC |
1268 | Dprintk("Boot done.\n"); |
1269 | ||
1270 | impress_friends(); | |
1271 | smp_checks(); | |
1272 | #ifdef CONFIG_X86_IO_APIC | |
1273 | setup_ioapic_dest(); | |
1274 | #endif | |
1275 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1276 | } |
1277 | ||
68a1c3f8 | 1278 | #ifdef CONFIG_HOTPLUG_CPU |
2cd9fb71 GOC |
1279 | |
1280 | # ifdef CONFIG_X86_32 | |
1281 | void cpu_exit_clear(void) | |
1282 | { | |
1283 | int cpu = raw_smp_processor_id(); | |
1284 | ||
1285 | idle_task_exit(); | |
1286 | ||
1287 | cpu_uninit(); | |
1288 | irq_ctx_exit(cpu); | |
1289 | ||
1290 | cpu_clear(cpu, cpu_callout_map); | |
1291 | cpu_clear(cpu, cpu_callin_map); | |
1292 | ||
1293 | unmap_cpu_to_logical_apicid(cpu); | |
1294 | } | |
1295 | # endif /* CONFIG_X86_32 */ | |
1296 | ||
a4928cff | 1297 | static void remove_siblinginfo(int cpu) |
768d9505 GC |
1298 | { |
1299 | int sibling; | |
1300 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1301 | ||
1302 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { | |
1303 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
1304 | /*/ | |
1305 | * last thread sibling in this cpu core going down | |
1306 | */ | |
1307 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) | |
1308 | cpu_data(sibling).booted_cores--; | |
1309 | } | |
1310 | ||
1311 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) | |
1312 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1313 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
1314 | cpus_clear(per_cpu(cpu_core_map, cpu)); | |
1315 | c->phys_proc_id = 0; | |
1316 | c->cpu_core_id = 0; | |
1317 | cpu_clear(cpu, cpu_sibling_setup_map); | |
1318 | } | |
68a1c3f8 | 1319 | |
c5562fae | 1320 | static int additional_cpus __initdata = -1; |
68a1c3f8 GC |
1321 | |
1322 | static __init int setup_additional_cpus(char *s) | |
1323 | { | |
1324 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; | |
1325 | } | |
1326 | early_param("additional_cpus", setup_additional_cpus); | |
1327 | ||
1328 | /* | |
1329 | * cpu_possible_map should be static, it cannot change as cpu's | |
1330 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1331 | * are allocated by some modules at init time, and dont expect to | |
1332 | * do this dynamically on cpu arrival/departure. | |
1333 | * cpu_present_map on the other hand can change dynamically. | |
1334 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1335 | * behaviour, which is cpu_possible == cpu_present. | |
1336 | * - Ashok Raj | |
1337 | * | |
1338 | * Three ways to find out the number of additional hotplug CPUs: | |
1339 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
1340 | * - The user can overwrite it with additional_cpus=NUM | |
1341 | * - Otherwise don't reserve additional CPUs. | |
1342 | * We do this because additional CPUs waste a lot of memory. | |
1343 | * -AK | |
1344 | */ | |
1345 | __init void prefill_possible_map(void) | |
1346 | { | |
1347 | int i; | |
1348 | int possible; | |
1349 | ||
1350 | if (additional_cpus == -1) { | |
1351 | if (disabled_cpus > 0) | |
1352 | additional_cpus = disabled_cpus; | |
1353 | else | |
1354 | additional_cpus = 0; | |
1355 | } | |
1356 | possible = num_processors + additional_cpus; | |
1357 | if (possible > NR_CPUS) | |
1358 | possible = NR_CPUS; | |
1359 | ||
1360 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1361 | possible, max_t(int, possible - num_processors, 0)); | |
1362 | ||
1363 | for (i = 0; i < possible; i++) | |
1364 | cpu_set(i, cpu_possible_map); | |
1365 | } | |
69c18c15 GC |
1366 | |
1367 | static void __ref remove_cpu_from_maps(int cpu) | |
1368 | { | |
1369 | cpu_clear(cpu, cpu_online_map); | |
1370 | #ifdef CONFIG_X86_64 | |
1371 | cpu_clear(cpu, cpu_callout_map); | |
1372 | cpu_clear(cpu, cpu_callin_map); | |
1373 | /* was set by cpu_init() */ | |
1374 | clear_bit(cpu, (unsigned long *)&cpu_initialized); | |
1375 | clear_node_cpumask(cpu); | |
1376 | #endif | |
1377 | } | |
1378 | ||
1379 | int __cpu_disable(void) | |
1380 | { | |
1381 | int cpu = smp_processor_id(); | |
1382 | ||
1383 | /* | |
1384 | * Perhaps use cpufreq to drop frequency, but that could go | |
1385 | * into generic code. | |
1386 | * | |
1387 | * We won't take down the boot processor on i386 due to some | |
1388 | * interrupts only being able to be serviced by the BSP. | |
1389 | * Especially so if we're not using an IOAPIC -zwane | |
1390 | */ | |
1391 | if (cpu == 0) | |
1392 | return -EBUSY; | |
1393 | ||
1394 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1395 | stop_apic_nmi_watchdog(NULL); | |
1396 | clear_local_APIC(); | |
1397 | ||
1398 | /* | |
1399 | * HACK: | |
1400 | * Allow any queued timer interrupts to get serviced | |
1401 | * This is only a temporary solution until we cleanup | |
1402 | * fixup_irqs as we do for IA64. | |
1403 | */ | |
1404 | local_irq_enable(); | |
1405 | mdelay(1); | |
1406 | ||
1407 | local_irq_disable(); | |
1408 | remove_siblinginfo(cpu); | |
1409 | ||
1410 | /* It's now safe to remove this processor from the online map */ | |
1411 | remove_cpu_from_maps(cpu); | |
1412 | fixup_irqs(cpu_online_map); | |
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | void __cpu_die(unsigned int cpu) | |
1417 | { | |
1418 | /* We don't do anything here: idle task is faking death itself. */ | |
1419 | unsigned int i; | |
1420 | ||
1421 | for (i = 0; i < 10; i++) { | |
1422 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1423 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1424 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1425 | if (1 == num_online_cpus()) | |
1426 | alternatives_smp_switch(0); | |
1427 | return; | |
1428 | } | |
1429 | msleep(100); | |
1430 | } | |
1431 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1432 | } | |
1433 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1434 | int __cpu_disable(void) | |
1435 | { | |
1436 | return -ENOSYS; | |
1437 | } | |
1438 | ||
1439 | void __cpu_die(unsigned int cpu) | |
1440 | { | |
1441 | /* We said "no" in __cpu_disable */ | |
1442 | BUG(); | |
1443 | } | |
68a1c3f8 GC |
1444 | #endif |
1445 | ||
89b08200 GC |
1446 | /* |
1447 | * If the BIOS enumerates physical processors before logical, | |
1448 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1449 | */ | |
1450 | static int __init parse_maxcpus(char *arg) | |
1451 | { | |
1452 | extern unsigned int maxcpus; | |
1453 | ||
1454 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1455 | return 0; | |
1456 | } | |
1457 | early_param("maxcpus", parse_maxcpus); |