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c767a54b 1 /*
4cedb334
GOC
2 * x86 SMP booting functions
3 *
87c6fe26 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
8f47e163 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
4cedb334
GOC
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
c767a54b
JP
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
68a1c3f8
GC
44#include <linux/init.h>
45#include <linux/smp.h>
186f4360 46#include <linux/export.h>
70708a18 47#include <linux/sched.h>
69c18c15 48#include <linux/percpu.h>
91718e8d 49#include <linux/bootmem.h>
cb3c8b90
GOC
50#include <linux/err.h>
51#include <linux/nmi.h>
69575d38 52#include <linux/tboot.h>
35f720c5 53#include <linux/stackprotector.h>
5a0e3ad6 54#include <linux/gfp.h>
1a022e3f 55#include <linux/cpuidle.h>
69c18c15 56
8aef135c 57#include <asm/acpi.h>
cb3c8b90 58#include <asm/desc.h>
69c18c15
GC
59#include <asm/nmi.h>
60#include <asm/irq.h>
07bbc16a 61#include <asm/idle.h>
48927bbb 62#include <asm/realmode.h>
69c18c15
GC
63#include <asm/cpu.h>
64#include <asm/numa.h>
cb3c8b90
GOC
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
ea530692 68#include <asm/mwait.h>
7b6aa335 69#include <asm/apic.h>
7167d08e 70#include <asm/io_apic.h>
78f7f1e5 71#include <asm/fpu/internal.h>
569712b2 72#include <asm/setup.h>
bdbcdd48 73#include <asm/uv/uv.h>
cb3c8b90 74#include <linux/mc146818rtc.h>
b81bb373 75#include <asm/i8259.h>
48927bbb 76#include <asm/realmode.h>
646e29a1 77#include <asm/misc.h>
48927bbb 78
a355352b
GC
79/* Number of siblings per CPU package */
80int smp_num_siblings = 1;
81EXPORT_SYMBOL(smp_num_siblings);
82
83/* Last level cache ID of each logical CPU */
0816b0f0 84DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
a355352b 85
a355352b 86/* representing HT siblings of each logical CPU */
0816b0f0 87DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
a355352b
GC
88EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89
90/* representing HT and core siblings of each logical CPU */
0816b0f0 91DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
a355352b
GC
92EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93
0816b0f0 94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
b3d7336d 95
a355352b 96/* Per CPU bogomips and other parameters */
2c773dd3 97DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
a355352b 98EXPORT_PER_CPU_SYMBOL(cpu_info);
768d9505 99
1f12e32f
TG
100/* Logical package management. We might want to allocate that dynamically */
101static int *physical_to_logical_pkg __read_mostly;
102static unsigned long *physical_package_map __read_mostly;;
1f12e32f
TG
103static unsigned int max_physical_pkg_id __read_mostly;
104unsigned int __max_logical_packages __read_mostly;
105EXPORT_SYMBOL(__max_logical_packages);
7b0501b1
JO
106static unsigned int logical_packages __read_mostly;
107static bool logical_packages_frozen __read_mostly;
1f12e32f 108
70b8301f
AK
109/* Maximum number of SMT threads on any online core */
110int __max_smt_threads __read_mostly;
111
f77aa308
TG
112static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
113{
114 unsigned long flags;
115
116 spin_lock_irqsave(&rtc_lock, flags);
117 CMOS_WRITE(0xa, 0xf);
118 spin_unlock_irqrestore(&rtc_lock, flags);
119 local_flush_tlb();
120 pr_debug("1.\n");
121 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
122 start_eip >> 4;
123 pr_debug("2.\n");
124 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
125 start_eip & 0xf;
126 pr_debug("3.\n");
127}
128
129static inline void smpboot_restore_warm_reset_vector(void)
130{
131 unsigned long flags;
132
133 /*
134 * Install writable page 0 entry to set BIOS data area.
135 */
136 local_flush_tlb();
137
138 /*
139 * Paranoid: Set warm reset code and vector here back
140 * to default values.
141 */
142 spin_lock_irqsave(&rtc_lock, flags);
143 CMOS_WRITE(0, 0xf);
144 spin_unlock_irqrestore(&rtc_lock, flags);
145
146 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
147}
148
cb3c8b90 149/*
30106c17
FY
150 * Report back to the Boot Processor during boot time or to the caller processor
151 * during CPU online.
cb3c8b90 152 */
148f9bb8 153static void smp_callin(void)
cb3c8b90
GOC
154{
155 int cpuid, phys_id;
cb3c8b90
GOC
156
157 /*
158 * If waken up by an INIT in an 82489DX configuration
656bba30
LB
159 * cpu_callout_mask guarantees we don't get here before
160 * an INIT_deassert IPI reaches our local APIC, so it is
161 * now safe to touch our local APIC.
cb3c8b90 162 */
e1c467e6 163 cpuid = smp_processor_id();
cb3c8b90
GOC
164
165 /*
166 * (This works even if the APIC is not enabled.)
167 */
4c9961d5 168 phys_id = read_apic_id();
cb3c8b90
GOC
169
170 /*
171 * the boot CPU has finished the init stage and is spinning
172 * on callin_map until we finish. We are free to set up this
173 * CPU, first the APIC. (this is probably redundant on most
174 * boards)
175 */
05f7e46d 176 apic_ap_setup();
cb3c8b90 177
b565201c
JS
178 /*
179 * Save our processor parameters. Note: this information
180 * is needed for clock calibration.
181 */
182 smp_store_cpu_info(cpuid);
183
cb3c8b90
GOC
184 /*
185 * Get our bogomips.
b565201c
JS
186 * Update loops_per_jiffy in cpu_data. Previous call to
187 * smp_store_cpu_info() stored a value that is close but not as
188 * accurate as the value just calculated.
cb3c8b90 189 */
cb3c8b90 190 calibrate_delay();
b565201c 191 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
cfc1b9a6 192 pr_debug("Stack at about %p\n", &cpuid);
cb3c8b90 193
5ef428c4
AK
194 /*
195 * This must be done before setting cpu_online_mask
196 * or calling notify_cpu_starting.
197 */
198 set_cpu_sibling_map(raw_smp_processor_id());
199 wmb();
200
85257024
PZ
201 notify_cpu_starting(cpuid);
202
cb3c8b90
GOC
203 /*
204 * Allow the master to continue.
205 */
c2d1cec1 206 cpumask_set_cpu(cpuid, cpu_callin_mask);
cb3c8b90
GOC
207}
208
e1c467e6
FY
209static int cpu0_logical_apicid;
210static int enable_start_cpu0;
bbc2ff6a
GOC
211/*
212 * Activate a secondary processor.
213 */
148f9bb8 214static void notrace start_secondary(void *unused)
bbc2ff6a
GOC
215{
216 /*
217 * Don't put *anything* before cpu_init(), SMP booting is too
218 * fragile that we want to limit the things done here to the
219 * most necessary things.
220 */
b40827fa 221 cpu_init();
df156f90 222 x86_cpuinit.early_percpu_clock_init();
b40827fa
BP
223 preempt_disable();
224 smp_callin();
fd89a137 225
e1c467e6
FY
226 enable_start_cpu0 = 0;
227
fd89a137 228#ifdef CONFIG_X86_32
b40827fa 229 /* switch away from the initial page table */
fd89a137
JR
230 load_cr3(swapper_pg_dir);
231 __flush_tlb_all();
232#endif
233
bbc2ff6a
GOC
234 /* otherwise gcc will move up smp_processor_id before the cpu_init */
235 barrier();
236 /*
237 * Check TSC synchronization with the BP:
238 */
239 check_tsc_sync_target();
240
bbc2ff6a 241 /*
5a3f75e3
TG
242 * Lock vector_lock and initialize the vectors on this cpu
243 * before setting the cpu online. We must set it online with
244 * vector_lock held to prevent a concurrent setup/teardown
245 * from seeing a half valid vector space.
bbc2ff6a 246 */
d388e5fd 247 lock_vector_lock();
5a3f75e3 248 setup_vector_irq(smp_processor_id());
c2d1cec1 249 set_cpu_online(smp_processor_id(), true);
d388e5fd 250 unlock_vector_lock();
2a442c9c 251 cpu_set_state_online(smp_processor_id());
78c06176 252 x86_platform.nmi_init();
bbc2ff6a 253
0cefa5b9
MS
254 /* enable local interrupts */
255 local_irq_enable();
256
35f720c5
JP
257 /* to prevent fake stack check failure in clock setup */
258 boot_init_stack_canary();
0cefa5b9 259
736decac 260 x86_cpuinit.setup_percpu_clockev();
bbc2ff6a
GOC
261
262 wmb();
fc6d73d6 263 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
bbc2ff6a
GOC
264}
265
1f12e32f
TG
266int topology_update_package_map(unsigned int apicid, unsigned int cpu)
267{
268 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
269
270 /* Called from early boot ? */
271 if (!physical_package_map)
272 return 0;
273
274 if (pkg >= max_physical_pkg_id)
275 return -EINVAL;
276
277 /* Set the logical package id */
278 if (test_and_set_bit(pkg, physical_package_map))
279 goto found;
280
7b0501b1 281 if (logical_packages_frozen) {
1f12e32f 282 physical_to_logical_pkg[pkg] = -1;
7b0501b1 283 pr_warn("APIC(%x) Package %u exceeds logical package max\n",
1f12e32f
TG
284 apicid, pkg);
285 return -ENOSPC;
286 }
7b0501b1
JO
287
288 new = logical_packages++;
1f12e32f
TG
289 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
290 apicid, pkg, new);
291 physical_to_logical_pkg[pkg] = new;
292
293found:
294 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
295 return 0;
296}
297
298/**
299 * topology_phys_to_logical_pkg - Map a physical package id to a logical
300 *
301 * Returns logical package id or -1 if not found
302 */
303int topology_phys_to_logical_pkg(unsigned int phys_pkg)
304{
305 if (phys_pkg >= max_physical_pkg_id)
306 return -1;
307 return physical_to_logical_pkg[phys_pkg];
308}
309EXPORT_SYMBOL(topology_phys_to_logical_pkg);
310
311static void __init smp_init_package_map(void)
312{
313 unsigned int ncpus, cpu;
314 size_t size;
315
316 /*
317 * Today neither Intel nor AMD support heterogenous systems. That
318 * might change in the future....
63d1e995
PZ
319 *
320 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
321 * computation, this won't actually work since some Intel BIOSes
322 * report inconsistent HT data when they disable HT.
323 *
324 * In particular, they reduce the APIC-IDs to only include the cores,
325 * but leave the CPUID topology to say there are (2) siblings.
326 * This means we don't know how many threads there will be until
327 * after the APIC enumeration.
328 *
329 * By not including this we'll sometimes over-estimate the number of
330 * logical packages by the amount of !present siblings, but this is
331 * still better than MAX_LOCAL_APIC.
3e8db224
TG
332 *
333 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
334 * on the command line leading to a similar issue as the HT disable
335 * problem because the hyperthreads are usually enumerated after the
336 * primary cores.
1f12e32f 337 */
63d1e995 338 ncpus = boot_cpu_data.x86_max_cores;
56402d63
TG
339 if (!ncpus) {
340 pr_warn("x86_max_cores == zero !?!?");
341 ncpus = 1;
342 }
343
3e8db224 344 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
7b0501b1 345 logical_packages = 0;
1f12e32f
TG
346
347 /*
348 * Possibly larger than what we need as the number of apic ids per
349 * package can be smaller than the actual used apic ids.
350 */
351 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
352 size = max_physical_pkg_id * sizeof(unsigned int);
353 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
354 memset(physical_to_logical_pkg, 0xff, size);
355 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
356 physical_package_map = kzalloc(size, GFP_KERNEL);
1f12e32f
TG
357
358 for_each_present_cpu(cpu) {
359 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
360
361 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
362 continue;
363 if (!topology_update_package_map(apicid, cpu))
364 continue;
365 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
366 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
367 set_cpu_possible(cpu, false);
368 set_cpu_present(cpu, false);
369 }
7b0501b1
JO
370
371 if (logical_packages > __max_logical_packages) {
372 pr_warn("Detected more packages (%u), then computed by BIOS data (%u).\n",
373 logical_packages, __max_logical_packages);
374 logical_packages_frozen = true;
375 __max_logical_packages = logical_packages;
376 }
377
378 pr_info("Max logical packages: %u\n", __max_logical_packages);
1f12e32f
TG
379}
380
30106c17
FY
381void __init smp_store_boot_cpu_info(void)
382{
383 int id = 0; /* CPU 0 */
384 struct cpuinfo_x86 *c = &cpu_data(id);
385
386 *c = boot_cpu_data;
387 c->cpu_index = id;
1f12e32f 388 smp_init_package_map();
30106c17
FY
389}
390
1d89a7f0
GOC
391/*
392 * The bootstrap kernel entry code has set these up. Save them for
393 * a given CPU
394 */
148f9bb8 395void smp_store_cpu_info(int id)
1d89a7f0
GOC
396{
397 struct cpuinfo_x86 *c = &cpu_data(id);
398
b3d7336d 399 *c = boot_cpu_data;
1d89a7f0 400 c->cpu_index = id;
30106c17
FY
401 /*
402 * During boot time, CPU0 has this setup already. Save the info when
403 * bringing up AP or offlined CPU0.
404 */
405 identify_secondary_cpu(c);
1d89a7f0
GOC
406}
407
cebf15eb
DH
408static bool
409topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
410{
411 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
412
413 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
414}
415
148f9bb8 416static bool
316ad248 417topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
d4fbe4f0 418{
316ad248
PZ
419 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
420
cebf15eb 421 return !WARN_ONCE(!topology_same_node(c, o),
316ad248
PZ
422 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
423 "[node: %d != %d]. Ignoring dependency.\n",
424 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
425}
426
7d79a7bd 427#define link_mask(mfunc, c1, c2) \
316ad248 428do { \
7d79a7bd
BG
429 cpumask_set_cpu((c1), mfunc(c2)); \
430 cpumask_set_cpu((c2), mfunc(c1)); \
316ad248
PZ
431} while (0)
432
148f9bb8 433static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
316ad248 434{
362f924b 435 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
316ad248
PZ
436 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
437
438 if (c->phys_proc_id == o->phys_proc_id &&
439 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
8196dab4 440 c->cpu_core_id == o->cpu_core_id)
316ad248
PZ
441 return topology_sane(c, o, "smt");
442
443 } else if (c->phys_proc_id == o->phys_proc_id &&
444 c->cpu_core_id == o->cpu_core_id) {
445 return topology_sane(c, o, "smt");
446 }
447
448 return false;
449}
450
148f9bb8 451static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
316ad248
PZ
452{
453 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
454
455 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
456 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
457 return topology_sane(c, o, "llc");
458
459 return false;
d4fbe4f0
AH
460}
461
cebf15eb
DH
462/*
463 * Unlike the other levels, we do not enforce keeping a
464 * multicore group inside a NUMA node. If this happens, we will
465 * discard the MC level of the topology later.
466 */
467static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
316ad248 468{
cebf15eb
DH
469 if (c->phys_proc_id == o->phys_proc_id)
470 return true;
316ad248
PZ
471 return false;
472}
1d89a7f0 473
8f37961c 474static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
cebf15eb
DH
475#ifdef CONFIG_SCHED_SMT
476 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
477#endif
478#ifdef CONFIG_SCHED_MC
479 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
480#endif
481 { NULL, },
482};
8f37961c
TC
483
484static struct sched_domain_topology_level x86_topology[] = {
485#ifdef CONFIG_SCHED_SMT
486 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
487#endif
488#ifdef CONFIG_SCHED_MC
489 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
490#endif
491 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
492 { NULL, },
493};
494
cebf15eb 495/*
8f37961c
TC
496 * Set if a package/die has multiple NUMA nodes inside.
497 * AMD Magny-Cours and Intel Cluster-on-Die have this.
cebf15eb 498 */
8f37961c 499static bool x86_has_numa_in_package;
cebf15eb 500
148f9bb8 501void set_cpu_sibling_map(int cpu)
768d9505 502{
316ad248 503 bool has_smt = smp_num_siblings > 1;
b0bc225d 504 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
768d9505 505 struct cpuinfo_x86 *c = &cpu_data(cpu);
316ad248 506 struct cpuinfo_x86 *o;
70b8301f 507 int i, threads;
768d9505 508
c2d1cec1 509 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
768d9505 510
b0bc225d 511 if (!has_mp) {
7d79a7bd 512 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
316ad248 513 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
7d79a7bd 514 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
768d9505
GC
515 c->booted_cores = 1;
516 return;
517 }
518
c2d1cec1 519 for_each_cpu(i, cpu_sibling_setup_mask) {
316ad248
PZ
520 o = &cpu_data(i);
521
522 if ((i == cpu) || (has_smt && match_smt(c, o)))
7d79a7bd 523 link_mask(topology_sibling_cpumask, cpu, i);
316ad248 524
b0bc225d 525 if ((i == cpu) || (has_mp && match_llc(c, o)))
7d79a7bd 526 link_mask(cpu_llc_shared_mask, cpu, i);
316ad248 527
ceb1cbac
KB
528 }
529
530 /*
531 * This needs a separate iteration over the cpus because we rely on all
7d79a7bd 532 * topology_sibling_cpumask links to be set-up.
ceb1cbac
KB
533 */
534 for_each_cpu(i, cpu_sibling_setup_mask) {
535 o = &cpu_data(i);
536
cebf15eb 537 if ((i == cpu) || (has_mp && match_die(c, o))) {
7d79a7bd 538 link_mask(topology_core_cpumask, cpu, i);
316ad248 539
768d9505
GC
540 /*
541 * Does this new cpu bringup a new core?
542 */
7d79a7bd
BG
543 if (cpumask_weight(
544 topology_sibling_cpumask(cpu)) == 1) {
768d9505
GC
545 /*
546 * for each core in package, increment
547 * the booted_cores for this new cpu
548 */
7d79a7bd
BG
549 if (cpumask_first(
550 topology_sibling_cpumask(i)) == i)
768d9505
GC
551 c->booted_cores++;
552 /*
553 * increment the core count for all
554 * the other cpus in this package
555 */
556 if (i != cpu)
557 cpu_data(i).booted_cores++;
558 } else if (i != cpu && !c->booted_cores)
559 c->booted_cores = cpu_data(i).booted_cores;
560 }
728e5653 561 if (match_die(c, o) && !topology_same_node(c, o))
8f37961c 562 x86_has_numa_in_package = true;
768d9505 563 }
70b8301f
AK
564
565 threads = cpumask_weight(topology_sibling_cpumask(cpu));
566 if (threads > __max_smt_threads)
567 __max_smt_threads = threads;
768d9505
GC
568}
569
70708a18 570/* maps the cpu to the sched domain representing multi-core */
030bb203 571const struct cpumask *cpu_coregroup_mask(int cpu)
70708a18 572{
9f646389 573 return cpu_llc_shared_mask(cpu);
030bb203
RR
574}
575
a4928cff 576static void impress_friends(void)
904541e2
GOC
577{
578 int cpu;
579 unsigned long bogosum = 0;
580 /*
581 * Allow the user to impress friends.
582 */
c767a54b 583 pr_debug("Before bogomips\n");
904541e2 584 for_each_possible_cpu(cpu)
c2d1cec1 585 if (cpumask_test_cpu(cpu, cpu_callout_mask))
904541e2 586 bogosum += cpu_data(cpu).loops_per_jiffy;
c767a54b 587 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
f68e00a3 588 num_online_cpus(),
904541e2
GOC
589 bogosum/(500000/HZ),
590 (bogosum/(5000/HZ))%100);
591
c767a54b 592 pr_debug("Before bogocount - setting activated=1\n");
904541e2
GOC
593}
594
569712b2 595void __inquire_remote_apic(int apicid)
cb3c8b90
GOC
596{
597 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
a6c23905 598 const char * const names[] = { "ID", "VERSION", "SPIV" };
cb3c8b90
GOC
599 int timeout;
600 u32 status;
601
c767a54b 602 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
cb3c8b90
GOC
603
604 for (i = 0; i < ARRAY_SIZE(regs); i++) {
c767a54b 605 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
cb3c8b90
GOC
606
607 /*
608 * Wait for idle.
609 */
610 status = safe_apic_wait_icr_idle();
611 if (status)
c767a54b 612 pr_cont("a previous APIC delivery may have failed\n");
cb3c8b90 613
1b374e4d 614 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
cb3c8b90
GOC
615
616 timeout = 0;
617 do {
618 udelay(100);
619 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
620 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
621
622 switch (status) {
623 case APIC_ICR_RR_VALID:
624 status = apic_read(APIC_RRR);
c767a54b 625 pr_cont("%08x\n", status);
cb3c8b90
GOC
626 break;
627 default:
c767a54b 628 pr_cont("failed\n");
cb3c8b90
GOC
629 }
630 }
631}
632
d68921f9
LB
633/*
634 * The Multiprocessor Specification 1.4 (1997) example code suggests
635 * that there should be a 10ms delay between the BSP asserting INIT
636 * and de-asserting INIT, when starting a remote processor.
637 * But that slows boot and resume on modern processors, which include
638 * many cores and don't require that delay.
639 *
640 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
1a744cb3 641 * Modern processor families are quirked to remove the delay entirely.
d68921f9
LB
642 */
643#define UDELAY_10MS_DEFAULT 10000
644
656279a1 645static unsigned int init_udelay = UINT_MAX;
d68921f9
LB
646
647static int __init cpu_init_udelay(char *str)
648{
649 get_option(&str, &init_udelay);
650
651 return 0;
652}
653early_param("cpu_init_udelay", cpu_init_udelay);
654
1a744cb3
LB
655static void __init smp_quirk_init_udelay(void)
656{
657 /* if cmdline changed it from default, leave it alone */
656279a1 658 if (init_udelay != UINT_MAX)
1a744cb3
LB
659 return;
660
661 /* if modern processor, use no delay */
662 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
656279a1 663 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
1a744cb3 664 init_udelay = 0;
656279a1
LB
665 return;
666 }
f1ccd249
LB
667 /* else, use legacy delay */
668 init_udelay = UDELAY_10MS_DEFAULT;
1a744cb3
LB
669}
670
cb3c8b90
GOC
671/*
672 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
673 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
674 * won't ... remember to clear down the APIC, etc later.
675 */
148f9bb8 676int
e1c467e6 677wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
cb3c8b90
GOC
678{
679 unsigned long send_status, accept_status = 0;
680 int maxlvt;
681
682 /* Target chip */
cb3c8b90
GOC
683 /* Boot on the stack */
684 /* Kick the second */
e1c467e6 685 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
cb3c8b90 686
cfc1b9a6 687 pr_debug("Waiting for send to finish...\n");
cb3c8b90
GOC
688 send_status = safe_apic_wait_icr_idle();
689
690 /*
691 * Give the other CPU some time to accept the IPI.
692 */
693 udelay(200);
cff9ab2b 694 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
59ef48a5
CG
695 maxlvt = lapic_get_maxlvt();
696 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
697 apic_write(APIC_ESR, 0);
698 accept_status = (apic_read(APIC_ESR) & 0xEF);
699 }
c767a54b 700 pr_debug("NMI sent\n");
cb3c8b90
GOC
701
702 if (send_status)
c767a54b 703 pr_err("APIC never delivered???\n");
cb3c8b90 704 if (accept_status)
c767a54b 705 pr_err("APIC delivery error (%lx)\n", accept_status);
cb3c8b90
GOC
706
707 return (send_status | accept_status);
708}
cb3c8b90 709
148f9bb8 710static int
569712b2 711wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
cb3c8b90 712{
f5d6a52f 713 unsigned long send_status = 0, accept_status = 0;
cb3c8b90
GOC
714 int maxlvt, num_starts, j;
715
593f4a78
MR
716 maxlvt = lapic_get_maxlvt();
717
cb3c8b90
GOC
718 /*
719 * Be paranoid about clearing APIC errors.
720 */
cff9ab2b 721 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
593f4a78
MR
722 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
723 apic_write(APIC_ESR, 0);
cb3c8b90
GOC
724 apic_read(APIC_ESR);
725 }
726
c767a54b 727 pr_debug("Asserting INIT\n");
cb3c8b90
GOC
728
729 /*
730 * Turn INIT on target chip
731 */
cb3c8b90
GOC
732 /*
733 * Send IPI
734 */
1b374e4d
SS
735 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
736 phys_apicid);
cb3c8b90 737
cfc1b9a6 738 pr_debug("Waiting for send to finish...\n");
cb3c8b90
GOC
739 send_status = safe_apic_wait_icr_idle();
740
7cb68598 741 udelay(init_udelay);
cb3c8b90 742
c767a54b 743 pr_debug("Deasserting INIT\n");
cb3c8b90
GOC
744
745 /* Target chip */
cb3c8b90 746 /* Send IPI */
1b374e4d 747 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
cb3c8b90 748
cfc1b9a6 749 pr_debug("Waiting for send to finish...\n");
cb3c8b90
GOC
750 send_status = safe_apic_wait_icr_idle();
751
752 mb();
cb3c8b90
GOC
753
754 /*
755 * Should we send STARTUP IPIs ?
756 *
757 * Determine this based on the APIC version.
758 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
759 */
cff9ab2b 760 if (APIC_INTEGRATED(boot_cpu_apic_version))
cb3c8b90
GOC
761 num_starts = 2;
762 else
763 num_starts = 0;
764
cb3c8b90
GOC
765 /*
766 * Run STARTUP IPI loop.
767 */
c767a54b 768 pr_debug("#startup loops: %d\n", num_starts);
cb3c8b90 769
cb3c8b90 770 for (j = 1; j <= num_starts; j++) {
c767a54b 771 pr_debug("Sending STARTUP #%d\n", j);
593f4a78
MR
772 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
773 apic_write(APIC_ESR, 0);
cb3c8b90 774 apic_read(APIC_ESR);
c767a54b 775 pr_debug("After apic_write\n");
cb3c8b90
GOC
776
777 /*
778 * STARTUP IPI
779 */
780
781 /* Target chip */
cb3c8b90
GOC
782 /* Boot on the stack */
783 /* Kick the second */
1b374e4d
SS
784 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
785 phys_apicid);
cb3c8b90
GOC
786
787 /*
788 * Give the other CPU some time to accept the IPI.
789 */
fcafddec
LB
790 if (init_udelay == 0)
791 udelay(10);
792 else
a9bcaa02 793 udelay(300);
cb3c8b90 794
c767a54b 795 pr_debug("Startup point 1\n");
cb3c8b90 796
cfc1b9a6 797 pr_debug("Waiting for send to finish...\n");
cb3c8b90
GOC
798 send_status = safe_apic_wait_icr_idle();
799
800 /*
801 * Give the other CPU some time to accept the IPI.
802 */
fcafddec
LB
803 if (init_udelay == 0)
804 udelay(10);
805 else
a9bcaa02 806 udelay(200);
cb3c8b90 807
593f4a78 808 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
cb3c8b90 809 apic_write(APIC_ESR, 0);
cb3c8b90
GOC
810 accept_status = (apic_read(APIC_ESR) & 0xEF);
811 if (send_status || accept_status)
812 break;
813 }
c767a54b 814 pr_debug("After Startup\n");
cb3c8b90
GOC
815
816 if (send_status)
c767a54b 817 pr_err("APIC never delivered???\n");
cb3c8b90 818 if (accept_status)
c767a54b 819 pr_err("APIC delivery error (%lx)\n", accept_status);
cb3c8b90
GOC
820
821 return (send_status | accept_status);
822}
cb3c8b90 823
a17bce4d
BP
824void smp_announce(void)
825{
826 int num_nodes = num_online_nodes();
827
828 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
829 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
830}
831
2eaad1fd 832/* reduce the number of lines printed when booting a large cpu count system */
148f9bb8 833static void announce_cpu(int cpu, int apicid)
2eaad1fd
MT
834{
835 static int current_node = -1;
4adc8b71 836 int node = early_cpu_to_node(cpu);
a17bce4d 837 static int width, node_width;
646e29a1
BP
838
839 if (!width)
840 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
2eaad1fd 841
a17bce4d
BP
842 if (!node_width)
843 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
844
845 if (cpu == 1)
846 printk(KERN_INFO "x86: Booting SMP configuration:\n");
847
2eaad1fd
MT
848 if (system_state == SYSTEM_BOOTING) {
849 if (node != current_node) {
850 if (current_node > (-1))
a17bce4d 851 pr_cont("\n");
2eaad1fd 852 current_node = node;
a17bce4d
BP
853
854 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
855 node_width - num_digits(node), " ", node);
2eaad1fd 856 }
646e29a1
BP
857
858 /* Add padding for the BSP */
859 if (cpu == 1)
860 pr_cont("%*s", width + 1, " ");
861
862 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
863
2eaad1fd
MT
864 } else
865 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
866 node, cpu, apicid);
867}
868
e1c467e6
FY
869static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
870{
871 int cpu;
872
873 cpu = smp_processor_id();
874 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
875 return NMI_HANDLED;
876
877 return NMI_DONE;
878}
879
880/*
881 * Wake up AP by INIT, INIT, STARTUP sequence.
882 *
883 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
884 * boot-strap code which is not a desired behavior for waking up BSP. To
885 * void the boot-strap code, wake up CPU0 by NMI instead.
886 *
887 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
888 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
889 * We'll change this code in the future to wake up hard offlined CPU0 if
890 * real platform and request are available.
891 */
148f9bb8 892static int
e1c467e6
FY
893wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
894 int *cpu0_nmi_registered)
895{
896 int id;
897 int boot_error;
898
ea7bdc65
JK
899 preempt_disable();
900
e1c467e6
FY
901 /*
902 * Wake up AP by INIT, INIT, STARTUP sequence.
903 */
ea7bdc65
JK
904 if (cpu) {
905 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
906 goto out;
907 }
e1c467e6
FY
908
909 /*
910 * Wake up BSP by nmi.
911 *
912 * Register a NMI handler to help wake up CPU0.
913 */
914 boot_error = register_nmi_handler(NMI_LOCAL,
915 wakeup_cpu0_nmi, 0, "wake_cpu0");
916
917 if (!boot_error) {
918 enable_start_cpu0 = 1;
919 *cpu0_nmi_registered = 1;
920 if (apic->dest_logical == APIC_DEST_LOGICAL)
921 id = cpu0_logical_apicid;
922 else
923 id = apicid;
924 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
925 }
ea7bdc65
JK
926
927out:
928 preempt_enable();
e1c467e6
FY
929
930 return boot_error;
931}
932
3f85483b
BO
933void common_cpu_up(unsigned int cpu, struct task_struct *idle)
934{
935 /* Just in case we booted with a single CPU. */
936 alternatives_enable_smp();
937
938 per_cpu(current_task, cpu) = idle;
939
940#ifdef CONFIG_X86_32
941 /* Stack for startup_32 can be just as for start_secondary onwards */
942 irq_ctx_init(cpu);
943 per_cpu(cpu_current_top_of_stack, cpu) =
944 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
945#else
3f85483b
BO
946 initial_gs = per_cpu_offset(cpu);
947#endif
3f85483b
BO
948}
949
cb3c8b90
GOC
950/*
951 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
952 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1f5bcabf
IM
953 * Returns zero if CPU booted OK, else error code from
954 * ->wakeup_secondary_cpu.
cb3c8b90 955 */
148f9bb8 956static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
cb3c8b90 957{
48927bbb 958 volatile u32 *trampoline_status =
b429dbf6 959 (volatile u32 *) __va(real_mode_header->trampoline_status);
48927bbb 960 /* start_ip had better be page-aligned! */
f37240f1 961 unsigned long start_ip = real_mode_header->trampoline_start;
48927bbb 962
cb3c8b90 963 unsigned long boot_error = 0;
e1c467e6 964 int cpu0_nmi_registered = 0;
ce4b1b16 965 unsigned long timeout;
cb3c8b90 966
7eb43a6d
TG
967 idle->thread.sp = (unsigned long) (((struct pt_regs *)
968 (THREAD_SIZE + task_stack_page(idle))) - 1);
cb3c8b90 969
a939098a 970 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
3e970473 971 initial_code = (unsigned long)start_secondary;
b32f96c7 972 initial_stack = idle->thread.sp;
cb3c8b90 973
20d5e4a9
ZG
974 /*
975 * Enable the espfix hack for this CPU
976 */
977#ifdef CONFIG_X86_ESPFIX64
978 init_espfix_ap(cpu);
979#endif
980
2eaad1fd
MT
981 /* So we see what's up */
982 announce_cpu(cpu, apicid);
cb3c8b90
GOC
983
984 /*
985 * This grunge runs the startup process for
986 * the targeted processor.
987 */
988
34d05591 989 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
cb3c8b90 990
cfc1b9a6 991 pr_debug("Setting warm reset code and vector.\n");
cb3c8b90 992
34d05591
JS
993 smpboot_setup_warm_reset_vector(start_ip);
994 /*
995 * Be paranoid about clearing APIC errors.
db96b0a0 996 */
cff9ab2b 997 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
db96b0a0
CG
998 apic_write(APIC_ESR, 0);
999 apic_read(APIC_ESR);
1000 }
34d05591 1001 }
cb3c8b90 1002
ce4b1b16
IM
1003 /*
1004 * AP might wait on cpu_callout_mask in cpu_init() with
1005 * cpu_initialized_mask set if previous attempt to online
1006 * it timed-out. Clear cpu_initialized_mask so that after
1007 * INIT/SIPI it could start with a clean state.
1008 */
1009 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1010 smp_mb();
1011
cb3c8b90 1012 /*
e1c467e6
FY
1013 * Wake up a CPU in difference cases:
1014 * - Use the method in the APIC driver if it's defined
1015 * Otherwise,
1016 * - Use an INIT boot APIC message for APs or NMI for BSP.
cb3c8b90 1017 */
1f5bcabf
IM
1018 if (apic->wakeup_secondary_cpu)
1019 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1020 else
e1c467e6
FY
1021 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1022 &cpu0_nmi_registered);
cb3c8b90
GOC
1023
1024 if (!boot_error) {
1025 /*
6e38f1e7 1026 * Wait 10s total for first sign of life from AP
cb3c8b90 1027 */
ce4b1b16
IM
1028 boot_error = -1;
1029 timeout = jiffies + 10*HZ;
1030 while (time_before(jiffies, timeout)) {
1031 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1032 /*
1033 * Tell AP to proceed with initialization
1034 */
1035 cpumask_set_cpu(cpu, cpu_callout_mask);
1036 boot_error = 0;
1037 break;
1038 }
ce4b1b16
IM
1039 schedule();
1040 }
1041 }
cb3c8b90 1042
ce4b1b16 1043 if (!boot_error) {
cb3c8b90 1044 /*
ce4b1b16 1045 * Wait till AP completes initial initialization
cb3c8b90 1046 */
ce4b1b16 1047 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
68f202e4
SS
1048 /*
1049 * Allow other tasks to run while we wait for the
1050 * AP to come online. This also gives a chance
1051 * for the MTRR work(triggered by the AP coming online)
1052 * to be completed in the stop machine context.
1053 */
1054 schedule();
cb3c8b90 1055 }
cb3c8b90
GOC
1056 }
1057
1058 /* mark "stuck" area as not stuck */
48927bbb 1059 *trampoline_status = 0;
cb3c8b90 1060
02421f98
YL
1061 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1062 /*
1063 * Cleanup possible dangling ends...
1064 */
1065 smpboot_restore_warm_reset_vector();
1066 }
e1c467e6
FY
1067 /*
1068 * Clean up the nmi handler. Do this after the callin and callout sync
1069 * to avoid impact of possible long unregister time.
1070 */
1071 if (cpu0_nmi_registered)
1072 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1073
cb3c8b90
GOC
1074 return boot_error;
1075}
1076
148f9bb8 1077int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
cb3c8b90 1078{
a21769a4 1079 int apicid = apic->cpu_present_to_apicid(cpu);
cb3c8b90
GOC
1080 unsigned long flags;
1081 int err;
1082
1083 WARN_ON(irqs_disabled());
1084
cfc1b9a6 1085 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
cb3c8b90 1086
30106c17 1087 if (apicid == BAD_APICID ||
c284b42a 1088 !physid_isset(apicid, phys_cpu_present_map) ||
fa63030e 1089 !apic->apic_id_valid(apicid)) {
c767a54b 1090 pr_err("%s: bad cpu %d\n", __func__, cpu);
cb3c8b90
GOC
1091 return -EINVAL;
1092 }
1093
1094 /*
1095 * Already booted CPU?
1096 */
c2d1cec1 1097 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
cfc1b9a6 1098 pr_debug("do_boot_cpu %d Already started\n", cpu);
cb3c8b90
GOC
1099 return -ENOSYS;
1100 }
1101
1102 /*
1103 * Save current MTRR state in case it was changed since early boot
1104 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1105 */
1106 mtrr_save_state();
1107
2a442c9c
PM
1108 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1109 err = cpu_check_up_prepare(cpu);
1110 if (err && err != -EBUSY)
1111 return err;
cb3c8b90 1112
644c1541
VP
1113 /* the FPU context is blank, nobody can own it */
1114 __cpu_disable_lazy_restore(cpu);
1115
3f85483b
BO
1116 common_cpu_up(cpu, tidle);
1117
7eb43a6d 1118 err = do_boot_cpu(apicid, cpu, tidle);
61165d7a 1119 if (err) {
feef1e8e 1120 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
61165d7a 1121 return -EIO;
cb3c8b90
GOC
1122 }
1123
1124 /*
1125 * Check TSC synchronization with the AP (keep irqs disabled
1126 * while doing so):
1127 */
1128 local_irq_save(flags);
1129 check_tsc_sync_source(cpu);
1130 local_irq_restore(flags);
1131
7c04e64a 1132 while (!cpu_online(cpu)) {
cb3c8b90
GOC
1133 cpu_relax();
1134 touch_nmi_watchdog();
1135 }
1136
1137 return 0;
1138}
1139
7167d08e
HK
1140/**
1141 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1142 */
1143void arch_disable_smp_support(void)
1144{
1145 disable_ioapic_support();
1146}
1147
8aef135c
GOC
1148/*
1149 * Fall back to non SMP mode after errors.
1150 *
1151 * RED-PEN audit/test this more. I bet there is more state messed up here.
1152 */
1153static __init void disable_smp(void)
1154{
613c25ef
TG
1155 pr_info("SMP disabled\n");
1156
ef4c59a4
TG
1157 disable_ioapic_support();
1158
4f062896
RR
1159 init_cpu_present(cpumask_of(0));
1160 init_cpu_possible(cpumask_of(0));
0f385d1d 1161
8aef135c 1162 if (smp_found_config)
b6df1b8b 1163 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
8aef135c 1164 else
b6df1b8b 1165 physid_set_mask_of_physid(0, &phys_cpu_present_map);
7d79a7bd
BG
1166 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1167 cpumask_set_cpu(0, topology_core_cpumask(0));
8aef135c
GOC
1168}
1169
613c25ef
TG
1170enum {
1171 SMP_OK,
1172 SMP_NO_CONFIG,
1173 SMP_NO_APIC,
1174 SMP_FORCE_UP,
1175};
1176
8aef135c
GOC
1177/*
1178 * Various sanity checks.
1179 */
1180static int __init smp_sanity_check(unsigned max_cpus)
1181{
ac23d4ee 1182 preempt_disable();
a58f03b0 1183
1ff2f20d 1184#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
a58f03b0
YL
1185 if (def_to_bigsmp && nr_cpu_ids > 8) {
1186 unsigned int cpu;
1187 unsigned nr;
1188
c767a54b
JP
1189 pr_warn("More than 8 CPUs detected - skipping them\n"
1190 "Use CONFIG_X86_BIGSMP\n");
a58f03b0
YL
1191
1192 nr = 0;
1193 for_each_present_cpu(cpu) {
1194 if (nr >= 8)
c2d1cec1 1195 set_cpu_present(cpu, false);
a58f03b0
YL
1196 nr++;
1197 }
1198
1199 nr = 0;
1200 for_each_possible_cpu(cpu) {
1201 if (nr >= 8)
c2d1cec1 1202 set_cpu_possible(cpu, false);
a58f03b0
YL
1203 nr++;
1204 }
1205
1206 nr_cpu_ids = 8;
1207 }
1208#endif
1209
8aef135c 1210 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
c767a54b 1211 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
55c395b4
MT
1212 hard_smp_processor_id());
1213
8aef135c
GOC
1214 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1215 }
1216
1217 /*
1218 * If we couldn't find an SMP configuration at boot time,
1219 * get out of here now!
1220 */
1221 if (!smp_found_config && !acpi_lapic) {
ac23d4ee 1222 preempt_enable();
c767a54b 1223 pr_notice("SMP motherboard not detected\n");
613c25ef 1224 return SMP_NO_CONFIG;
8aef135c
GOC
1225 }
1226
1227 /*
1228 * Should not be necessary because the MP table should list the boot
1229 * CPU too, but we do it for the sake of robustness anyway.
1230 */
a27a6210 1231 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
c767a54b
JP
1232 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1233 boot_cpu_physical_apicid);
8aef135c
GOC
1234 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1235 }
ac23d4ee 1236 preempt_enable();
8aef135c
GOC
1237
1238 /*
1239 * If we couldn't find a local APIC, then get out of here now!
1240 */
cff9ab2b 1241 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
93984fbd 1242 !boot_cpu_has(X86_FEATURE_APIC)) {
103428e5
CG
1243 if (!disable_apic) {
1244 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1245 boot_cpu_physical_apicid);
c767a54b 1246 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
103428e5 1247 }
613c25ef 1248 return SMP_NO_APIC;
8aef135c
GOC
1249 }
1250
8aef135c
GOC
1251 /*
1252 * If SMP should be disabled, then really disable it!
1253 */
1254 if (!max_cpus) {
c767a54b 1255 pr_info("SMP mode deactivated\n");
613c25ef 1256 return SMP_FORCE_UP;
8aef135c
GOC
1257 }
1258
613c25ef 1259 return SMP_OK;
8aef135c
GOC
1260}
1261
1262static void __init smp_cpu_index_default(void)
1263{
1264 int i;
1265 struct cpuinfo_x86 *c;
1266
7c04e64a 1267 for_each_possible_cpu(i) {
8aef135c
GOC
1268 c = &cpu_data(i);
1269 /* mark all to hotplug */
9628937d 1270 c->cpu_index = nr_cpu_ids;
8aef135c
GOC
1271 }
1272}
1273
1274/*
1275 * Prepare for SMP bootup. The MP table or ACPI has been read
1276 * earlier. Just do some sanity checking here and enable APIC mode.
1277 */
1278void __init native_smp_prepare_cpus(unsigned int max_cpus)
1279{
7ad728f9
RR
1280 unsigned int i;
1281
8aef135c 1282 smp_cpu_index_default();
792363d2 1283
8aef135c
GOC
1284 /*
1285 * Setup boot CPU information
1286 */
30106c17 1287 smp_store_boot_cpu_info(); /* Final full version of the data */
792363d2
YL
1288 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1289 mb();
bd22a2f1 1290
7ad728f9 1291 for_each_possible_cpu(i) {
79f55997
LZ
1292 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1293 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
b3d7336d 1294 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
7ad728f9 1295 }
8f37961c
TC
1296
1297 /*
1298 * Set 'default' x86 topology, this matches default_topology() in that
1299 * it has NUMA nodes as a topology level. See also
1300 * native_smp_cpus_done().
1301 *
1302 * Must be done before set_cpus_sibling_map() is ran.
1303 */
1304 set_sched_topology(x86_topology);
1305
8aef135c
GOC
1306 set_cpu_sibling_map(0);
1307
613c25ef
TG
1308 switch (smp_sanity_check(max_cpus)) {
1309 case SMP_NO_CONFIG:
8aef135c 1310 disable_smp();
613c25ef
TG
1311 if (APIC_init_uniprocessor())
1312 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1313 return;
1314 case SMP_NO_APIC:
1315 disable_smp();
1316 return;
1317 case SMP_FORCE_UP:
1318 disable_smp();
374aab33 1319 apic_bsp_setup(false);
250a1ac6 1320 return;
613c25ef
TG
1321 case SMP_OK:
1322 break;
8aef135c
GOC
1323 }
1324
4c9961d5 1325 if (read_apic_id() != boot_cpu_physical_apicid) {
8aef135c 1326 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
4c9961d5 1327 read_apic_id(), boot_cpu_physical_apicid);
8aef135c
GOC
1328 /* Or can we switch back to PIC here? */
1329 }
1330
384d9fe3 1331 default_setup_apic_routing();
374aab33 1332 cpu0_logical_apicid = apic_bsp_setup(false);
ef4c59a4 1333
c767a54b 1334 pr_info("CPU%d: ", 0);
8aef135c 1335 print_cpu_info(&cpu_data(0));
c4bd1fda
MS
1336
1337 if (is_uv_system())
1338 uv_system_init();
d0af9eed
SS
1339
1340 set_mtrr_aps_delayed_init();
1a744cb3
LB
1341
1342 smp_quirk_init_udelay();
8aef135c 1343}
d0af9eed
SS
1344
1345void arch_enable_nonboot_cpus_begin(void)
1346{
1347 set_mtrr_aps_delayed_init();
1348}
1349
1350void arch_enable_nonboot_cpus_end(void)
1351{
1352 mtrr_aps_init();
1353}
1354
a8db8453
GOC
1355/*
1356 * Early setup to make printk work.
1357 */
1358void __init native_smp_prepare_boot_cpu(void)
1359{
1360 int me = smp_processor_id();
552be871 1361 switch_to_new_gdt(me);
c2d1cec1
MT
1362 /* already set me in cpu_online_mask in boot_cpu_init() */
1363 cpumask_set_cpu(me, cpu_callout_mask);
2a442c9c 1364 cpu_set_state_online(me);
a8db8453
GOC
1365}
1366
83f7eb9c
GOC
1367void __init native_smp_cpus_done(unsigned int max_cpus)
1368{
c767a54b 1369 pr_debug("Boot done\n");
83f7eb9c 1370
8f37961c
TC
1371 if (x86_has_numa_in_package)
1372 set_sched_topology(x86_numa_in_package_topology);
1373
99e8b9ca 1374 nmi_selftest();
83f7eb9c 1375 impress_friends();
83f7eb9c 1376 setup_ioapic_dest();
d0af9eed 1377 mtrr_aps_init();
83f7eb9c
GOC
1378}
1379
3b11ce7f
MT
1380static int __initdata setup_possible_cpus = -1;
1381static int __init _setup_possible_cpus(char *str)
1382{
1383 get_option(&str, &setup_possible_cpus);
1384 return 0;
1385}
1386early_param("possible_cpus", _setup_possible_cpus);
1387
1388
68a1c3f8 1389/*
4f062896 1390 * cpu_possible_mask should be static, it cannot change as cpu's
68a1c3f8
GC
1391 * are onlined, or offlined. The reason is per-cpu data-structures
1392 * are allocated by some modules at init time, and dont expect to
1393 * do this dynamically on cpu arrival/departure.
4f062896 1394 * cpu_present_mask on the other hand can change dynamically.
68a1c3f8
GC
1395 * In case when cpu_hotplug is not compiled, then we resort to current
1396 * behaviour, which is cpu_possible == cpu_present.
1397 * - Ashok Raj
1398 *
1399 * Three ways to find out the number of additional hotplug CPUs:
1400 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
3b11ce7f 1401 * - The user can overwrite it with possible_cpus=NUM
68a1c3f8
GC
1402 * - Otherwise don't reserve additional CPUs.
1403 * We do this because additional CPUs waste a lot of memory.
1404 * -AK
1405 */
1406__init void prefill_possible_map(void)
1407{
cb48bb59 1408 int i, possible;
68a1c3f8 1409
2a51fe08
PB
1410 /* No boot processor was found in mptable or ACPI MADT */
1411 if (!num_processors) {
ff856051
VS
1412 if (boot_cpu_has(X86_FEATURE_APIC)) {
1413 int apicid = boot_cpu_physical_apicid;
1414 int cpu = hard_smp_processor_id();
2a51fe08 1415
ff856051 1416 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
2a51fe08 1417
ff856051
VS
1418 /* Make sure boot cpu is enumerated */
1419 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1420 apic->apic_id_valid(apicid))
1421 generic_processor_info(apicid, boot_cpu_apic_version);
1422 }
2a51fe08
PB
1423
1424 if (!num_processors)
1425 num_processors = 1;
1426 }
329513a3 1427
5f2eb550
JB
1428 i = setup_max_cpus ?: 1;
1429 if (setup_possible_cpus == -1) {
1430 possible = num_processors;
1431#ifdef CONFIG_HOTPLUG_CPU
1432 if (setup_max_cpus)
1433 possible += disabled_cpus;
1434#else
1435 if (possible > i)
1436 possible = i;
1437#endif
1438 } else
3b11ce7f
MT
1439 possible = setup_possible_cpus;
1440
730cf272
MT
1441 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1442
2b633e3f
YL
1443 /* nr_cpu_ids could be reduced via nr_cpus= */
1444 if (possible > nr_cpu_ids) {
c767a54b 1445 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
2b633e3f
YL
1446 possible, nr_cpu_ids);
1447 possible = nr_cpu_ids;
3b11ce7f 1448 }
68a1c3f8 1449
5f2eb550
JB
1450#ifdef CONFIG_HOTPLUG_CPU
1451 if (!setup_max_cpus)
1452#endif
1453 if (possible > i) {
c767a54b 1454 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
5f2eb550
JB
1455 possible, setup_max_cpus);
1456 possible = i;
1457 }
1458
c767a54b 1459 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
68a1c3f8
GC
1460 possible, max_t(int, possible - num_processors, 0));
1461
1462 for (i = 0; i < possible; i++)
c2d1cec1 1463 set_cpu_possible(i, true);
5f2eb550
JB
1464 for (; i < NR_CPUS; i++)
1465 set_cpu_possible(i, false);
3461b0af
MT
1466
1467 nr_cpu_ids = possible;
68a1c3f8 1468}
69c18c15 1469
14adf855
CE
1470#ifdef CONFIG_HOTPLUG_CPU
1471
70b8301f
AK
1472/* Recompute SMT state for all CPUs on offline */
1473static void recompute_smt_state(void)
1474{
1475 int max_threads, cpu;
1476
1477 max_threads = 0;
1478 for_each_online_cpu (cpu) {
1479 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1480
1481 if (threads > max_threads)
1482 max_threads = threads;
1483 }
1484 __max_smt_threads = max_threads;
1485}
1486
14adf855
CE
1487static void remove_siblinginfo(int cpu)
1488{
1489 int sibling;
1490 struct cpuinfo_x86 *c = &cpu_data(cpu);
1491
7d79a7bd
BG
1492 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1493 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
14adf855
CE
1494 /*/
1495 * last thread sibling in this cpu core going down
1496 */
7d79a7bd 1497 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
14adf855
CE
1498 cpu_data(sibling).booted_cores--;
1499 }
1500
7d79a7bd
BG
1501 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1502 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
03bd4e1f
WL
1503 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1504 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1505 cpumask_clear(cpu_llc_shared_mask(cpu));
7d79a7bd
BG
1506 cpumask_clear(topology_sibling_cpumask(cpu));
1507 cpumask_clear(topology_core_cpumask(cpu));
14adf855
CE
1508 c->phys_proc_id = 0;
1509 c->cpu_core_id = 0;
c2d1cec1 1510 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
70b8301f 1511 recompute_smt_state();
14adf855
CE
1512}
1513
4daa832d 1514static void remove_cpu_from_maps(int cpu)
69c18c15 1515{
c2d1cec1
MT
1516 set_cpu_online(cpu, false);
1517 cpumask_clear_cpu(cpu, cpu_callout_mask);
1518 cpumask_clear_cpu(cpu, cpu_callin_mask);
69c18c15 1519 /* was set by cpu_init() */
c2d1cec1 1520 cpumask_clear_cpu(cpu, cpu_initialized_mask);
23ca4bba 1521 numa_remove_cpu(cpu);
69c18c15
GC
1522}
1523
8227dce7 1524void cpu_disable_common(void)
69c18c15
GC
1525{
1526 int cpu = smp_processor_id();
69c18c15 1527
69c18c15
GC
1528 remove_siblinginfo(cpu);
1529
1530 /* It's now safe to remove this processor from the online map */
d388e5fd 1531 lock_vector_lock();
69c18c15 1532 remove_cpu_from_maps(cpu);
d388e5fd 1533 unlock_vector_lock();
d7b381bb 1534 fixup_irqs();
8227dce7
AN
1535}
1536
1537int native_cpu_disable(void)
1538{
da6139e4
PB
1539 int ret;
1540
1541 ret = check_irq_vectors_for_cpu_disable();
1542 if (ret)
1543 return ret;
1544
8227dce7 1545 clear_local_APIC();
8227dce7 1546 cpu_disable_common();
2ed53c0d 1547
69c18c15
GC
1548 return 0;
1549}
1550
2a442c9c 1551int common_cpu_die(unsigned int cpu)
54279552 1552{
2a442c9c 1553 int ret = 0;
54279552 1554
69c18c15 1555 /* We don't do anything here: idle task is faking death itself. */
54279552 1556
2ed53c0d 1557 /* They ack this in play_dead() by setting CPU_DEAD */
2a442c9c 1558 if (cpu_wait_death(cpu, 5)) {
2ed53c0d
LT
1559 if (system_state == SYSTEM_RUNNING)
1560 pr_info("CPU %u is now offline\n", cpu);
1561 } else {
1562 pr_err("CPU %u didn't die...\n", cpu);
2a442c9c 1563 ret = -1;
69c18c15 1564 }
2a442c9c
PM
1565
1566 return ret;
1567}
1568
1569void native_cpu_die(unsigned int cpu)
1570{
1571 common_cpu_die(cpu);
69c18c15 1572}
a21f5d88
AN
1573
1574void play_dead_common(void)
1575{
1576 idle_task_exit();
1577 reset_lazy_tlbstate();
02c68a02 1578 amd_e400_remove_cpu(raw_smp_processor_id());
a21f5d88 1579
a21f5d88 1580 /* Ack it */
2a442c9c 1581 (void)cpu_report_death();
a21f5d88
AN
1582
1583 /*
1584 * With physical CPU hotplug, we should halt the cpu
1585 */
1586 local_irq_disable();
1587}
1588
e1c467e6
FY
1589static bool wakeup_cpu0(void)
1590{
1591 if (smp_processor_id() == 0 && enable_start_cpu0)
1592 return true;
1593
1594 return false;
1595}
1596
ea530692
PA
1597/*
1598 * We need to flush the caches before going to sleep, lest we have
1599 * dirty data in our caches when we come back up.
1600 */
1601static inline void mwait_play_dead(void)
1602{
1603 unsigned int eax, ebx, ecx, edx;
1604 unsigned int highest_cstate = 0;
1605 unsigned int highest_subcstate = 0;
ce5f6824 1606 void *mwait_ptr;
576cfb40 1607 int i;
ea530692 1608
69fb3676 1609 if (!this_cpu_has(X86_FEATURE_MWAIT))
ea530692 1610 return;
840d2830 1611 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
ce5f6824 1612 return;
7b543a53 1613 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
ea530692
PA
1614 return;
1615
1616 eax = CPUID_MWAIT_LEAF;
1617 ecx = 0;
1618 native_cpuid(&eax, &ebx, &ecx, &edx);
1619
1620 /*
1621 * eax will be 0 if EDX enumeration is not valid.
1622 * Initialized below to cstate, sub_cstate value when EDX is valid.
1623 */
1624 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1625 eax = 0;
1626 } else {
1627 edx >>= MWAIT_SUBSTATE_SIZE;
1628 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1629 if (edx & MWAIT_SUBSTATE_MASK) {
1630 highest_cstate = i;
1631 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1632 }
1633 }
1634 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1635 (highest_subcstate - 1);
1636 }
1637
ce5f6824
PA
1638 /*
1639 * This should be a memory location in a cache line which is
1640 * unlikely to be touched by other processors. The actual
1641 * content is immaterial as it is not actually modified in any way.
1642 */
1643 mwait_ptr = &current_thread_info()->flags;
1644
a68e5c94
PA
1645 wbinvd();
1646
ea530692 1647 while (1) {
ce5f6824
PA
1648 /*
1649 * The CLFLUSH is a workaround for erratum AAI65 for
1650 * the Xeon 7400 series. It's not clear it is actually
1651 * needed, but it should be harmless in either case.
1652 * The WBINVD is insufficient due to the spurious-wakeup
1653 * case where we return around the loop.
1654 */
7d590cca 1655 mb();
ce5f6824 1656 clflush(mwait_ptr);
7d590cca 1657 mb();
ce5f6824 1658 __monitor(mwait_ptr, 0, 0);
ea530692
PA
1659 mb();
1660 __mwait(eax, 0);
e1c467e6
FY
1661 /*
1662 * If NMI wants to wake up CPU0, start CPU0.
1663 */
1664 if (wakeup_cpu0())
1665 start_cpu0();
ea530692
PA
1666 }
1667}
1668
406f992e 1669void hlt_play_dead(void)
ea530692 1670{
7b543a53 1671 if (__this_cpu_read(cpu_info.x86) >= 4)
a68e5c94
PA
1672 wbinvd();
1673
ea530692 1674 while (1) {
ea530692 1675 native_halt();
e1c467e6
FY
1676 /*
1677 * If NMI wants to wake up CPU0, start CPU0.
1678 */
1679 if (wakeup_cpu0())
1680 start_cpu0();
ea530692
PA
1681 }
1682}
1683
a21f5d88
AN
1684void native_play_dead(void)
1685{
1686 play_dead_common();
86886e55 1687 tboot_shutdown(TB_SHUTDOWN_WFS);
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PA
1688
1689 mwait_play_dead(); /* Only returns on failure */
1a022e3f
BO
1690 if (cpuidle_play_dead())
1691 hlt_play_dead();
a21f5d88
AN
1692}
1693
69c18c15 1694#else /* ... !CONFIG_HOTPLUG_CPU */
93be71b6 1695int native_cpu_disable(void)
69c18c15
GC
1696{
1697 return -ENOSYS;
1698}
1699
93be71b6 1700void native_cpu_die(unsigned int cpu)
69c18c15
GC
1701{
1702 /* We said "no" in __cpu_disable */
1703 BUG();
1704}
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AN
1705
1706void native_play_dead(void)
1707{
1708 BUG();
1709}
1710
68a1c3f8 1711#endif