]>
Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
07bbc16a | 55 | #include <asm/idle.h> |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
bbc2ff6a | 62 | #include <asm/vmi.h> |
7b6aa335 | 63 | #include <asm/apic.h> |
569712b2 | 64 | #include <asm/setup.h> |
bdbcdd48 | 65 | #include <asm/uv/uv.h> |
cb3c8b90 | 66 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 67 | |
1164dd00 | 68 | #include <asm/smpboot_hooks.h> |
cb3c8b90 | 69 | |
16ecf7a4 | 70 | #ifdef CONFIG_X86_32 |
4cedb334 | 71 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 72 | static int low_mappings; |
acbb6734 GOC |
73 | #endif |
74 | ||
a8db8453 GOC |
75 | /* State of each CPU */ |
76 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
77 | ||
cb3c8b90 GOC |
78 | /* Store all idle threads, this can be reused instead of creating |
79 | * a new thread. Also avoids complicated thread destroy functionality | |
80 | * for idle threads. | |
81 | */ | |
82 | #ifdef CONFIG_HOTPLUG_CPU | |
83 | /* | |
84 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
85 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
86 | */ | |
87 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
88 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
89 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
90 | #else | |
f86c9985 | 91 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
92 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
93 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
94 | #endif | |
f6bc4029 | 95 | |
a355352b GC |
96 | /* Number of siblings per CPU package */ |
97 | int smp_num_siblings = 1; | |
98 | EXPORT_SYMBOL(smp_num_siblings); | |
99 | ||
100 | /* Last level cache ID of each logical CPU */ | |
101 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
102 | ||
a355352b | 103 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 104 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
105 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
106 | ||
107 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 108 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
109 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
110 | ||
111 | /* Per CPU bogomips and other parameters */ | |
112 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
113 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 114 | |
2b6163bf | 115 | atomic_t init_deasserted; |
cb3c8b90 | 116 | |
7cc3959e | 117 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
118 | /* which node each logical CPU is on */ |
119 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
120 | EXPORT_SYMBOL(cpu_to_node_map); | |
121 | ||
122 | /* set up a mapping between cpu and node. */ | |
123 | static void map_cpu_to_node(int cpu, int node) | |
124 | { | |
125 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 126 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
127 | cpu_to_node_map[cpu] = node; |
128 | } | |
129 | ||
130 | /* undo a mapping between cpu and node. */ | |
131 | static void unmap_cpu_to_node(int cpu) | |
132 | { | |
133 | int node; | |
134 | ||
135 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
136 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 137 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
138 | cpu_to_node_map[cpu] = 0; |
139 | } | |
140 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
141 | #define map_cpu_to_node(cpu, node) ({}) | |
142 | #define unmap_cpu_to_node(cpu) ({}) | |
143 | #endif | |
144 | ||
145 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
146 | static int boot_cpu_logical_apicid; |
147 | ||
7cc3959e GOC |
148 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
149 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
150 | ||
a4928cff | 151 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
152 | { |
153 | int cpu = smp_processor_id(); | |
154 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 155 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
156 | |
157 | if (!node_online(node)) | |
158 | node = first_online_node; | |
159 | ||
160 | cpu_2_logical_apicid[cpu] = apicid; | |
161 | map_cpu_to_node(cpu, node); | |
162 | } | |
163 | ||
1481a3dd | 164 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
165 | { |
166 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
167 | unmap_cpu_to_node(cpu); | |
168 | } | |
169 | #else | |
7cc3959e GOC |
170 | #define map_cpu_to_logical_apicid() do {} while (0) |
171 | #endif | |
172 | ||
cb3c8b90 GOC |
173 | /* |
174 | * Report back to the Boot Processor. | |
175 | * Running on AP. | |
176 | */ | |
a4928cff | 177 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
178 | { |
179 | int cpuid, phys_id; | |
180 | unsigned long timeout; | |
181 | ||
182 | /* | |
183 | * If waken up by an INIT in an 82489DX configuration | |
184 | * we may get here before an INIT-deassert IPI reaches | |
185 | * our local APIC. We have to wait for the IPI or we'll | |
186 | * lock up on an APIC access. | |
187 | */ | |
a9659366 IM |
188 | if (apic->wait_for_init_deassert) |
189 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
190 | |
191 | /* | |
192 | * (This works even if the APIC is not enabled.) | |
193 | */ | |
4c9961d5 | 194 | phys_id = read_apic_id(); |
cb3c8b90 | 195 | cpuid = smp_processor_id(); |
c2d1cec1 | 196 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
197 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
198 | phys_id, cpuid); | |
199 | } | |
cfc1b9a6 | 200 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
201 | |
202 | /* | |
203 | * STARTUP IPIs are fragile beasts as they might sometimes | |
204 | * trigger some glue motherboard logic. Complete APIC bus | |
205 | * silence for 1 second, this overestimates the time the | |
206 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
207 | * by a factor of two. This should be enough. | |
208 | */ | |
209 | ||
210 | /* | |
211 | * Waiting 2s total for startup (udelay is not yet working) | |
212 | */ | |
213 | timeout = jiffies + 2*HZ; | |
214 | while (time_before(jiffies, timeout)) { | |
215 | /* | |
216 | * Has the boot CPU finished it's STARTUP sequence? | |
217 | */ | |
c2d1cec1 | 218 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
219 | break; |
220 | cpu_relax(); | |
221 | } | |
222 | ||
223 | if (!time_before(jiffies, timeout)) { | |
224 | panic("%s: CPU%d started up but did not get a callout!\n", | |
225 | __func__, cpuid); | |
226 | } | |
227 | ||
228 | /* | |
229 | * the boot CPU has finished the init stage and is spinning | |
230 | * on callin_map until we finish. We are free to set up this | |
231 | * CPU, first the APIC. (this is probably redundant on most | |
232 | * boards) | |
233 | */ | |
234 | ||
cfc1b9a6 | 235 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
236 | if (apic->smp_callin_clear_local_apic) |
237 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
238 | setup_local_APIC(); |
239 | end_local_APIC_setup(); | |
240 | map_cpu_to_logical_apicid(); | |
241 | ||
e545a614 | 242 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
243 | /* |
244 | * Get our bogomips. | |
245 | * | |
246 | * Need to enable IRQs because it can take longer and then | |
247 | * the NMI watchdog might kill us. | |
248 | */ | |
249 | local_irq_enable(); | |
250 | calibrate_delay(); | |
251 | local_irq_disable(); | |
cfc1b9a6 | 252 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
253 | |
254 | /* | |
255 | * Save our processor parameters | |
256 | */ | |
257 | smp_store_cpu_info(cpuid); | |
258 | ||
259 | /* | |
260 | * Allow the master to continue. | |
261 | */ | |
c2d1cec1 | 262 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
263 | } |
264 | ||
bbc2ff6a GOC |
265 | /* |
266 | * Activate a secondary processor. | |
267 | */ | |
0ca59dd9 | 268 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
269 | { |
270 | /* | |
271 | * Don't put *anything* before cpu_init(), SMP booting is too | |
272 | * fragile that we want to limit the things done here to the | |
273 | * most necessary things. | |
274 | */ | |
bbc2ff6a | 275 | vmi_bringup(); |
bbc2ff6a GOC |
276 | cpu_init(); |
277 | preempt_disable(); | |
278 | smp_callin(); | |
279 | ||
280 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
281 | barrier(); | |
282 | /* | |
283 | * Check TSC synchronization with the BP: | |
284 | */ | |
285 | check_tsc_sync_target(); | |
286 | ||
287 | if (nmi_watchdog == NMI_IO_APIC) { | |
288 | disable_8259A_irq(0); | |
289 | enable_NMI_through_LVT0(); | |
290 | enable_8259A_irq(0); | |
291 | } | |
292 | ||
61165d7a HD |
293 | #ifdef CONFIG_X86_32 |
294 | while (low_mappings) | |
295 | cpu_relax(); | |
296 | __flush_tlb_all(); | |
297 | #endif | |
298 | ||
bbc2ff6a GOC |
299 | /* This must be done before setting cpu_online_map */ |
300 | set_cpu_sibling_map(raw_smp_processor_id()); | |
301 | wmb(); | |
302 | ||
303 | /* | |
304 | * We need to hold call_lock, so there is no inconsistency | |
305 | * between the time smp_call_function() determines number of | |
306 | * IPI recipients, and the time when the determination is made | |
307 | * for which cpus receive the IPI. Holding this | |
308 | * lock helps us to not include this cpu in a currently in progress | |
309 | * smp_call_function(). | |
d388e5fd EB |
310 | * |
311 | * We need to hold vector_lock so there the set of online cpus | |
312 | * does not change while we are assigning vectors to cpus. Holding | |
313 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 314 | */ |
0cefa5b9 | 315 | ipi_call_lock(); |
d388e5fd EB |
316 | lock_vector_lock(); |
317 | __setup_vector_irq(smp_processor_id()); | |
c2d1cec1 | 318 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 319 | unlock_vector_lock(); |
0cefa5b9 | 320 | ipi_call_unlock(); |
bbc2ff6a GOC |
321 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
322 | ||
0cefa5b9 MS |
323 | /* enable local interrupts */ |
324 | local_irq_enable(); | |
325 | ||
bbc2ff6a GOC |
326 | setup_secondary_clock(); |
327 | ||
328 | wmb(); | |
329 | cpu_idle(); | |
330 | } | |
331 | ||
1d89a7f0 GOC |
332 | /* |
333 | * The bootstrap kernel entry code has set these up. Save them for | |
334 | * a given CPU | |
335 | */ | |
336 | ||
337 | void __cpuinit smp_store_cpu_info(int id) | |
338 | { | |
339 | struct cpuinfo_x86 *c = &cpu_data(id); | |
340 | ||
341 | *c = boot_cpu_data; | |
342 | c->cpu_index = id; | |
343 | if (id != 0) | |
344 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
345 | } |
346 | ||
347 | ||
768d9505 GC |
348 | void __cpuinit set_cpu_sibling_map(int cpu) |
349 | { | |
350 | int i; | |
351 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
352 | ||
c2d1cec1 | 353 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
354 | |
355 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
356 | for_each_cpu(i, cpu_sibling_setup_mask) { |
357 | struct cpuinfo_x86 *o = &cpu_data(i); | |
358 | ||
359 | if (c->phys_proc_id == o->phys_proc_id && | |
360 | c->cpu_core_id == o->cpu_core_id) { | |
361 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
362 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
363 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
364 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
365 | cpumask_set_cpu(i, &c->llc_shared_map); | |
366 | cpumask_set_cpu(cpu, &o->llc_shared_map); | |
768d9505 GC |
367 | } |
368 | } | |
369 | } else { | |
c2d1cec1 | 370 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
371 | } |
372 | ||
c2d1cec1 | 373 | cpumask_set_cpu(cpu, &c->llc_shared_map); |
768d9505 GC |
374 | |
375 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 376 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
377 | c->booted_cores = 1; |
378 | return; | |
379 | } | |
380 | ||
c2d1cec1 | 381 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
382 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
383 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
c2d1cec1 MT |
384 | cpumask_set_cpu(i, &c->llc_shared_map); |
385 | cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map); | |
768d9505 GC |
386 | } |
387 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
388 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
389 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
390 | /* |
391 | * Does this new cpu bringup a new core? | |
392 | */ | |
c2d1cec1 | 393 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
394 | /* |
395 | * for each core in package, increment | |
396 | * the booted_cores for this new cpu | |
397 | */ | |
c2d1cec1 | 398 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
399 | c->booted_cores++; |
400 | /* | |
401 | * increment the core count for all | |
402 | * the other cpus in this package | |
403 | */ | |
404 | if (i != cpu) | |
405 | cpu_data(i).booted_cores++; | |
406 | } else if (i != cpu && !c->booted_cores) | |
407 | c->booted_cores = cpu_data(i).booted_cores; | |
408 | } | |
409 | } | |
410 | } | |
411 | ||
70708a18 | 412 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 413 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
414 | { |
415 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
416 | /* | |
417 | * For perf, we return last level cache shared map. | |
418 | * And for power savings, we return cpu_core_map | |
419 | */ | |
420 | if (sched_mc_power_savings || sched_smt_power_savings) | |
c2d1cec1 | 421 | return cpu_core_mask(cpu); |
70708a18 | 422 | else |
030bb203 RR |
423 | return &c->llc_shared_map; |
424 | } | |
425 | ||
a4928cff | 426 | static void impress_friends(void) |
904541e2 GOC |
427 | { |
428 | int cpu; | |
429 | unsigned long bogosum = 0; | |
430 | /* | |
431 | * Allow the user to impress friends. | |
432 | */ | |
cfc1b9a6 | 433 | pr_debug("Before bogomips.\n"); |
904541e2 | 434 | for_each_possible_cpu(cpu) |
c2d1cec1 | 435 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
436 | bogosum += cpu_data(cpu).loops_per_jiffy; |
437 | printk(KERN_INFO | |
438 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 439 | num_online_cpus(), |
904541e2 GOC |
440 | bogosum/(500000/HZ), |
441 | (bogosum/(5000/HZ))%100); | |
442 | ||
cfc1b9a6 | 443 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
444 | } |
445 | ||
569712b2 | 446 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
447 | { |
448 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
449 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
450 | int timeout; | |
451 | u32 status; | |
452 | ||
823b259b | 453 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
454 | |
455 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 456 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
457 | |
458 | /* | |
459 | * Wait for idle. | |
460 | */ | |
461 | status = safe_apic_wait_icr_idle(); | |
462 | if (status) | |
463 | printk(KERN_CONT | |
464 | "a previous APIC delivery may have failed\n"); | |
465 | ||
1b374e4d | 466 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
467 | |
468 | timeout = 0; | |
469 | do { | |
470 | udelay(100); | |
471 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
472 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
473 | ||
474 | switch (status) { | |
475 | case APIC_ICR_RR_VALID: | |
476 | status = apic_read(APIC_RRR); | |
477 | printk(KERN_CONT "%08x\n", status); | |
478 | break; | |
479 | default: | |
480 | printk(KERN_CONT "failed\n"); | |
481 | } | |
482 | } | |
483 | } | |
484 | ||
cb3c8b90 GOC |
485 | /* |
486 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
487 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
488 | * won't ... remember to clear down the APIC, etc later. | |
489 | */ | |
569712b2 YL |
490 | int __devinit |
491 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) | |
cb3c8b90 GOC |
492 | { |
493 | unsigned long send_status, accept_status = 0; | |
494 | int maxlvt; | |
495 | ||
496 | /* Target chip */ | |
cb3c8b90 GOC |
497 | /* Boot on the stack */ |
498 | /* Kick the second */ | |
bdb1a9b6 | 499 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 500 | |
cfc1b9a6 | 501 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
502 | send_status = safe_apic_wait_icr_idle(); |
503 | ||
504 | /* | |
505 | * Give the other CPU some time to accept the IPI. | |
506 | */ | |
507 | udelay(200); | |
569712b2 | 508 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
509 | maxlvt = lapic_get_maxlvt(); |
510 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
511 | apic_write(APIC_ESR, 0); | |
512 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
513 | } | |
cfc1b9a6 | 514 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
515 | |
516 | if (send_status) | |
517 | printk(KERN_ERR "APIC never delivered???\n"); | |
518 | if (accept_status) | |
519 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
520 | ||
521 | return (send_status | accept_status); | |
522 | } | |
cb3c8b90 | 523 | |
54ac14a8 | 524 | int __devinit |
569712b2 | 525 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
526 | { |
527 | unsigned long send_status, accept_status = 0; | |
528 | int maxlvt, num_starts, j; | |
529 | ||
593f4a78 MR |
530 | maxlvt = lapic_get_maxlvt(); |
531 | ||
cb3c8b90 GOC |
532 | /* |
533 | * Be paranoid about clearing APIC errors. | |
534 | */ | |
535 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
536 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
537 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
538 | apic_read(APIC_ESR); |
539 | } | |
540 | ||
cfc1b9a6 | 541 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
542 | |
543 | /* | |
544 | * Turn INIT on target chip | |
545 | */ | |
cb3c8b90 GOC |
546 | /* |
547 | * Send IPI | |
548 | */ | |
1b374e4d SS |
549 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
550 | phys_apicid); | |
cb3c8b90 | 551 | |
cfc1b9a6 | 552 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
553 | send_status = safe_apic_wait_icr_idle(); |
554 | ||
555 | mdelay(10); | |
556 | ||
cfc1b9a6 | 557 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
558 | |
559 | /* Target chip */ | |
cb3c8b90 | 560 | /* Send IPI */ |
1b374e4d | 561 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 562 | |
cfc1b9a6 | 563 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
564 | send_status = safe_apic_wait_icr_idle(); |
565 | ||
566 | mb(); | |
567 | atomic_set(&init_deasserted, 1); | |
568 | ||
569 | /* | |
570 | * Should we send STARTUP IPIs ? | |
571 | * | |
572 | * Determine this based on the APIC version. | |
573 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
574 | */ | |
575 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
576 | num_starts = 2; | |
577 | else | |
578 | num_starts = 0; | |
579 | ||
580 | /* | |
581 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
582 | * target processor state. | |
583 | */ | |
584 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 585 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
586 | |
587 | /* | |
588 | * Run STARTUP IPI loop. | |
589 | */ | |
cfc1b9a6 | 590 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 591 | |
cb3c8b90 | 592 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 593 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
594 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
595 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 596 | apic_read(APIC_ESR); |
cfc1b9a6 | 597 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
598 | |
599 | /* | |
600 | * STARTUP IPI | |
601 | */ | |
602 | ||
603 | /* Target chip */ | |
cb3c8b90 GOC |
604 | /* Boot on the stack */ |
605 | /* Kick the second */ | |
1b374e4d SS |
606 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
607 | phys_apicid); | |
cb3c8b90 GOC |
608 | |
609 | /* | |
610 | * Give the other CPU some time to accept the IPI. | |
611 | */ | |
612 | udelay(300); | |
613 | ||
cfc1b9a6 | 614 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 615 | |
cfc1b9a6 | 616 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
617 | send_status = safe_apic_wait_icr_idle(); |
618 | ||
619 | /* | |
620 | * Give the other CPU some time to accept the IPI. | |
621 | */ | |
622 | udelay(200); | |
593f4a78 | 623 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 624 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
625 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
626 | if (send_status || accept_status) | |
627 | break; | |
628 | } | |
cfc1b9a6 | 629 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
630 | |
631 | if (send_status) | |
632 | printk(KERN_ERR "APIC never delivered???\n"); | |
633 | if (accept_status) | |
634 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
635 | ||
636 | return (send_status | accept_status); | |
637 | } | |
cb3c8b90 GOC |
638 | |
639 | struct create_idle { | |
640 | struct work_struct work; | |
641 | struct task_struct *idle; | |
642 | struct completion done; | |
643 | int cpu; | |
644 | }; | |
645 | ||
646 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
647 | { | |
648 | struct create_idle *c_idle = | |
649 | container_of(work, struct create_idle, work); | |
650 | ||
651 | c_idle->idle = fork_idle(c_idle->cpu); | |
652 | complete(&c_idle->done); | |
653 | } | |
654 | ||
cb3c8b90 GOC |
655 | /* |
656 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
657 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
658 | * Returns zero if CPU booted OK, else error code from |
659 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 660 | */ |
ab6fb7c0 | 661 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
662 | { |
663 | unsigned long boot_error = 0; | |
cb3c8b90 | 664 | unsigned long start_ip; |
ab6fb7c0 | 665 | int timeout; |
cb3c8b90 | 666 | struct create_idle c_idle = { |
ab6fb7c0 IM |
667 | .cpu = cpu, |
668 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 669 | }; |
ab6fb7c0 | 670 | |
cb3c8b90 | 671 | INIT_WORK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 672 | |
cb3c8b90 GOC |
673 | alternatives_smp_switch(1); |
674 | ||
675 | c_idle.idle = get_idle_for_cpu(cpu); | |
676 | ||
677 | /* | |
678 | * We can't use kernel_thread since we must avoid to | |
679 | * reschedule the child. | |
680 | */ | |
681 | if (c_idle.idle) { | |
682 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
683 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
684 | init_idle(c_idle.idle, cpu); | |
685 | goto do_rest; | |
686 | } | |
687 | ||
688 | if (!keventd_up() || current_is_keventd()) | |
689 | c_idle.work.func(&c_idle.work); | |
690 | else { | |
691 | schedule_work(&c_idle.work); | |
692 | wait_for_completion(&c_idle.done); | |
693 | } | |
694 | ||
695 | if (IS_ERR(c_idle.idle)) { | |
696 | printk("failed fork for CPU %d\n", cpu); | |
697 | return PTR_ERR(c_idle.idle); | |
698 | } | |
699 | ||
700 | set_idle_for_cpu(cpu, c_idle.idle); | |
701 | do_rest: | |
cb3c8b90 | 702 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 703 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 704 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
705 | irq_ctx_init(cpu); |
706 | #else | |
cb3c8b90 | 707 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 708 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
709 | per_cpu(kernel_stack, cpu) = |
710 | (unsigned long)task_stack_page(c_idle.idle) - | |
711 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 712 | #endif |
a939098a | 713 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 714 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 715 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
716 | |
717 | /* start_ip had better be page-aligned! */ | |
718 | start_ip = setup_trampoline(); | |
719 | ||
720 | /* So we see what's up */ | |
823b259b | 721 | printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", |
cb3c8b90 GOC |
722 | cpu, apicid, start_ip); |
723 | ||
724 | /* | |
725 | * This grunge runs the startup process for | |
726 | * the targeted processor. | |
727 | */ | |
728 | ||
729 | atomic_set(&init_deasserted, 0); | |
730 | ||
34d05591 | 731 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 732 | |
cfc1b9a6 | 733 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 734 | |
34d05591 JS |
735 | smpboot_setup_warm_reset_vector(start_ip); |
736 | /* | |
737 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
738 | */ |
739 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
740 | apic_write(APIC_ESR, 0); | |
741 | apic_read(APIC_ESR); | |
742 | } | |
34d05591 | 743 | } |
cb3c8b90 | 744 | |
cb3c8b90 | 745 | /* |
1f5bcabf IM |
746 | * Kick the secondary CPU. Use the method in the APIC driver |
747 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 748 | */ |
1f5bcabf IM |
749 | if (apic->wakeup_secondary_cpu) |
750 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
751 | else | |
752 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
753 | |
754 | if (!boot_error) { | |
755 | /* | |
756 | * allow APs to start initializing. | |
757 | */ | |
cfc1b9a6 | 758 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 759 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 760 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
761 | |
762 | /* | |
763 | * Wait 5s total for a response | |
764 | */ | |
765 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 766 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
767 | break; /* It has booted */ |
768 | udelay(100); | |
769 | } | |
770 | ||
c2d1cec1 | 771 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cb3c8b90 | 772 | /* number CPUs logically, starting from 1 (BSP is 0) */ |
cfc1b9a6 | 773 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
774 | printk(KERN_INFO "CPU%d: ", cpu); |
775 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 776 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
777 | } else { |
778 | boot_error = 1; | |
779 | if (*((volatile unsigned char *)trampoline_base) | |
780 | == 0xA5) | |
781 | /* trampoline started but...? */ | |
782 | printk(KERN_ERR "Stuck ??\n"); | |
783 | else | |
784 | /* trampoline code not run */ | |
785 | printk(KERN_ERR "Not responding.\n"); | |
25dc0049 IM |
786 | if (apic->inquire_remote_apic) |
787 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
788 | } |
789 | } | |
1a51e3a0 | 790 | |
cb3c8b90 GOC |
791 | if (boot_error) { |
792 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 793 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
794 | |
795 | /* was set by do_boot_cpu() */ | |
796 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
797 | ||
798 | /* was set by cpu_init() */ | |
799 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
800 | ||
801 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
802 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
803 | } | |
804 | ||
805 | /* mark "stuck" area as not stuck */ | |
806 | *((volatile unsigned long *)trampoline_base) = 0; | |
807 | ||
63d38198 AK |
808 | /* |
809 | * Cleanup possible dangling ends... | |
810 | */ | |
811 | smpboot_restore_warm_reset_vector(); | |
812 | ||
cb3c8b90 GOC |
813 | return boot_error; |
814 | } | |
815 | ||
816 | int __cpuinit native_cpu_up(unsigned int cpu) | |
817 | { | |
a21769a4 | 818 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
819 | unsigned long flags; |
820 | int err; | |
821 | ||
822 | WARN_ON(irqs_disabled()); | |
823 | ||
cfc1b9a6 | 824 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
825 | |
826 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
827 | !physid_isset(apicid, phys_cpu_present_map)) { | |
828 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
829 | return -EINVAL; | |
830 | } | |
831 | ||
832 | /* | |
833 | * Already booted CPU? | |
834 | */ | |
c2d1cec1 | 835 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 836 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
837 | return -ENOSYS; |
838 | } | |
839 | ||
840 | /* | |
841 | * Save current MTRR state in case it was changed since early boot | |
842 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
843 | */ | |
844 | mtrr_save_state(); | |
845 | ||
846 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
847 | ||
848 | #ifdef CONFIG_X86_32 | |
849 | /* init low mem mapping */ | |
68db065c | 850 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 851 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 852 | flush_tlb_all(); |
61165d7a | 853 | low_mappings = 1; |
cb3c8b90 GOC |
854 | |
855 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
856 | |
857 | zap_low_mappings(); | |
858 | low_mappings = 0; | |
859 | #else | |
860 | err = do_boot_cpu(apicid, cpu); | |
861 | #endif | |
862 | if (err) { | |
cfc1b9a6 | 863 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 864 | return -EIO; |
cb3c8b90 GOC |
865 | } |
866 | ||
867 | /* | |
868 | * Check TSC synchronization with the AP (keep irqs disabled | |
869 | * while doing so): | |
870 | */ | |
871 | local_irq_save(flags); | |
872 | check_tsc_sync_source(cpu); | |
873 | local_irq_restore(flags); | |
874 | ||
7c04e64a | 875 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
876 | cpu_relax(); |
877 | touch_nmi_watchdog(); | |
878 | } | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
8aef135c GOC |
883 | /* |
884 | * Fall back to non SMP mode after errors. | |
885 | * | |
886 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
887 | */ | |
888 | static __init void disable_smp(void) | |
889 | { | |
c2d1cec1 MT |
890 | /* use the read/write pointers to the present and possible maps */ |
891 | cpumask_copy(&cpu_present_map, cpumask_of(0)); | |
892 | cpumask_copy(&cpu_possible_map, cpumask_of(0)); | |
8aef135c | 893 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 894 | |
8aef135c | 895 | if (smp_found_config) |
b6df1b8b | 896 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 897 | else |
b6df1b8b | 898 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 899 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
900 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
901 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
902 | } |
903 | ||
904 | /* | |
905 | * Various sanity checks. | |
906 | */ | |
907 | static int __init smp_sanity_check(unsigned max_cpus) | |
908 | { | |
ac23d4ee | 909 | preempt_disable(); |
a58f03b0 | 910 | |
1ff2f20d | 911 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
912 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
913 | unsigned int cpu; | |
914 | unsigned nr; | |
915 | ||
916 | printk(KERN_WARNING | |
917 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 918 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
919 | |
920 | nr = 0; | |
921 | for_each_present_cpu(cpu) { | |
922 | if (nr >= 8) | |
c2d1cec1 | 923 | set_cpu_present(cpu, false); |
a58f03b0 YL |
924 | nr++; |
925 | } | |
926 | ||
927 | nr = 0; | |
928 | for_each_possible_cpu(cpu) { | |
929 | if (nr >= 8) | |
c2d1cec1 | 930 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
931 | nr++; |
932 | } | |
933 | ||
934 | nr_cpu_ids = 8; | |
935 | } | |
936 | #endif | |
937 | ||
8aef135c | 938 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
939 | printk(KERN_WARNING |
940 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
941 | hard_smp_processor_id()); | |
942 | ||
8aef135c GOC |
943 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
944 | } | |
945 | ||
946 | /* | |
947 | * If we couldn't find an SMP configuration at boot time, | |
948 | * get out of here now! | |
949 | */ | |
950 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 951 | preempt_enable(); |
8aef135c GOC |
952 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
953 | disable_smp(); | |
954 | if (APIC_init_uniprocessor()) | |
955 | printk(KERN_NOTICE "Local APIC not detected." | |
956 | " Using dummy APIC emulation.\n"); | |
957 | return -1; | |
958 | } | |
959 | ||
960 | /* | |
961 | * Should not be necessary because the MP table should list the boot | |
962 | * CPU too, but we do it for the sake of robustness anyway. | |
963 | */ | |
a27a6210 | 964 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
965 | printk(KERN_NOTICE |
966 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
967 | boot_cpu_physical_apicid); | |
968 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
969 | } | |
ac23d4ee | 970 | preempt_enable(); |
8aef135c GOC |
971 | |
972 | /* | |
973 | * If we couldn't find a local APIC, then get out of here now! | |
974 | */ | |
975 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
976 | !cpu_has_apic) { | |
977 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
978 | boot_cpu_physical_apicid); | |
979 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
980 | "(tell your hw vendor)\n"); | |
981 | smpboot_clear_io_apic(); | |
65a4e574 | 982 | arch_disable_smp_support(); |
8aef135c GOC |
983 | return -1; |
984 | } | |
985 | ||
986 | verify_local_APIC(); | |
987 | ||
988 | /* | |
989 | * If SMP should be disabled, then really disable it! | |
990 | */ | |
991 | if (!max_cpus) { | |
73d08e63 | 992 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 993 | smpboot_clear_io_apic(); |
d54db1ac MR |
994 | |
995 | localise_nmi_watchdog(); | |
996 | ||
e90955c2 | 997 | connect_bsp_APIC(); |
e90955c2 JB |
998 | setup_local_APIC(); |
999 | end_local_APIC_setup(); | |
8aef135c GOC |
1000 | return -1; |
1001 | } | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static void __init smp_cpu_index_default(void) | |
1007 | { | |
1008 | int i; | |
1009 | struct cpuinfo_x86 *c; | |
1010 | ||
7c04e64a | 1011 | for_each_possible_cpu(i) { |
8aef135c GOC |
1012 | c = &cpu_data(i); |
1013 | /* mark all to hotplug */ | |
9628937d | 1014 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1015 | } |
1016 | } | |
1017 | ||
1018 | /* | |
1019 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1020 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1021 | */ | |
1022 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1023 | { | |
7ad728f9 RR |
1024 | unsigned int i; |
1025 | ||
deef3250 | 1026 | preempt_disable(); |
8aef135c GOC |
1027 | smp_cpu_index_default(); |
1028 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1029 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1030 | mb(); |
1031 | /* | |
1032 | * Setup boot CPU information | |
1033 | */ | |
1034 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1035 | #ifdef CONFIG_X86_32 |
8aef135c | 1036 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1037 | #endif |
8aef135c | 1038 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 RR |
1039 | for_each_possible_cpu(i) { |
1040 | alloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); | |
1041 | alloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
1042 | cpumask_clear(per_cpu(cpu_core_map, i)); | |
1043 | cpumask_clear(per_cpu(cpu_sibling_map, i)); | |
1044 | } | |
8aef135c GOC |
1045 | set_cpu_sibling_map(0); |
1046 | ||
6e1cb38a | 1047 | enable_IR_x2apic(); |
06cd9a7d | 1048 | #ifdef CONFIG_X86_64 |
72ce0165 | 1049 | default_setup_apic_routing(); |
6e1cb38a SS |
1050 | #endif |
1051 | ||
8aef135c GOC |
1052 | if (smp_sanity_check(max_cpus) < 0) { |
1053 | printk(KERN_INFO "SMP disabled\n"); | |
1054 | disable_smp(); | |
deef3250 | 1055 | goto out; |
8aef135c GOC |
1056 | } |
1057 | ||
ac23d4ee | 1058 | preempt_disable(); |
4c9961d5 | 1059 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1060 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1061 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1062 | /* Or can we switch back to PIC here? */ |
1063 | } | |
ac23d4ee | 1064 | preempt_enable(); |
8aef135c | 1065 | |
8aef135c | 1066 | connect_bsp_APIC(); |
b5841765 | 1067 | |
8aef135c GOC |
1068 | /* |
1069 | * Switch from PIC to APIC mode. | |
1070 | */ | |
1071 | setup_local_APIC(); | |
1072 | ||
8aef135c GOC |
1073 | /* |
1074 | * Enable IO APIC before setting up error vector | |
1075 | */ | |
1076 | if (!skip_ioapic_setup && nr_ioapics) | |
1077 | enable_IO_APIC(); | |
88d0f550 | 1078 | |
8aef135c GOC |
1079 | end_local_APIC_setup(); |
1080 | ||
1081 | map_cpu_to_logical_apicid(); | |
1082 | ||
d83093b5 IM |
1083 | if (apic->setup_portio_remap) |
1084 | apic->setup_portio_remap(); | |
8aef135c GOC |
1085 | |
1086 | smpboot_setup_io_apic(); | |
1087 | /* | |
1088 | * Set up local APIC timer on boot CPU. | |
1089 | */ | |
1090 | ||
1091 | printk(KERN_INFO "CPU%d: ", 0); | |
1092 | print_cpu_info(&cpu_data(0)); | |
1093 | setup_boot_clock(); | |
c4bd1fda MS |
1094 | |
1095 | if (is_uv_system()) | |
1096 | uv_system_init(); | |
deef3250 IM |
1097 | out: |
1098 | preempt_enable(); | |
8aef135c | 1099 | } |
a8db8453 GOC |
1100 | /* |
1101 | * Early setup to make printk work. | |
1102 | */ | |
1103 | void __init native_smp_prepare_boot_cpu(void) | |
1104 | { | |
1105 | int me = smp_processor_id(); | |
552be871 | 1106 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1107 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1108 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1109 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1110 | } | |
1111 | ||
83f7eb9c GOC |
1112 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1113 | { | |
cfc1b9a6 | 1114 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1115 | |
1116 | impress_friends(); | |
83f7eb9c GOC |
1117 | #ifdef CONFIG_X86_IO_APIC |
1118 | setup_ioapic_dest(); | |
1119 | #endif | |
1120 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1121 | } |
1122 | ||
3b11ce7f MT |
1123 | static int __initdata setup_possible_cpus = -1; |
1124 | static int __init _setup_possible_cpus(char *str) | |
1125 | { | |
1126 | get_option(&str, &setup_possible_cpus); | |
1127 | return 0; | |
1128 | } | |
1129 | early_param("possible_cpus", _setup_possible_cpus); | |
1130 | ||
1131 | ||
68a1c3f8 GC |
1132 | /* |
1133 | * cpu_possible_map should be static, it cannot change as cpu's | |
1134 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1135 | * are allocated by some modules at init time, and dont expect to | |
1136 | * do this dynamically on cpu arrival/departure. | |
1137 | * cpu_present_map on the other hand can change dynamically. | |
1138 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1139 | * behaviour, which is cpu_possible == cpu_present. | |
1140 | * - Ashok Raj | |
1141 | * | |
1142 | * Three ways to find out the number of additional hotplug CPUs: | |
1143 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1144 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1145 | * - Otherwise don't reserve additional CPUs. |
1146 | * We do this because additional CPUs waste a lot of memory. | |
1147 | * -AK | |
1148 | */ | |
1149 | __init void prefill_possible_map(void) | |
1150 | { | |
cb48bb59 | 1151 | int i, possible; |
68a1c3f8 | 1152 | |
329513a3 YL |
1153 | /* no processor from mptable or madt */ |
1154 | if (!num_processors) | |
1155 | num_processors = 1; | |
1156 | ||
3b11ce7f MT |
1157 | if (setup_possible_cpus == -1) |
1158 | possible = num_processors + disabled_cpus; | |
1159 | else | |
1160 | possible = setup_possible_cpus; | |
1161 | ||
730cf272 MT |
1162 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1163 | ||
3b11ce7f MT |
1164 | if (possible > CONFIG_NR_CPUS) { |
1165 | printk(KERN_WARNING | |
1166 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
1167 | possible, CONFIG_NR_CPUS); | |
1168 | possible = CONFIG_NR_CPUS; | |
1169 | } | |
68a1c3f8 GC |
1170 | |
1171 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1172 | possible, max_t(int, possible - num_processors, 0)); | |
1173 | ||
1174 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1175 | set_cpu_possible(i, true); |
3461b0af MT |
1176 | |
1177 | nr_cpu_ids = possible; | |
68a1c3f8 | 1178 | } |
69c18c15 | 1179 | |
14adf855 CE |
1180 | #ifdef CONFIG_HOTPLUG_CPU |
1181 | ||
1182 | static void remove_siblinginfo(int cpu) | |
1183 | { | |
1184 | int sibling; | |
1185 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1186 | ||
c2d1cec1 MT |
1187 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1188 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1189 | /*/ |
1190 | * last thread sibling in this cpu core going down | |
1191 | */ | |
c2d1cec1 | 1192 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1193 | cpu_data(sibling).booted_cores--; |
1194 | } | |
1195 | ||
c2d1cec1 MT |
1196 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1197 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1198 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1199 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1200 | c->phys_proc_id = 0; |
1201 | c->cpu_core_id = 0; | |
c2d1cec1 | 1202 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1203 | } |
1204 | ||
69c18c15 GC |
1205 | static void __ref remove_cpu_from_maps(int cpu) |
1206 | { | |
c2d1cec1 MT |
1207 | set_cpu_online(cpu, false); |
1208 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1209 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1210 | /* was set by cpu_init() */ |
c2d1cec1 | 1211 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1212 | numa_remove_cpu(cpu); |
69c18c15 GC |
1213 | } |
1214 | ||
8227dce7 | 1215 | void cpu_disable_common(void) |
69c18c15 GC |
1216 | { |
1217 | int cpu = smp_processor_id(); | |
69c18c15 GC |
1218 | /* |
1219 | * HACK: | |
1220 | * Allow any queued timer interrupts to get serviced | |
1221 | * This is only a temporary solution until we cleanup | |
1222 | * fixup_irqs as we do for IA64. | |
1223 | */ | |
1224 | local_irq_enable(); | |
1225 | mdelay(1); | |
1226 | ||
1227 | local_irq_disable(); | |
1228 | remove_siblinginfo(cpu); | |
1229 | ||
1230 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1231 | lock_vector_lock(); |
69c18c15 | 1232 | remove_cpu_from_maps(cpu); |
d388e5fd | 1233 | unlock_vector_lock(); |
d7b381bb | 1234 | fixup_irqs(); |
8227dce7 AN |
1235 | } |
1236 | ||
1237 | int native_cpu_disable(void) | |
1238 | { | |
1239 | int cpu = smp_processor_id(); | |
1240 | ||
1241 | /* | |
1242 | * Perhaps use cpufreq to drop frequency, but that could go | |
1243 | * into generic code. | |
1244 | * | |
1245 | * We won't take down the boot processor on i386 due to some | |
1246 | * interrupts only being able to be serviced by the BSP. | |
1247 | * Especially so if we're not using an IOAPIC -zwane | |
1248 | */ | |
1249 | if (cpu == 0) | |
1250 | return -EBUSY; | |
1251 | ||
1252 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1253 | stop_apic_nmi_watchdog(NULL); | |
1254 | clear_local_APIC(); | |
1255 | ||
1256 | cpu_disable_common(); | |
69c18c15 GC |
1257 | return 0; |
1258 | } | |
1259 | ||
93be71b6 | 1260 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1261 | { |
1262 | /* We don't do anything here: idle task is faking death itself. */ | |
1263 | unsigned int i; | |
1264 | ||
1265 | for (i = 0; i < 10; i++) { | |
1266 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1267 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1268 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1269 | if (1 == num_online_cpus()) | |
1270 | alternatives_smp_switch(0); | |
1271 | return; | |
1272 | } | |
1273 | msleep(100); | |
1274 | } | |
1275 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1276 | } | |
a21f5d88 AN |
1277 | |
1278 | void play_dead_common(void) | |
1279 | { | |
1280 | idle_task_exit(); | |
1281 | reset_lazy_tlbstate(); | |
1282 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1283 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1284 | |
1285 | mb(); | |
1286 | /* Ack it */ | |
1287 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1288 | ||
1289 | /* | |
1290 | * With physical CPU hotplug, we should halt the cpu | |
1291 | */ | |
1292 | local_irq_disable(); | |
1293 | } | |
1294 | ||
1295 | void native_play_dead(void) | |
1296 | { | |
1297 | play_dead_common(); | |
1298 | wbinvd_halt(); | |
1299 | } | |
1300 | ||
69c18c15 | 1301 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1302 | int native_cpu_disable(void) |
69c18c15 GC |
1303 | { |
1304 | return -ENOSYS; | |
1305 | } | |
1306 | ||
93be71b6 | 1307 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1308 | { |
1309 | /* We said "no" in __cpu_disable */ | |
1310 | BUG(); | |
1311 | } | |
a21f5d88 AN |
1312 | |
1313 | void native_play_dead(void) | |
1314 | { | |
1315 | BUG(); | |
1316 | } | |
1317 | ||
68a1c3f8 | 1318 | #endif |