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9ff554e9 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c767a54b | 2 | /* |
4cedb334 GOC |
3 | * x86 SMP booting functions |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
7 | * Copyright 2001 Andi Kleen, SuSE Labs. |
8 | * | |
9 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
10 | * whom a great many thanks are extended. | |
11 | * | |
12 | * Thanks to Intel for making available several different Pentium, | |
13 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
14 | * Original development of Linux SMP code supported by Caldera. | |
15 | * | |
4cedb334 GOC |
16 | * Fixes |
17 | * Felix Koop : NR_CPUS used properly | |
18 | * Jose Renau : Handle single CPU case. | |
19 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
20 | * Greg Wright : Fix for kernel stacks panic. | |
21 | * Erich Boleyn : MP v1.4 and additional changes. | |
22 | * Matthias Sattler : Changes for 2.1 kernel map. | |
23 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
24 | * Michael Chastain : Change trampoline.S to gnu as. | |
25 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
26 | * Ingo Molnar : Added APIC timers, based on code | |
27 | * from Jose Renau | |
28 | * Ingo Molnar : various cleanups and rewrites | |
29 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
30 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
31 | * Andi Kleen : Changed for SMP boot into long mode. | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
35 | * Andi Kleen : Converted to new state machine. | |
36 | * Ashok Raj : CPU hotplug support | |
37 | * Glauber Costa : i386 and x86_64 integration | |
38 | */ | |
39 | ||
c767a54b JP |
40 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
186f4360 | 44 | #include <linux/export.h> |
70708a18 | 45 | #include <linux/sched.h> |
105ab3d8 | 46 | #include <linux/sched/topology.h> |
ef8bd77f | 47 | #include <linux/sched/hotplug.h> |
68db0cf1 | 48 | #include <linux/sched/task_stack.h> |
69c18c15 | 49 | #include <linux/percpu.h> |
57c8a661 | 50 | #include <linux/memblock.h> |
cb3c8b90 GOC |
51 | #include <linux/err.h> |
52 | #include <linux/nmi.h> | |
69575d38 | 53 | #include <linux/tboot.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
98fa15f3 | 56 | #include <linux/numa.h> |
65fddcfc | 57 | #include <linux/pgtable.h> |
e2b0d619 | 58 | #include <linux/overflow.h> |
69c18c15 | 59 | |
8aef135c | 60 | #include <asm/acpi.h> |
cb3c8b90 | 61 | #include <asm/desc.h> |
69c18c15 GC |
62 | #include <asm/nmi.h> |
63 | #include <asm/irq.h> | |
48927bbb | 64 | #include <asm/realmode.h> |
69c18c15 GC |
65 | #include <asm/cpu.h> |
66 | #include <asm/numa.h> | |
cb3c8b90 GOC |
67 | #include <asm/tlbflush.h> |
68 | #include <asm/mtrr.h> | |
ea530692 | 69 | #include <asm/mwait.h> |
7b6aa335 | 70 | #include <asm/apic.h> |
7167d08e | 71 | #include <asm/io_apic.h> |
78f7f1e5 | 72 | #include <asm/fpu/internal.h> |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
b81bb373 | 76 | #include <asm/i8259.h> |
646e29a1 | 77 | #include <asm/misc.h> |
9043442b | 78 | #include <asm/qspinlock.h> |
1340ccfa AS |
79 | #include <asm/intel-family.h> |
80 | #include <asm/cpu_device_id.h> | |
1f50ddb4 | 81 | #include <asm/spec-ctrl.h> |
447ae316 | 82 | #include <asm/hw_irq.h> |
c9a1ff31 | 83 | #include <asm/stackprotector.h> |
48927bbb | 84 | |
a355352b | 85 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 86 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
87 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
88 | ||
89 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 90 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
91 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
92 | ||
2e4c54da LB |
93 | /* representing HT, core, and die siblings of each logical CPU */ |
94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); | |
95 | EXPORT_PER_CPU_SYMBOL(cpu_die_map); | |
96 | ||
0816b0f0 | 97 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 98 | |
a355352b | 99 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 100 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 101 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 102 | |
1f12e32f | 103 | /* Logical package management. We might want to allocate that dynamically */ |
1f12e32f TG |
104 | unsigned int __max_logical_packages __read_mostly; |
105 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 106 | static unsigned int logical_packages __read_mostly; |
212bf4fd | 107 | static unsigned int logical_die __read_mostly; |
1f12e32f | 108 | |
70b8301f | 109 | /* Maximum number of SMT threads on any online core */ |
947134d9 | 110 | int __read_mostly __max_smt_threads = 1; |
70b8301f | 111 | |
7d25127c TC |
112 | /* Flag to indicate if a complete sched domain rebuild is required */ |
113 | bool x86_topology_update; | |
114 | ||
115 | int arch_update_cpu_topology(void) | |
116 | { | |
117 | int retval = x86_topology_update; | |
118 | ||
119 | x86_topology_update = false; | |
120 | return retval; | |
121 | } | |
122 | ||
f77aa308 TG |
123 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
124 | { | |
125 | unsigned long flags; | |
126 | ||
127 | spin_lock_irqsave(&rtc_lock, flags); | |
128 | CMOS_WRITE(0xa, 0xf); | |
129 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
130 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
131 | start_eip >> 4; | |
f77aa308 TG |
132 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
133 | start_eip & 0xf; | |
f77aa308 TG |
134 | } |
135 | ||
136 | static inline void smpboot_restore_warm_reset_vector(void) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
f77aa308 TG |
140 | /* |
141 | * Paranoid: Set warm reset code and vector here back | |
142 | * to default values. | |
143 | */ | |
144 | spin_lock_irqsave(&rtc_lock, flags); | |
145 | CMOS_WRITE(0, 0xf); | |
146 | spin_unlock_irqrestore(&rtc_lock, flags); | |
147 | ||
148 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
149 | } | |
150 | ||
b56e7d45 | 151 | static void init_freq_invariance(bool secondary); |
1567c3e3 | 152 | |
cb3c8b90 | 153 | /* |
30106c17 FY |
154 | * Report back to the Boot Processor during boot time or to the caller processor |
155 | * during CPU online. | |
cb3c8b90 | 156 | */ |
148f9bb8 | 157 | static void smp_callin(void) |
cb3c8b90 | 158 | { |
f91fecc0 | 159 | int cpuid; |
cb3c8b90 GOC |
160 | |
161 | /* | |
162 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
163 | * cpu_callout_mask guarantees we don't get here before |
164 | * an INIT_deassert IPI reaches our local APIC, so it is | |
165 | * now safe to touch our local APIC. | |
cb3c8b90 | 166 | */ |
e1c467e6 | 167 | cpuid = smp_processor_id(); |
cb3c8b90 | 168 | |
cb3c8b90 GOC |
169 | /* |
170 | * the boot CPU has finished the init stage and is spinning | |
171 | * on callin_map until we finish. We are free to set up this | |
172 | * CPU, first the APIC. (this is probably redundant on most | |
173 | * boards) | |
174 | */ | |
05f7e46d | 175 | apic_ap_setup(); |
cb3c8b90 | 176 | |
b565201c JS |
177 | /* |
178 | * Save our processor parameters. Note: this information | |
179 | * is needed for clock calibration. | |
180 | */ | |
181 | smp_store_cpu_info(cpuid); | |
182 | ||
76ce7cfe PT |
183 | /* |
184 | * The topology information must be up to date before | |
185 | * calibrate_delay() and notify_cpu_starting(). | |
186 | */ | |
187 | set_cpu_sibling_map(raw_smp_processor_id()); | |
188 | ||
b56e7d45 | 189 | init_freq_invariance(true); |
1567c3e3 | 190 | |
cb3c8b90 GOC |
191 | /* |
192 | * Get our bogomips. | |
b565201c JS |
193 | * Update loops_per_jiffy in cpu_data. Previous call to |
194 | * smp_store_cpu_info() stored a value that is close but not as | |
195 | * accurate as the value just calculated. | |
cb3c8b90 | 196 | */ |
cb3c8b90 | 197 | calibrate_delay(); |
b565201c | 198 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 199 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 200 | |
5ef428c4 AK |
201 | wmb(); |
202 | ||
85257024 PZ |
203 | notify_cpu_starting(cpuid); |
204 | ||
cb3c8b90 GOC |
205 | /* |
206 | * Allow the master to continue. | |
207 | */ | |
c2d1cec1 | 208 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
209 | } |
210 | ||
e1c467e6 FY |
211 | static int cpu0_logical_apicid; |
212 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
213 | /* |
214 | * Activate a secondary processor. | |
215 | */ | |
148f9bb8 | 216 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
217 | { |
218 | /* | |
c7ad5ad2 AL |
219 | * Don't put *anything* except direct CPU state initialization |
220 | * before cpu_init(), SMP booting is too fragile that we want to | |
221 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 222 | */ |
7652ac92 | 223 | cr4_init(); |
e1c467e6 | 224 | |
fd89a137 | 225 | #ifdef CONFIG_X86_32 |
b40827fa | 226 | /* switch away from the initial page table */ |
fd89a137 JR |
227 | load_cr3(swapper_pg_dir); |
228 | __flush_tlb_all(); | |
229 | #endif | |
520d0308 | 230 | cpu_init_exception_handling(); |
4ba55e65 AL |
231 | cpu_init(); |
232 | x86_cpuinit.early_percpu_clock_init(); | |
233 | preempt_disable(); | |
234 | smp_callin(); | |
235 | ||
236 | enable_start_cpu0 = 0; | |
237 | ||
bbc2ff6a GOC |
238 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
239 | barrier(); | |
240 | /* | |
a1652bb8 | 241 | * Check TSC synchronization with the boot CPU: |
bbc2ff6a GOC |
242 | */ |
243 | check_tsc_sync_target(); | |
244 | ||
1f50ddb4 TG |
245 | speculative_store_bypass_ht_init(); |
246 | ||
bbc2ff6a | 247 | /* |
8ed4f3e6 TG |
248 | * Lock vector_lock, set CPU online and bring the vector |
249 | * allocator online. Online must be set with vector_lock held | |
250 | * to prevent a concurrent irq setup/teardown from seeing a | |
251 | * half valid vector space. | |
bbc2ff6a | 252 | */ |
d388e5fd | 253 | lock_vector_lock(); |
c2d1cec1 | 254 | set_cpu_online(smp_processor_id(), true); |
8ed4f3e6 | 255 | lapic_online(); |
d388e5fd | 256 | unlock_vector_lock(); |
2a442c9c | 257 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 258 | x86_platform.nmi_init(); |
bbc2ff6a | 259 | |
0cefa5b9 MS |
260 | /* enable local interrupts */ |
261 | local_irq_enable(); | |
262 | ||
736decac | 263 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
264 | |
265 | wmb(); | |
fc6d73d6 | 266 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
267 | } |
268 | ||
6a4d2657 TG |
269 | /** |
270 | * topology_is_primary_thread - Check whether CPU is the primary SMT thread | |
271 | * @cpu: CPU to check | |
272 | */ | |
273 | bool topology_is_primary_thread(unsigned int cpu) | |
274 | { | |
275 | return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); | |
276 | } | |
277 | ||
f048c399 TG |
278 | /** |
279 | * topology_smt_supported - Check whether SMT is supported by the CPUs | |
280 | */ | |
281 | bool topology_smt_supported(void) | |
282 | { | |
283 | return smp_num_siblings > 1; | |
284 | } | |
285 | ||
30bb9811 AK |
286 | /** |
287 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
288 | * | |
289 | * Returns logical package id or -1 if not found | |
290 | */ | |
291 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
292 | { | |
293 | int cpu; | |
294 | ||
295 | for_each_possible_cpu(cpu) { | |
296 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
297 | ||
298 | if (c->initialized && c->phys_proc_id == phys_pkg) | |
299 | return c->logical_proc_id; | |
300 | } | |
301 | return -1; | |
302 | } | |
303 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
212bf4fd LB |
304 | /** |
305 | * topology_phys_to_logical_die - Map a physical die id to logical | |
306 | * | |
307 | * Returns logical die id or -1 if not found | |
308 | */ | |
309 | int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) | |
310 | { | |
311 | int cpu; | |
312 | int proc_id = cpu_data(cur_cpu).phys_proc_id; | |
313 | ||
314 | for_each_possible_cpu(cpu) { | |
315 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
316 | ||
317 | if (c->initialized && c->cpu_die_id == die_id && | |
318 | c->phys_proc_id == proc_id) | |
319 | return c->logical_die_id; | |
320 | } | |
321 | return -1; | |
322 | } | |
323 | EXPORT_SYMBOL(topology_phys_to_logical_die); | |
30bb9811 | 324 | |
9d85eb91 TG |
325 | /** |
326 | * topology_update_package_map - Update the physical to logical package map | |
327 | * @pkg: The physical package id as retrieved via CPUID | |
328 | * @cpu: The cpu for which this is updated | |
329 | */ | |
330 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 331 | { |
30bb9811 | 332 | int new; |
1f12e32f | 333 | |
30bb9811 AK |
334 | /* Already available somewhere? */ |
335 | new = topology_phys_to_logical_pkg(pkg); | |
336 | if (new >= 0) | |
1f12e32f TG |
337 | goto found; |
338 | ||
7b0501b1 | 339 | new = logical_packages++; |
9d85eb91 TG |
340 | if (new != pkg) { |
341 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
342 | cpu, pkg, new); | |
343 | } | |
1f12e32f | 344 | found: |
30bb9811 | 345 | cpu_data(cpu).logical_proc_id = new; |
1f12e32f TG |
346 | return 0; |
347 | } | |
212bf4fd LB |
348 | /** |
349 | * topology_update_die_map - Update the physical to logical die map | |
350 | * @die: The die id as retrieved via CPUID | |
351 | * @cpu: The cpu for which this is updated | |
352 | */ | |
353 | int topology_update_die_map(unsigned int die, unsigned int cpu) | |
354 | { | |
355 | int new; | |
356 | ||
357 | /* Already available somewhere? */ | |
358 | new = topology_phys_to_logical_die(die, cpu); | |
359 | if (new >= 0) | |
360 | goto found; | |
361 | ||
362 | new = logical_die++; | |
363 | if (new != die) { | |
364 | pr_info("CPU %u Converting physical %u to logical die %u\n", | |
365 | cpu, die, new); | |
366 | } | |
367 | found: | |
368 | cpu_data(cpu).logical_die_id = new; | |
369 | return 0; | |
370 | } | |
1f12e32f | 371 | |
30106c17 FY |
372 | void __init smp_store_boot_cpu_info(void) |
373 | { | |
374 | int id = 0; /* CPU 0 */ | |
375 | struct cpuinfo_x86 *c = &cpu_data(id); | |
376 | ||
377 | *c = boot_cpu_data; | |
378 | c->cpu_index = id; | |
b4c0a732 | 379 | topology_update_package_map(c->phys_proc_id, id); |
212bf4fd | 380 | topology_update_die_map(c->cpu_die_id, id); |
30bb9811 | 381 | c->initialized = true; |
30106c17 FY |
382 | } |
383 | ||
1d89a7f0 GOC |
384 | /* |
385 | * The bootstrap kernel entry code has set these up. Save them for | |
386 | * a given CPU | |
387 | */ | |
148f9bb8 | 388 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
389 | { |
390 | struct cpuinfo_x86 *c = &cpu_data(id); | |
391 | ||
30bb9811 AK |
392 | /* Copy boot_cpu_data only on the first bringup */ |
393 | if (!c->initialized) | |
394 | *c = boot_cpu_data; | |
1d89a7f0 | 395 | c->cpu_index = id; |
30106c17 FY |
396 | /* |
397 | * During boot time, CPU0 has this setup already. Save the info when | |
398 | * bringing up AP or offlined CPU0. | |
399 | */ | |
400 | identify_secondary_cpu(c); | |
30bb9811 | 401 | c->initialized = true; |
1d89a7f0 GOC |
402 | } |
403 | ||
cebf15eb DH |
404 | static bool |
405 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
406 | { | |
407 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
408 | ||
409 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
410 | } | |
411 | ||
148f9bb8 | 412 | static bool |
316ad248 | 413 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 414 | { |
316ad248 PZ |
415 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
416 | ||
cebf15eb | 417 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
418 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
419 | "[node: %d != %d]. Ignoring dependency.\n", | |
420 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
421 | } | |
422 | ||
7d79a7bd | 423 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 424 | do { \ |
7d79a7bd BG |
425 | cpumask_set_cpu((c1), mfunc(c2)); \ |
426 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
427 | } while (0) |
428 | ||
148f9bb8 | 429 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 430 | { |
362f924b | 431 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
432 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
433 | ||
434 | if (c->phys_proc_id == o->phys_proc_id && | |
7745f03e | 435 | c->cpu_die_id == o->cpu_die_id && |
79a8b9aa BP |
436 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
437 | if (c->cpu_core_id == o->cpu_core_id) | |
438 | return topology_sane(c, o, "smt"); | |
439 | ||
440 | if ((c->cu_id != 0xff) && | |
441 | (o->cu_id != 0xff) && | |
442 | (c->cu_id == o->cu_id)) | |
443 | return topology_sane(c, o, "smt"); | |
444 | } | |
316ad248 PZ |
445 | |
446 | } else if (c->phys_proc_id == o->phys_proc_id && | |
7745f03e | 447 | c->cpu_die_id == o->cpu_die_id && |
316ad248 PZ |
448 | c->cpu_core_id == o->cpu_core_id) { |
449 | return topology_sane(c, o, "smt"); | |
450 | } | |
451 | ||
452 | return false; | |
453 | } | |
454 | ||
1340ccfa AS |
455 | /* |
456 | * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. | |
457 | * | |
458 | * These are Intel CPUs that enumerate an LLC that is shared by | |
459 | * multiple NUMA nodes. The LLC on these systems is shared for | |
460 | * off-package data access but private to the NUMA node (half | |
461 | * of the package) for on-package access. | |
462 | * | |
463 | * CPUID (the source of the information about the LLC) can only | |
464 | * enumerate the cache as being shared *or* unshared, but not | |
465 | * this particular configuration. The CPU in this case enumerates | |
466 | * the cache to be shared across the entire package (spanning both | |
467 | * NUMA nodes). | |
468 | */ | |
469 | ||
470 | static const struct x86_cpu_id snc_cpu[] = { | |
adefe55e | 471 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), |
1340ccfa AS |
472 | {} |
473 | }; | |
474 | ||
148f9bb8 | 475 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
476 | { |
477 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
478 | ||
1340ccfa AS |
479 | /* Do not match if we do not have a valid APICID for cpu: */ |
480 | if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) | |
481 | return false; | |
316ad248 | 482 | |
1340ccfa AS |
483 | /* Do not match if LLC id does not match: */ |
484 | if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) | |
485 | return false; | |
486 | ||
487 | /* | |
488 | * Allow the SNC topology without warning. Return of false | |
489 | * means 'c' does not share the LLC of 'o'. This will be | |
490 | * reflected to userspace. | |
491 | */ | |
492 | if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) | |
493 | return false; | |
494 | ||
495 | return topology_sane(c, o, "llc"); | |
d4fbe4f0 AH |
496 | } |
497 | ||
cebf15eb DH |
498 | /* |
499 | * Unlike the other levels, we do not enforce keeping a | |
500 | * multicore group inside a NUMA node. If this happens, we will | |
501 | * discard the MC level of the topology later. | |
502 | */ | |
169d0869 | 503 | static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 504 | { |
cebf15eb DH |
505 | if (c->phys_proc_id == o->phys_proc_id) |
506 | return true; | |
316ad248 PZ |
507 | return false; |
508 | } | |
1d89a7f0 | 509 | |
2e4c54da LB |
510 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
511 | { | |
512 | if ((c->phys_proc_id == o->phys_proc_id) && | |
513 | (c->cpu_die_id == o->cpu_die_id)) | |
514 | return true; | |
515 | return false; | |
516 | } | |
517 | ||
518 | ||
d3d37d85 TC |
519 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
520 | static inline int x86_sched_itmt_flags(void) | |
521 | { | |
522 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
523 | } | |
524 | ||
525 | #ifdef CONFIG_SCHED_MC | |
526 | static int x86_core_flags(void) | |
527 | { | |
528 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
529 | } | |
530 | #endif | |
531 | #ifdef CONFIG_SCHED_SMT | |
532 | static int x86_smt_flags(void) | |
533 | { | |
534 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
535 | } | |
536 | #endif | |
537 | #endif | |
538 | ||
8f37961c | 539 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 540 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 541 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
542 | #endif |
543 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 544 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
545 | #endif |
546 | { NULL, }, | |
547 | }; | |
8f37961c TC |
548 | |
549 | static struct sched_domain_topology_level x86_topology[] = { | |
550 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 551 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
552 | #endif |
553 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 554 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
555 | #endif |
556 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
557 | { NULL, }, | |
558 | }; | |
559 | ||
cebf15eb | 560 | /* |
8f37961c | 561 | * Set if a package/die has multiple NUMA nodes inside. |
1340ccfa AS |
562 | * AMD Magny-Cours, Intel Cluster-on-Die, and Intel |
563 | * Sub-NUMA Clustering have this. | |
cebf15eb | 564 | */ |
8f37961c | 565 | static bool x86_has_numa_in_package; |
cebf15eb | 566 | |
148f9bb8 | 567 | void set_cpu_sibling_map(int cpu) |
768d9505 | 568 | { |
316ad248 | 569 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 570 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 571 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 572 | struct cpuinfo_x86 *o; |
70b8301f | 573 | int i, threads; |
768d9505 | 574 | |
c2d1cec1 | 575 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 576 | |
b0bc225d | 577 | if (!has_mp) { |
7d79a7bd | 578 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 579 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 580 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
2e4c54da | 581 | cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); |
768d9505 GC |
582 | c->booted_cores = 1; |
583 | return; | |
584 | } | |
585 | ||
c2d1cec1 | 586 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
587 | o = &cpu_data(i); |
588 | ||
589 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 590 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 591 | |
b0bc225d | 592 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 593 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 594 | |
ceb1cbac KB |
595 | } |
596 | ||
597 | /* | |
598 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 599 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
600 | */ |
601 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
602 | o = &cpu_data(i); | |
603 | ||
169d0869 | 604 | if ((i == cpu) || (has_mp && match_pkg(c, o))) { |
7d79a7bd | 605 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 606 | |
768d9505 GC |
607 | /* |
608 | * Does this new cpu bringup a new core? | |
609 | */ | |
7d79a7bd BG |
610 | if (cpumask_weight( |
611 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
612 | /* |
613 | * for each core in package, increment | |
614 | * the booted_cores for this new cpu | |
615 | */ | |
7d79a7bd BG |
616 | if (cpumask_first( |
617 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
618 | c->booted_cores++; |
619 | /* | |
620 | * increment the core count for all | |
621 | * the other cpus in this package | |
622 | */ | |
623 | if (i != cpu) | |
624 | cpu_data(i).booted_cores++; | |
625 | } else if (i != cpu && !c->booted_cores) | |
626 | c->booted_cores = cpu_data(i).booted_cores; | |
627 | } | |
169d0869 | 628 | if (match_pkg(c, o) && !topology_same_node(c, o)) |
8f37961c | 629 | x86_has_numa_in_package = true; |
2e4c54da LB |
630 | |
631 | if ((i == cpu) || (has_mp && match_die(c, o))) | |
632 | link_mask(topology_die_cpumask, cpu, i); | |
768d9505 | 633 | } |
70b8301f AK |
634 | |
635 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
636 | if (threads > __max_smt_threads) | |
637 | __max_smt_threads = threads; | |
768d9505 GC |
638 | } |
639 | ||
70708a18 | 640 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 641 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 642 | { |
9f646389 | 643 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
644 | } |
645 | ||
a4928cff | 646 | static void impress_friends(void) |
904541e2 GOC |
647 | { |
648 | int cpu; | |
649 | unsigned long bogosum = 0; | |
650 | /* | |
651 | * Allow the user to impress friends. | |
652 | */ | |
c767a54b | 653 | pr_debug("Before bogomips\n"); |
904541e2 | 654 | for_each_possible_cpu(cpu) |
c2d1cec1 | 655 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 656 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 657 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 658 | num_online_cpus(), |
904541e2 GOC |
659 | bogosum/(500000/HZ), |
660 | (bogosum/(5000/HZ))%100); | |
661 | ||
c767a54b | 662 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
663 | } |
664 | ||
569712b2 | 665 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
666 | { |
667 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 668 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
669 | int timeout; |
670 | u32 status; | |
671 | ||
c767a54b | 672 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
673 | |
674 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 675 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
676 | |
677 | /* | |
678 | * Wait for idle. | |
679 | */ | |
680 | status = safe_apic_wait_icr_idle(); | |
681 | if (status) | |
c767a54b | 682 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 683 | |
1b374e4d | 684 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
685 | |
686 | timeout = 0; | |
687 | do { | |
688 | udelay(100); | |
689 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
690 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
691 | ||
692 | switch (status) { | |
693 | case APIC_ICR_RR_VALID: | |
694 | status = apic_read(APIC_RRR); | |
c767a54b | 695 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
696 | break; |
697 | default: | |
c767a54b | 698 | pr_cont("failed\n"); |
cb3c8b90 GOC |
699 | } |
700 | } | |
701 | } | |
702 | ||
d68921f9 LB |
703 | /* |
704 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
705 | * that there should be a 10ms delay between the BSP asserting INIT | |
706 | * and de-asserting INIT, when starting a remote processor. | |
707 | * But that slows boot and resume on modern processors, which include | |
708 | * many cores and don't require that delay. | |
709 | * | |
710 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 711 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
712 | */ |
713 | #define UDELAY_10MS_DEFAULT 10000 | |
714 | ||
656279a1 | 715 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
716 | |
717 | static int __init cpu_init_udelay(char *str) | |
718 | { | |
719 | get_option(&str, &init_udelay); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | early_param("cpu_init_udelay", cpu_init_udelay); | |
724 | ||
1a744cb3 LB |
725 | static void __init smp_quirk_init_udelay(void) |
726 | { | |
727 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 728 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
729 | return; |
730 | ||
731 | /* if modern processor, use no delay */ | |
732 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
0b13bec7 | 733 | ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || |
656279a1 | 734 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 735 | init_udelay = 0; |
656279a1 LB |
736 | return; |
737 | } | |
f1ccd249 LB |
738 | /* else, use legacy delay */ |
739 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
740 | } |
741 | ||
cb3c8b90 GOC |
742 | /* |
743 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
744 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
745 | * won't ... remember to clear down the APIC, etc later. | |
746 | */ | |
148f9bb8 | 747 | int |
e1c467e6 | 748 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 | 749 | { |
e57d04e5 | 750 | u32 dm = apic->irq_dest_mode ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; |
cb3c8b90 GOC |
751 | unsigned long send_status, accept_status = 0; |
752 | int maxlvt; | |
753 | ||
754 | /* Target chip */ | |
cb3c8b90 GOC |
755 | /* Boot on the stack */ |
756 | /* Kick the second */ | |
e57d04e5 | 757 | apic_icr_write(APIC_DM_NMI | dm, apicid); |
cb3c8b90 | 758 | |
cfc1b9a6 | 759 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
760 | send_status = safe_apic_wait_icr_idle(); |
761 | ||
762 | /* | |
763 | * Give the other CPU some time to accept the IPI. | |
764 | */ | |
765 | udelay(200); | |
cff9ab2b | 766 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
767 | maxlvt = lapic_get_maxlvt(); |
768 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
769 | apic_write(APIC_ESR, 0); | |
770 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
771 | } | |
c767a54b | 772 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
773 | |
774 | if (send_status) | |
c767a54b | 775 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 776 | if (accept_status) |
c767a54b | 777 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
778 | |
779 | return (send_status | accept_status); | |
780 | } | |
cb3c8b90 | 781 | |
148f9bb8 | 782 | static int |
569712b2 | 783 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 784 | { |
f5d6a52f | 785 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
786 | int maxlvt, num_starts, j; |
787 | ||
593f4a78 MR |
788 | maxlvt = lapic_get_maxlvt(); |
789 | ||
cb3c8b90 GOC |
790 | /* |
791 | * Be paranoid about clearing APIC errors. | |
792 | */ | |
cff9ab2b | 793 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
794 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
795 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
796 | apic_read(APIC_ESR); |
797 | } | |
798 | ||
c767a54b | 799 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
800 | |
801 | /* | |
802 | * Turn INIT on target chip | |
803 | */ | |
cb3c8b90 GOC |
804 | /* |
805 | * Send IPI | |
806 | */ | |
1b374e4d SS |
807 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
808 | phys_apicid); | |
cb3c8b90 | 809 | |
cfc1b9a6 | 810 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
811 | send_status = safe_apic_wait_icr_idle(); |
812 | ||
7cb68598 | 813 | udelay(init_udelay); |
cb3c8b90 | 814 | |
c767a54b | 815 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
816 | |
817 | /* Target chip */ | |
cb3c8b90 | 818 | /* Send IPI */ |
1b374e4d | 819 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 820 | |
cfc1b9a6 | 821 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
822 | send_status = safe_apic_wait_icr_idle(); |
823 | ||
824 | mb(); | |
cb3c8b90 GOC |
825 | |
826 | /* | |
827 | * Should we send STARTUP IPIs ? | |
828 | * | |
829 | * Determine this based on the APIC version. | |
830 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
831 | */ | |
cff9ab2b | 832 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
833 | num_starts = 2; |
834 | else | |
835 | num_starts = 0; | |
836 | ||
cb3c8b90 GOC |
837 | /* |
838 | * Run STARTUP IPI loop. | |
839 | */ | |
c767a54b | 840 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 841 | |
cb3c8b90 | 842 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 843 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
844 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
845 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 846 | apic_read(APIC_ESR); |
c767a54b | 847 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
848 | |
849 | /* | |
850 | * STARTUP IPI | |
851 | */ | |
852 | ||
853 | /* Target chip */ | |
cb3c8b90 GOC |
854 | /* Boot on the stack */ |
855 | /* Kick the second */ | |
1b374e4d SS |
856 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
857 | phys_apicid); | |
cb3c8b90 GOC |
858 | |
859 | /* | |
860 | * Give the other CPU some time to accept the IPI. | |
861 | */ | |
fcafddec LB |
862 | if (init_udelay == 0) |
863 | udelay(10); | |
864 | else | |
a9bcaa02 | 865 | udelay(300); |
cb3c8b90 | 866 | |
c767a54b | 867 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 868 | |
cfc1b9a6 | 869 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
870 | send_status = safe_apic_wait_icr_idle(); |
871 | ||
872 | /* | |
873 | * Give the other CPU some time to accept the IPI. | |
874 | */ | |
fcafddec LB |
875 | if (init_udelay == 0) |
876 | udelay(10); | |
877 | else | |
a9bcaa02 | 878 | udelay(200); |
cb3c8b90 | 879 | |
593f4a78 | 880 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 881 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
882 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
883 | if (send_status || accept_status) | |
884 | break; | |
885 | } | |
c767a54b | 886 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
887 | |
888 | if (send_status) | |
c767a54b | 889 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 890 | if (accept_status) |
c767a54b | 891 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
892 | |
893 | return (send_status | accept_status); | |
894 | } | |
cb3c8b90 | 895 | |
2eaad1fd | 896 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 897 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd | 898 | { |
98fa15f3 | 899 | static int current_node = NUMA_NO_NODE; |
4adc8b71 | 900 | int node = early_cpu_to_node(cpu); |
a17bce4d | 901 | static int width, node_width; |
646e29a1 BP |
902 | |
903 | if (!width) | |
904 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 905 | |
a17bce4d BP |
906 | if (!node_width) |
907 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
908 | ||
909 | if (cpu == 1) | |
910 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
911 | ||
719b3680 | 912 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
913 | if (node != current_node) { |
914 | if (current_node > (-1)) | |
a17bce4d | 915 | pr_cont("\n"); |
2eaad1fd | 916 | current_node = node; |
a17bce4d BP |
917 | |
918 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
919 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 920 | } |
646e29a1 BP |
921 | |
922 | /* Add padding for the BSP */ | |
923 | if (cpu == 1) | |
924 | pr_cont("%*s", width + 1, " "); | |
925 | ||
926 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
927 | ||
2eaad1fd MT |
928 | } else |
929 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
930 | node, cpu, apicid); | |
931 | } | |
932 | ||
e1c467e6 FY |
933 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
934 | { | |
935 | int cpu; | |
936 | ||
937 | cpu = smp_processor_id(); | |
938 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
939 | return NMI_HANDLED; | |
940 | ||
941 | return NMI_DONE; | |
942 | } | |
943 | ||
944 | /* | |
945 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
946 | * | |
947 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
948 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
949 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
950 | * | |
951 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
952 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
953 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
954 | * real platform and request are available. | |
955 | */ | |
148f9bb8 | 956 | static int |
e1c467e6 FY |
957 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
958 | int *cpu0_nmi_registered) | |
959 | { | |
960 | int id; | |
961 | int boot_error; | |
962 | ||
ea7bdc65 JK |
963 | preempt_disable(); |
964 | ||
e1c467e6 FY |
965 | /* |
966 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
967 | */ | |
ea7bdc65 JK |
968 | if (cpu) { |
969 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
970 | goto out; | |
971 | } | |
e1c467e6 FY |
972 | |
973 | /* | |
974 | * Wake up BSP by nmi. | |
975 | * | |
976 | * Register a NMI handler to help wake up CPU0. | |
977 | */ | |
978 | boot_error = register_nmi_handler(NMI_LOCAL, | |
979 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
980 | ||
981 | if (!boot_error) { | |
982 | enable_start_cpu0 = 1; | |
983 | *cpu0_nmi_registered = 1; | |
e57d04e5 | 984 | if (apic->irq_dest_mode) |
e1c467e6 FY |
985 | id = cpu0_logical_apicid; |
986 | else | |
987 | id = apicid; | |
988 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
989 | } | |
ea7bdc65 JK |
990 | |
991 | out: | |
992 | preempt_enable(); | |
e1c467e6 FY |
993 | |
994 | return boot_error; | |
995 | } | |
996 | ||
66c7ceb4 | 997 | int common_cpu_up(unsigned int cpu, struct task_struct *idle) |
3f85483b | 998 | { |
66c7ceb4 TG |
999 | int ret; |
1000 | ||
3f85483b BO |
1001 | /* Just in case we booted with a single CPU. */ |
1002 | alternatives_enable_smp(); | |
1003 | ||
1004 | per_cpu(current_task, cpu) = idle; | |
c9a1ff31 | 1005 | cpu_init_stack_canary(cpu, idle); |
3f85483b | 1006 | |
66c7ceb4 TG |
1007 | /* Initialize the interrupt stack(s) */ |
1008 | ret = irq_init_percpu_irqstack(cpu); | |
1009 | if (ret) | |
1010 | return ret; | |
1011 | ||
3f85483b BO |
1012 | #ifdef CONFIG_X86_32 |
1013 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
cd493a6d | 1014 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 1015 | #else |
3f85483b BO |
1016 | initial_gs = per_cpu_offset(cpu); |
1017 | #endif | |
66c7ceb4 | 1018 | return 0; |
3f85483b BO |
1019 | } |
1020 | ||
cb3c8b90 GOC |
1021 | /* |
1022 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
1023 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
1024 | * Returns zero if CPU booted OK, else error code from |
1025 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 1026 | */ |
10e66760 VK |
1027 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
1028 | int *cpu0_nmi_registered) | |
cb3c8b90 | 1029 | { |
48927bbb | 1030 | /* start_ip had better be page-aligned! */ |
f37240f1 | 1031 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 1032 | |
cb3c8b90 | 1033 | unsigned long boot_error = 0; |
ce4b1b16 | 1034 | unsigned long timeout; |
cb3c8b90 | 1035 | |
b9b1a9c3 | 1036 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 1037 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 1038 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 1039 | initial_stack = idle->thread.sp; |
cb3c8b90 | 1040 | |
613e396b | 1041 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 1042 | init_espfix_ap(cpu); |
20d5e4a9 | 1043 | |
2eaad1fd MT |
1044 | /* So we see what's up */ |
1045 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
1046 | |
1047 | /* | |
1048 | * This grunge runs the startup process for | |
1049 | * the targeted processor. | |
1050 | */ | |
1051 | ||
e348caef | 1052 | if (x86_platform.legacy.warm_reset) { |
cb3c8b90 | 1053 | |
cfc1b9a6 | 1054 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 1055 | |
34d05591 JS |
1056 | smpboot_setup_warm_reset_vector(start_ip); |
1057 | /* | |
1058 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1059 | */ |
cff9ab2b | 1060 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1061 | apic_write(APIC_ESR, 0); |
1062 | apic_read(APIC_ESR); | |
1063 | } | |
34d05591 | 1064 | } |
cb3c8b90 | 1065 | |
ce4b1b16 IM |
1066 | /* |
1067 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1068 | * cpu_initialized_mask set if previous attempt to online | |
1069 | * it timed-out. Clear cpu_initialized_mask so that after | |
1070 | * INIT/SIPI it could start with a clean state. | |
1071 | */ | |
1072 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1073 | smp_mb(); | |
1074 | ||
cb3c8b90 | 1075 | /* |
e1c467e6 FY |
1076 | * Wake up a CPU in difference cases: |
1077 | * - Use the method in the APIC driver if it's defined | |
1078 | * Otherwise, | |
1079 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1080 | */ |
1f5bcabf IM |
1081 | if (apic->wakeup_secondary_cpu) |
1082 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1083 | else | |
e1c467e6 | 1084 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 1085 | cpu0_nmi_registered); |
cb3c8b90 GOC |
1086 | |
1087 | if (!boot_error) { | |
1088 | /* | |
6e38f1e7 | 1089 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1090 | */ |
ce4b1b16 IM |
1091 | boot_error = -1; |
1092 | timeout = jiffies + 10*HZ; | |
1093 | while (time_before(jiffies, timeout)) { | |
1094 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1095 | /* | |
1096 | * Tell AP to proceed with initialization | |
1097 | */ | |
1098 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1099 | boot_error = 0; | |
1100 | break; | |
1101 | } | |
ce4b1b16 IM |
1102 | schedule(); |
1103 | } | |
1104 | } | |
cb3c8b90 | 1105 | |
ce4b1b16 | 1106 | if (!boot_error) { |
cb3c8b90 | 1107 | /* |
ce4b1b16 | 1108 | * Wait till AP completes initial initialization |
cb3c8b90 | 1109 | */ |
ce4b1b16 | 1110 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1111 | /* |
1112 | * Allow other tasks to run while we wait for the | |
1113 | * AP to come online. This also gives a chance | |
1114 | * for the MTRR work(triggered by the AP coming online) | |
1115 | * to be completed in the stop machine context. | |
1116 | */ | |
1117 | schedule(); | |
cb3c8b90 | 1118 | } |
cb3c8b90 GOC |
1119 | } |
1120 | ||
e348caef | 1121 | if (x86_platform.legacy.warm_reset) { |
02421f98 YL |
1122 | /* |
1123 | * Cleanup possible dangling ends... | |
1124 | */ | |
1125 | smpboot_restore_warm_reset_vector(); | |
1126 | } | |
e1c467e6 | 1127 | |
cb3c8b90 GOC |
1128 | return boot_error; |
1129 | } | |
1130 | ||
148f9bb8 | 1131 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1132 | { |
a21769a4 | 1133 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1134 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1135 | unsigned long flags; |
10e66760 | 1136 | int err, ret = 0; |
cb3c8b90 | 1137 | |
7a10e2a9 | 1138 | lockdep_assert_irqs_enabled(); |
cb3c8b90 | 1139 | |
cfc1b9a6 | 1140 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1141 | |
30106c17 | 1142 | if (apicid == BAD_APICID || |
c284b42a | 1143 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1144 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1145 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1146 | return -EINVAL; |
1147 | } | |
1148 | ||
1149 | /* | |
1150 | * Already booted CPU? | |
1151 | */ | |
c2d1cec1 | 1152 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1153 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1154 | return -ENOSYS; |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * Save current MTRR state in case it was changed since early boot | |
1159 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1160 | */ | |
1161 | mtrr_save_state(); | |
1162 | ||
2a442c9c PM |
1163 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1164 | err = cpu_check_up_prepare(cpu); | |
1165 | if (err && err != -EBUSY) | |
1166 | return err; | |
cb3c8b90 | 1167 | |
644c1541 | 1168 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1169 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1170 | |
66c7ceb4 TG |
1171 | err = common_cpu_up(cpu, tidle); |
1172 | if (err) | |
1173 | return err; | |
3f85483b | 1174 | |
10e66760 | 1175 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1176 | if (err) { |
feef1e8e | 1177 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1178 | ret = -EIO; |
1179 | goto unreg_nmi; | |
cb3c8b90 GOC |
1180 | } |
1181 | ||
1182 | /* | |
1183 | * Check TSC synchronization with the AP (keep irqs disabled | |
1184 | * while doing so): | |
1185 | */ | |
1186 | local_irq_save(flags); | |
1187 | check_tsc_sync_source(cpu); | |
1188 | local_irq_restore(flags); | |
1189 | ||
7c04e64a | 1190 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1191 | cpu_relax(); |
1192 | touch_nmi_watchdog(); | |
1193 | } | |
1194 | ||
10e66760 VK |
1195 | unreg_nmi: |
1196 | /* | |
1197 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1198 | * to avoid impact of possible long unregister time. | |
1199 | */ | |
1200 | if (cpu0_nmi_registered) | |
1201 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1202 | ||
1203 | return ret; | |
cb3c8b90 GOC |
1204 | } |
1205 | ||
7167d08e HK |
1206 | /** |
1207 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1208 | */ | |
1209 | void arch_disable_smp_support(void) | |
1210 | { | |
1211 | disable_ioapic_support(); | |
1212 | } | |
1213 | ||
8aef135c GOC |
1214 | /* |
1215 | * Fall back to non SMP mode after errors. | |
1216 | * | |
1217 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1218 | */ | |
1219 | static __init void disable_smp(void) | |
1220 | { | |
613c25ef TG |
1221 | pr_info("SMP disabled\n"); |
1222 | ||
ef4c59a4 TG |
1223 | disable_ioapic_support(); |
1224 | ||
4f062896 RR |
1225 | init_cpu_present(cpumask_of(0)); |
1226 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1227 | |
8aef135c | 1228 | if (smp_found_config) |
b6df1b8b | 1229 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1230 | else |
b6df1b8b | 1231 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1232 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1233 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
2e4c54da | 1234 | cpumask_set_cpu(0, topology_die_cpumask(0)); |
8aef135c GOC |
1235 | } |
1236 | ||
1237 | /* | |
1238 | * Various sanity checks. | |
1239 | */ | |
4f45ed9f | 1240 | static void __init smp_sanity_check(void) |
8aef135c | 1241 | { |
ac23d4ee | 1242 | preempt_disable(); |
a58f03b0 | 1243 | |
1ff2f20d | 1244 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1245 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1246 | unsigned int cpu; | |
1247 | unsigned nr; | |
1248 | ||
c767a54b JP |
1249 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1250 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1251 | |
1252 | nr = 0; | |
1253 | for_each_present_cpu(cpu) { | |
1254 | if (nr >= 8) | |
c2d1cec1 | 1255 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1256 | nr++; |
1257 | } | |
1258 | ||
1259 | nr = 0; | |
1260 | for_each_possible_cpu(cpu) { | |
1261 | if (nr >= 8) | |
c2d1cec1 | 1262 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1263 | nr++; |
1264 | } | |
1265 | ||
1266 | nr_cpu_ids = 8; | |
1267 | } | |
1268 | #endif | |
1269 | ||
8aef135c | 1270 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1271 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1272 | hard_smp_processor_id()); |
1273 | ||
8aef135c GOC |
1274 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1275 | } | |
1276 | ||
8aef135c GOC |
1277 | /* |
1278 | * Should not be necessary because the MP table should list the boot | |
1279 | * CPU too, but we do it for the sake of robustness anyway. | |
1280 | */ | |
a27a6210 | 1281 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1282 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1283 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1284 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1285 | } | |
ac23d4ee | 1286 | preempt_enable(); |
8aef135c GOC |
1287 | } |
1288 | ||
1289 | static void __init smp_cpu_index_default(void) | |
1290 | { | |
1291 | int i; | |
1292 | struct cpuinfo_x86 *c; | |
1293 | ||
7c04e64a | 1294 | for_each_possible_cpu(i) { |
8aef135c GOC |
1295 | c = &cpu_data(i); |
1296 | /* mark all to hotplug */ | |
9628937d | 1297 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1298 | } |
1299 | } | |
1300 | ||
4b1244b4 DL |
1301 | static void __init smp_get_logical_apicid(void) |
1302 | { | |
1303 | if (x2apic_mode) | |
1304 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1305 | else | |
1306 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1307 | } | |
1308 | ||
8aef135c | 1309 | /* |
935356ce DL |
1310 | * Prepare for SMP bootup. |
1311 | * @max_cpus: configured maximum number of CPUs, It is a legacy parameter | |
1312 | * for common interface support. | |
8aef135c GOC |
1313 | */ |
1314 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1315 | { | |
7ad728f9 RR |
1316 | unsigned int i; |
1317 | ||
8aef135c | 1318 | smp_cpu_index_default(); |
792363d2 | 1319 | |
8aef135c GOC |
1320 | /* |
1321 | * Setup boot CPU information | |
1322 | */ | |
30106c17 | 1323 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1324 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1325 | mb(); | |
bd22a2f1 | 1326 | |
7ad728f9 | 1327 | for_each_possible_cpu(i) { |
79f55997 LZ |
1328 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1329 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
2e4c54da | 1330 | zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); |
b3d7336d | 1331 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1332 | } |
8f37961c TC |
1333 | |
1334 | /* | |
1335 | * Set 'default' x86 topology, this matches default_topology() in that | |
1336 | * it has NUMA nodes as a topology level. See also | |
1337 | * native_smp_cpus_done(). | |
1338 | * | |
1339 | * Must be done before set_cpus_sibling_map() is ran. | |
1340 | */ | |
1341 | set_sched_topology(x86_topology); | |
1342 | ||
8aef135c | 1343 | set_cpu_sibling_map(0); |
b56e7d45 | 1344 | init_freq_invariance(false); |
4f45ed9f DL |
1345 | smp_sanity_check(); |
1346 | ||
1347 | switch (apic_intr_mode) { | |
1348 | case APIC_PIC: | |
1349 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
613c25ef TG |
1350 | disable_smp(); |
1351 | return; | |
4f45ed9f | 1352 | case APIC_SYMMETRIC_IO_NO_ROUTING: |
613c25ef | 1353 | disable_smp(); |
a2510d15 DL |
1354 | /* Setup local timer */ |
1355 | x86_init.timers.setup_percpu_clockev(); | |
250a1ac6 | 1356 | return; |
4f45ed9f DL |
1357 | case APIC_VIRTUAL_WIRE: |
1358 | case APIC_SYMMETRIC_IO: | |
613c25ef | 1359 | break; |
8aef135c GOC |
1360 | } |
1361 | ||
a2510d15 DL |
1362 | /* Setup local timer */ |
1363 | x86_init.timers.setup_percpu_clockev(); | |
8aef135c | 1364 | |
4b1244b4 | 1365 | smp_get_logical_apicid(); |
ef4c59a4 | 1366 | |
d54ff31d | 1367 | pr_info("CPU0: "); |
8aef135c | 1368 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1369 | |
9ec808a0 | 1370 | uv_system_init(); |
d0af9eed SS |
1371 | |
1372 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1373 | |
1374 | smp_quirk_init_udelay(); | |
1f50ddb4 TG |
1375 | |
1376 | speculative_store_bypass_ht_init(); | |
8aef135c | 1377 | } |
d0af9eed | 1378 | |
56555855 | 1379 | void arch_thaw_secondary_cpus_begin(void) |
d0af9eed SS |
1380 | { |
1381 | set_mtrr_aps_delayed_init(); | |
1382 | } | |
1383 | ||
56555855 | 1384 | void arch_thaw_secondary_cpus_end(void) |
d0af9eed SS |
1385 | { |
1386 | mtrr_aps_init(); | |
1387 | } | |
1388 | ||
a8db8453 GOC |
1389 | /* |
1390 | * Early setup to make printk work. | |
1391 | */ | |
1392 | void __init native_smp_prepare_boot_cpu(void) | |
1393 | { | |
1394 | int me = smp_processor_id(); | |
552be871 | 1395 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1396 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1397 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1398 | cpu_set_state_online(me); |
090d54bc | 1399 | native_pv_lock_init(); |
a8db8453 GOC |
1400 | } |
1401 | ||
63e708f8 | 1402 | void __init calculate_max_logical_packages(void) |
83f7eb9c | 1403 | { |
b4c0a732 PB |
1404 | int ncpus; |
1405 | ||
b4c0a732 PB |
1406 | /* |
1407 | * Today neither Intel nor AMD support heterogenous systems so | |
1408 | * extrapolate the boot cpu's data to all packages. | |
1409 | */ | |
947134d9 | 1410 | ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); |
aa02ef09 | 1411 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
b4c0a732 | 1412 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
63e708f8 PB |
1413 | } |
1414 | ||
1415 | void __init native_smp_cpus_done(unsigned int max_cpus) | |
1416 | { | |
1417 | pr_debug("Boot done\n"); | |
1418 | ||
1419 | calculate_max_logical_packages(); | |
83f7eb9c | 1420 | |
8f37961c TC |
1421 | if (x86_has_numa_in_package) |
1422 | set_sched_topology(x86_numa_in_package_topology); | |
1423 | ||
99e8b9ca | 1424 | nmi_selftest(); |
83f7eb9c | 1425 | impress_friends(); |
d0af9eed | 1426 | mtrr_aps_init(); |
83f7eb9c GOC |
1427 | } |
1428 | ||
3b11ce7f MT |
1429 | static int __initdata setup_possible_cpus = -1; |
1430 | static int __init _setup_possible_cpus(char *str) | |
1431 | { | |
1432 | get_option(&str, &setup_possible_cpus); | |
1433 | return 0; | |
1434 | } | |
1435 | early_param("possible_cpus", _setup_possible_cpus); | |
1436 | ||
1437 | ||
68a1c3f8 | 1438 | /* |
4f062896 | 1439 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 | 1440 | * are onlined, or offlined. The reason is per-cpu data-structures |
4d1d0977 | 1441 | * are allocated by some modules at init time, and don't expect to |
68a1c3f8 | 1442 | * do this dynamically on cpu arrival/departure. |
4f062896 | 1443 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1444 | * In case when cpu_hotplug is not compiled, then we resort to current |
1445 | * behaviour, which is cpu_possible == cpu_present. | |
1446 | * - Ashok Raj | |
1447 | * | |
1448 | * Three ways to find out the number of additional hotplug CPUs: | |
1449 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1450 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1451 | * - Otherwise don't reserve additional CPUs. |
1452 | * We do this because additional CPUs waste a lot of memory. | |
1453 | * -AK | |
1454 | */ | |
1455 | __init void prefill_possible_map(void) | |
1456 | { | |
cb48bb59 | 1457 | int i, possible; |
68a1c3f8 | 1458 | |
2a51fe08 PB |
1459 | /* No boot processor was found in mptable or ACPI MADT */ |
1460 | if (!num_processors) { | |
ff856051 VS |
1461 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1462 | int apicid = boot_cpu_physical_apicid; | |
1463 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1464 | |
ff856051 | 1465 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1466 | |
ff856051 VS |
1467 | /* Make sure boot cpu is enumerated */ |
1468 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1469 | apic->apic_id_valid(apicid)) | |
1470 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1471 | } | |
2a51fe08 PB |
1472 | |
1473 | if (!num_processors) | |
1474 | num_processors = 1; | |
1475 | } | |
329513a3 | 1476 | |
5f2eb550 JB |
1477 | i = setup_max_cpus ?: 1; |
1478 | if (setup_possible_cpus == -1) { | |
1479 | possible = num_processors; | |
1480 | #ifdef CONFIG_HOTPLUG_CPU | |
1481 | if (setup_max_cpus) | |
1482 | possible += disabled_cpus; | |
1483 | #else | |
1484 | if (possible > i) | |
1485 | possible = i; | |
1486 | #endif | |
1487 | } else | |
3b11ce7f MT |
1488 | possible = setup_possible_cpus; |
1489 | ||
730cf272 MT |
1490 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1491 | ||
2b633e3f YL |
1492 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1493 | if (possible > nr_cpu_ids) { | |
9b130ad5 | 1494 | pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", |
2b633e3f YL |
1495 | possible, nr_cpu_ids); |
1496 | possible = nr_cpu_ids; | |
3b11ce7f | 1497 | } |
68a1c3f8 | 1498 | |
5f2eb550 JB |
1499 | #ifdef CONFIG_HOTPLUG_CPU |
1500 | if (!setup_max_cpus) | |
1501 | #endif | |
1502 | if (possible > i) { | |
c767a54b | 1503 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1504 | possible, setup_max_cpus); |
1505 | possible = i; | |
1506 | } | |
1507 | ||
427d77a3 TG |
1508 | nr_cpu_ids = possible; |
1509 | ||
c767a54b | 1510 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1511 | possible, max_t(int, possible - num_processors, 0)); |
1512 | ||
427d77a3 TG |
1513 | reset_cpu_possible_mask(); |
1514 | ||
68a1c3f8 | 1515 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1516 | set_cpu_possible(i, true); |
68a1c3f8 | 1517 | } |
69c18c15 | 1518 | |
14adf855 CE |
1519 | #ifdef CONFIG_HOTPLUG_CPU |
1520 | ||
70b8301f AK |
1521 | /* Recompute SMT state for all CPUs on offline */ |
1522 | static void recompute_smt_state(void) | |
1523 | { | |
1524 | int max_threads, cpu; | |
1525 | ||
1526 | max_threads = 0; | |
1527 | for_each_online_cpu (cpu) { | |
1528 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1529 | ||
1530 | if (threads > max_threads) | |
1531 | max_threads = threads; | |
1532 | } | |
1533 | __max_smt_threads = max_threads; | |
1534 | } | |
1535 | ||
14adf855 CE |
1536 | static void remove_siblinginfo(int cpu) |
1537 | { | |
1538 | int sibling; | |
1539 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1540 | ||
7d79a7bd BG |
1541 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1542 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1543 | /*/ |
1544 | * last thread sibling in this cpu core going down | |
1545 | */ | |
7d79a7bd | 1546 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1547 | cpu_data(sibling).booted_cores--; |
1548 | } | |
1549 | ||
2e4c54da LB |
1550 | for_each_cpu(sibling, topology_die_cpumask(cpu)) |
1551 | cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); | |
7d79a7bd BG |
1552 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1553 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1554 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1555 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1556 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1557 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1558 | cpumask_clear(topology_core_cpumask(cpu)); | |
2e4c54da | 1559 | cpumask_clear(topology_die_cpumask(cpu)); |
14adf855 | 1560 | c->cpu_core_id = 0; |
45967493 | 1561 | c->booted_cores = 0; |
c2d1cec1 | 1562 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1563 | recompute_smt_state(); |
14adf855 CE |
1564 | } |
1565 | ||
4daa832d | 1566 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1567 | { |
c2d1cec1 MT |
1568 | set_cpu_online(cpu, false); |
1569 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1570 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1571 | /* was set by cpu_init() */ |
c2d1cec1 | 1572 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1573 | numa_remove_cpu(cpu); |
69c18c15 GC |
1574 | } |
1575 | ||
8227dce7 | 1576 | void cpu_disable_common(void) |
69c18c15 GC |
1577 | { |
1578 | int cpu = smp_processor_id(); | |
69c18c15 | 1579 | |
69c18c15 GC |
1580 | remove_siblinginfo(cpu); |
1581 | ||
1582 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1583 | lock_vector_lock(); |
69c18c15 | 1584 | remove_cpu_from_maps(cpu); |
d388e5fd | 1585 | unlock_vector_lock(); |
d7b381bb | 1586 | fixup_irqs(); |
0fa115da | 1587 | lapic_offline(); |
8227dce7 AN |
1588 | } |
1589 | ||
1590 | int native_cpu_disable(void) | |
1591 | { | |
da6139e4 PB |
1592 | int ret; |
1593 | ||
2cffad7b | 1594 | ret = lapic_can_unplug_cpu(); |
da6139e4 PB |
1595 | if (ret) |
1596 | return ret; | |
1597 | ||
8227dce7 | 1598 | cpu_disable_common(); |
2ed53c0d | 1599 | |
52d6b926 AR |
1600 | /* |
1601 | * Disable the local APIC. Otherwise IPI broadcasts will reach | |
1602 | * it. It still responds normally to INIT, NMI, SMI, and SIPI | |
1603 | * messages. | |
1604 | * | |
1605 | * Disabling the APIC must happen after cpu_disable_common() | |
1606 | * which invokes fixup_irqs(). | |
1607 | * | |
1608 | * Disabling the APIC preserves already set bits in IRR, but | |
1609 | * an interrupt arriving after disabling the local APIC does not | |
1610 | * set the corresponding IRR bit. | |
1611 | * | |
1612 | * fixup_irqs() scans IRR for set bits so it can raise a not | |
1613 | * yet handled interrupt on the new destination CPU via an IPI | |
1614 | * but obviously it can't do so for IRR bits which are not set. | |
1615 | * IOW, interrupts arriving after disabling the local APIC will | |
1616 | * be lost. | |
1617 | */ | |
1618 | apic_soft_disable(); | |
1619 | ||
69c18c15 GC |
1620 | return 0; |
1621 | } | |
1622 | ||
2a442c9c | 1623 | int common_cpu_die(unsigned int cpu) |
54279552 | 1624 | { |
2a442c9c | 1625 | int ret = 0; |
54279552 | 1626 | |
69c18c15 | 1627 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1628 | |
2ed53c0d | 1629 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1630 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1631 | if (system_state == SYSTEM_RUNNING) |
1632 | pr_info("CPU %u is now offline\n", cpu); | |
1633 | } else { | |
1634 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1635 | ret = -1; |
69c18c15 | 1636 | } |
2a442c9c PM |
1637 | |
1638 | return ret; | |
1639 | } | |
1640 | ||
1641 | void native_cpu_die(unsigned int cpu) | |
1642 | { | |
1643 | common_cpu_die(cpu); | |
69c18c15 | 1644 | } |
a21f5d88 AN |
1645 | |
1646 | void play_dead_common(void) | |
1647 | { | |
1648 | idle_task_exit(); | |
a21f5d88 | 1649 | |
a21f5d88 | 1650 | /* Ack it */ |
2a442c9c | 1651 | (void)cpu_report_death(); |
a21f5d88 AN |
1652 | |
1653 | /* | |
1654 | * With physical CPU hotplug, we should halt the cpu | |
1655 | */ | |
1656 | local_irq_disable(); | |
1657 | } | |
1658 | ||
e1c467e6 FY |
1659 | static bool wakeup_cpu0(void) |
1660 | { | |
1661 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1662 | return true; | |
1663 | ||
1664 | return false; | |
1665 | } | |
1666 | ||
ea530692 PA |
1667 | /* |
1668 | * We need to flush the caches before going to sleep, lest we have | |
1669 | * dirty data in our caches when we come back up. | |
1670 | */ | |
1671 | static inline void mwait_play_dead(void) | |
1672 | { | |
1673 | unsigned int eax, ebx, ecx, edx; | |
1674 | unsigned int highest_cstate = 0; | |
1675 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1676 | void *mwait_ptr; |
576cfb40 | 1677 | int i; |
ea530692 | 1678 | |
0b13bec7 PW |
1679 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
1680 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) | |
da6fa7ef | 1681 | return; |
69fb3676 | 1682 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1683 | return; |
840d2830 | 1684 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1685 | return; |
7b543a53 | 1686 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1687 | return; |
1688 | ||
1689 | eax = CPUID_MWAIT_LEAF; | |
1690 | ecx = 0; | |
1691 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1692 | ||
1693 | /* | |
1694 | * eax will be 0 if EDX enumeration is not valid. | |
1695 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1696 | */ | |
1697 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1698 | eax = 0; | |
1699 | } else { | |
1700 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1701 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1702 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1703 | highest_cstate = i; | |
1704 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1705 | } | |
1706 | } | |
1707 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1708 | (highest_subcstate - 1); | |
1709 | } | |
1710 | ||
ce5f6824 PA |
1711 | /* |
1712 | * This should be a memory location in a cache line which is | |
1713 | * unlikely to be touched by other processors. The actual | |
1714 | * content is immaterial as it is not actually modified in any way. | |
1715 | */ | |
1716 | mwait_ptr = ¤t_thread_info()->flags; | |
1717 | ||
a68e5c94 PA |
1718 | wbinvd(); |
1719 | ||
ea530692 | 1720 | while (1) { |
ce5f6824 PA |
1721 | /* |
1722 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1723 | * the Xeon 7400 series. It's not clear it is actually | |
1724 | * needed, but it should be harmless in either case. | |
1725 | * The WBINVD is insufficient due to the spurious-wakeup | |
1726 | * case where we return around the loop. | |
1727 | */ | |
7d590cca | 1728 | mb(); |
ce5f6824 | 1729 | clflush(mwait_ptr); |
7d590cca | 1730 | mb(); |
ce5f6824 | 1731 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1732 | mb(); |
1733 | __mwait(eax, 0); | |
e1c467e6 FY |
1734 | /* |
1735 | * If NMI wants to wake up CPU0, start CPU0. | |
1736 | */ | |
1737 | if (wakeup_cpu0()) | |
1738 | start_cpu0(); | |
ea530692 PA |
1739 | } |
1740 | } | |
1741 | ||
406f992e | 1742 | void hlt_play_dead(void) |
ea530692 | 1743 | { |
7b543a53 | 1744 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1745 | wbinvd(); |
1746 | ||
ea530692 | 1747 | while (1) { |
ea530692 | 1748 | native_halt(); |
e1c467e6 FY |
1749 | /* |
1750 | * If NMI wants to wake up CPU0, start CPU0. | |
1751 | */ | |
1752 | if (wakeup_cpu0()) | |
1753 | start_cpu0(); | |
ea530692 PA |
1754 | } |
1755 | } | |
1756 | ||
a21f5d88 AN |
1757 | void native_play_dead(void) |
1758 | { | |
1759 | play_dead_common(); | |
86886e55 | 1760 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1761 | |
1762 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1763 | if (cpuidle_play_dead()) |
1764 | hlt_play_dead(); | |
a21f5d88 AN |
1765 | } |
1766 | ||
69c18c15 | 1767 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1768 | int native_cpu_disable(void) |
69c18c15 GC |
1769 | { |
1770 | return -ENOSYS; | |
1771 | } | |
1772 | ||
93be71b6 | 1773 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1774 | { |
1775 | /* We said "no" in __cpu_disable */ | |
1776 | BUG(); | |
1777 | } | |
a21f5d88 AN |
1778 | |
1779 | void native_play_dead(void) | |
1780 | { | |
1781 | BUG(); | |
1782 | } | |
1783 | ||
68a1c3f8 | 1784 | #endif |
1567c3e3 | 1785 | |
e2b0d619 | 1786 | #ifdef CONFIG_X86_64 |
1567c3e3 GG |
1787 | /* |
1788 | * APERF/MPERF frequency ratio computation. | |
1789 | * | |
1790 | * The scheduler wants to do frequency invariant accounting and needs a <1 | |
1791 | * ratio to account for the 'current' frequency, corresponding to | |
1792 | * freq_curr / freq_max. | |
1793 | * | |
1794 | * Since the frequency freq_curr on x86 is controlled by micro-controller and | |
1795 | * our P-state setting is little more than a request/hint, we need to observe | |
1796 | * the effective frequency 'BusyMHz', i.e. the average frequency over a time | |
1797 | * interval after discarding idle time. This is given by: | |
1798 | * | |
1799 | * BusyMHz = delta_APERF / delta_MPERF * freq_base | |
1800 | * | |
1801 | * where freq_base is the max non-turbo P-state. | |
1802 | * | |
1803 | * The freq_max term has to be set to a somewhat arbitrary value, because we | |
1804 | * can't know which turbo states will be available at a given point in time: | |
1805 | * it all depends on the thermal headroom of the entire package. We set it to | |
1806 | * the turbo level with 4 cores active. | |
1807 | * | |
1808 | * Benchmarks show that's a good compromise between the 1C turbo ratio | |
1809 | * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, | |
1810 | * which would ignore the entire turbo range (a conspicuous part, making | |
1811 | * freq_curr/freq_max always maxed out). | |
1812 | * | |
eacf0474 GG |
1813 | * An exception to the heuristic above is the Atom uarch, where we choose the |
1814 | * highest turbo level for freq_max since Atom's are generally oriented towards | |
1815 | * power efficiency. | |
1816 | * | |
1567c3e3 GG |
1817 | * Setting freq_max to anything less than the 1C turbo ratio makes the ratio |
1818 | * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. | |
1819 | */ | |
1820 | ||
1821 | DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); | |
1822 | ||
1823 | static DEFINE_PER_CPU(u64, arch_prev_aperf); | |
1824 | static DEFINE_PER_CPU(u64, arch_prev_mperf); | |
918229cd | 1825 | static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; |
1567c3e3 GG |
1826 | static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; |
1827 | ||
918229cd GG |
1828 | void arch_set_max_freq_ratio(bool turbo_disabled) |
1829 | { | |
1830 | arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : | |
1831 | arch_turbo_freq_ratio; | |
1832 | } | |
1833 | ||
1567c3e3 GG |
1834 | static bool turbo_disabled(void) |
1835 | { | |
1836 | u64 misc_en; | |
1837 | int err; | |
1838 | ||
1839 | err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); | |
1840 | if (err) | |
1841 | return false; | |
1842 | ||
1843 | return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
1844 | } | |
1845 | ||
298c6f99 GG |
1846 | static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) |
1847 | { | |
1848 | int err; | |
1849 | ||
1850 | err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); | |
1851 | if (err) | |
1852 | return false; | |
1853 | ||
1854 | err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); | |
1855 | if (err) | |
1856 | return false; | |
1857 | ||
1858 | *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ | |
1859 | *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ | |
1860 | ||
1861 | return true; | |
1862 | } | |
1863 | ||
1567c3e3 GG |
1864 | #include <asm/cpu_device_id.h> |
1865 | #include <asm/intel-family.h> | |
1866 | ||
2fa9a3cf BP |
1867 | #define X86_MATCH(model) \ |
1868 | X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ | |
1869 | INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) | |
1567c3e3 GG |
1870 | |
1871 | static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { | |
2fa9a3cf BP |
1872 | X86_MATCH(XEON_PHI_KNL), |
1873 | X86_MATCH(XEON_PHI_KNM), | |
1567c3e3 GG |
1874 | {} |
1875 | }; | |
1876 | ||
1877 | static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { | |
2fa9a3cf | 1878 | X86_MATCH(SKYLAKE_X), |
1567c3e3 GG |
1879 | {} |
1880 | }; | |
1881 | ||
1882 | static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { | |
2fa9a3cf BP |
1883 | X86_MATCH(ATOM_GOLDMONT), |
1884 | X86_MATCH(ATOM_GOLDMONT_D), | |
1885 | X86_MATCH(ATOM_GOLDMONT_PLUS), | |
1567c3e3 GG |
1886 | {} |
1887 | }; | |
1888 | ||
8bea0dfb GG |
1889 | static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, |
1890 | int num_delta_fratio) | |
1891 | { | |
1892 | int fratio, delta_fratio, found; | |
1893 | int err, i; | |
1894 | u64 msr; | |
1895 | ||
8bea0dfb GG |
1896 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); |
1897 | if (err) | |
1898 | return false; | |
1899 | ||
1900 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ | |
1901 | ||
1902 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); | |
1903 | if (err) | |
1904 | return false; | |
1905 | ||
1906 | fratio = (msr >> 8) & 0xFF; | |
1907 | i = 16; | |
1908 | found = 0; | |
1909 | do { | |
1910 | if (found >= num_delta_fratio) { | |
1911 | *turbo_freq = fratio; | |
1912 | return true; | |
1913 | } | |
1914 | ||
1915 | delta_fratio = (msr >> (i + 5)) & 0x7; | |
1916 | ||
1917 | if (delta_fratio) { | |
1918 | found += 1; | |
1919 | fratio -= delta_fratio; | |
1920 | } | |
1921 | ||
1922 | i += 8; | |
1923 | } while (i < 64); | |
1924 | ||
1925 | return true; | |
1926 | } | |
1927 | ||
2a0abc59 GG |
1928 | static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) |
1929 | { | |
1930 | u64 ratios, counts; | |
1931 | u32 group_size; | |
1932 | int err, i; | |
1933 | ||
1934 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); | |
1935 | if (err) | |
1936 | return false; | |
1937 | ||
1938 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ | |
1939 | ||
1940 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); | |
1941 | if (err) | |
1942 | return false; | |
1943 | ||
1944 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); | |
1945 | if (err) | |
1946 | return false; | |
1947 | ||
1948 | for (i = 0; i < 64; i += 8) { | |
1949 | group_size = (counts >> i) & 0xFF; | |
1950 | if (group_size >= size) { | |
1951 | *turbo_freq = (ratios >> i) & 0xFF; | |
1952 | return true; | |
1953 | } | |
1954 | } | |
1955 | ||
1956 | return false; | |
1957 | } | |
1958 | ||
1959 | static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) | |
1567c3e3 | 1960 | { |
23ccee22 | 1961 | u64 msr; |
1567c3e3 GG |
1962 | int err; |
1963 | ||
2a0abc59 | 1964 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); |
1567c3e3 GG |
1965 | if (err) |
1966 | return false; | |
1967 | ||
23ccee22 | 1968 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); |
1567c3e3 GG |
1969 | if (err) |
1970 | return false; | |
1971 | ||
23ccee22 GG |
1972 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ |
1973 | *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */ | |
1974 | ||
1975 | /* The CPU may have less than 4 cores */ | |
1976 | if (!*turbo_freq) | |
1977 | *turbo_freq = msr & 0xFF; /* 1C turbo */ | |
1567c3e3 | 1978 | |
1567c3e3 GG |
1979 | return true; |
1980 | } | |
1981 | ||
1982 | static bool intel_set_max_freq_ratio(void) | |
1983 | { | |
918229cd | 1984 | u64 base_freq, turbo_freq; |
f4291df1 | 1985 | u64 turbo_ratio; |
2a0abc59 | 1986 | |
298c6f99 GG |
1987 | if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) |
1988 | goto out; | |
1989 | ||
eacf0474 GG |
1990 | if (x86_match_cpu(has_glm_turbo_ratio_limits) && |
1991 | skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) | |
1992 | goto out; | |
1993 | ||
db441bd9 GG |
1994 | if (x86_match_cpu(has_knl_turbo_ratio_limits) && |
1995 | knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) | |
8bea0dfb GG |
1996 | goto out; |
1997 | ||
2a0abc59 GG |
1998 | if (x86_match_cpu(has_skx_turbo_ratio_limits) && |
1999 | skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) | |
2000 | goto out; | |
2001 | ||
2002 | if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) | |
2003 | goto out; | |
1567c3e3 GG |
2004 | |
2005 | return false; | |
2a0abc59 GG |
2006 | |
2007 | out: | |
9a6c2c3c GG |
2008 | /* |
2009 | * Some hypervisors advertise X86_FEATURE_APERFMPERF | |
2010 | * but then fill all MSR's with zeroes. | |
51beea88 GG |
2011 | * Some CPUs have turbo boost but don't declare any turbo ratio |
2012 | * in MSR_TURBO_RATIO_LIMIT. | |
9a6c2c3c | 2013 | */ |
51beea88 GG |
2014 | if (!base_freq || !turbo_freq) { |
2015 | pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n"); | |
9a6c2c3c GG |
2016 | return false; |
2017 | } | |
2018 | ||
f4291df1 GG |
2019 | turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq); |
2020 | if (!turbo_ratio) { | |
2021 | pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n"); | |
2022 | return false; | |
2023 | } | |
2024 | ||
2025 | arch_turbo_freq_ratio = turbo_ratio; | |
918229cd | 2026 | arch_set_max_freq_ratio(turbo_disabled()); |
f4291df1 | 2027 | |
2a0abc59 | 2028 | return true; |
1567c3e3 GG |
2029 | } |
2030 | ||
b56e7d45 | 2031 | static void init_counter_refs(void) |
1567c3e3 GG |
2032 | { |
2033 | u64 aperf, mperf; | |
2034 | ||
2035 | rdmsrl(MSR_IA32_APERF, aperf); | |
2036 | rdmsrl(MSR_IA32_MPERF, mperf); | |
2037 | ||
2038 | this_cpu_write(arch_prev_aperf, aperf); | |
2039 | this_cpu_write(arch_prev_mperf, mperf); | |
2040 | } | |
2041 | ||
b56e7d45 | 2042 | static void init_freq_invariance(bool secondary) |
1567c3e3 GG |
2043 | { |
2044 | bool ret = false; | |
2045 | ||
b56e7d45 | 2046 | if (!boot_cpu_has(X86_FEATURE_APERFMPERF)) |
1567c3e3 GG |
2047 | return; |
2048 | ||
b56e7d45 PZI |
2049 | if (secondary) { |
2050 | if (static_branch_likely(&arch_scale_freq_key)) { | |
2051 | init_counter_refs(); | |
2052 | } | |
2053 | return; | |
2054 | } | |
2055 | ||
1567c3e3 GG |
2056 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2057 | ret = intel_set_max_freq_ratio(); | |
2058 | ||
2059 | if (ret) { | |
b56e7d45 | 2060 | init_counter_refs(); |
1567c3e3 GG |
2061 | static_branch_enable(&arch_scale_freq_key); |
2062 | } else { | |
2063 | pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); | |
2064 | } | |
2065 | } | |
2066 | ||
e2b0d619 GG |
2067 | static void disable_freq_invariance_workfn(struct work_struct *work) |
2068 | { | |
2069 | static_branch_disable(&arch_scale_freq_key); | |
2070 | } | |
2071 | ||
2072 | static DECLARE_WORK(disable_freq_invariance_work, | |
2073 | disable_freq_invariance_workfn); | |
2074 | ||
1567c3e3 GG |
2075 | DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; |
2076 | ||
2077 | void arch_scale_freq_tick(void) | |
2078 | { | |
e2b0d619 | 2079 | u64 freq_scale = SCHED_CAPACITY_SCALE; |
1567c3e3 GG |
2080 | u64 aperf, mperf; |
2081 | u64 acnt, mcnt; | |
2082 | ||
2083 | if (!arch_scale_freq_invariant()) | |
2084 | return; | |
2085 | ||
2086 | rdmsrl(MSR_IA32_APERF, aperf); | |
2087 | rdmsrl(MSR_IA32_MPERF, mperf); | |
2088 | ||
2089 | acnt = aperf - this_cpu_read(arch_prev_aperf); | |
2090 | mcnt = mperf - this_cpu_read(arch_prev_mperf); | |
1567c3e3 GG |
2091 | |
2092 | this_cpu_write(arch_prev_aperf, aperf); | |
2093 | this_cpu_write(arch_prev_mperf, mperf); | |
2094 | ||
e2b0d619 GG |
2095 | if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt)) |
2096 | goto error; | |
2097 | ||
2098 | if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt) | |
2099 | goto error; | |
1567c3e3 GG |
2100 | |
2101 | freq_scale = div64_u64(acnt, mcnt); | |
e2b0d619 GG |
2102 | if (!freq_scale) |
2103 | goto error; | |
1567c3e3 GG |
2104 | |
2105 | if (freq_scale > SCHED_CAPACITY_SCALE) | |
2106 | freq_scale = SCHED_CAPACITY_SCALE; | |
2107 | ||
2108 | this_cpu_write(arch_freq_scale, freq_scale); | |
e2b0d619 GG |
2109 | return; |
2110 | ||
2111 | error: | |
2112 | pr_warn("Scheduler frequency invariance went wobbly, disabling!\n"); | |
2113 | schedule_work(&disable_freq_invariance_work); | |
2114 | } | |
2115 | #else | |
2116 | static inline void init_freq_invariance(bool secondary) | |
2117 | { | |
1567c3e3 | 2118 | } |
e2b0d619 | 2119 | #endif /* CONFIG_X86_64 */ |