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9ff554e9 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c767a54b | 2 | /* |
4cedb334 GOC |
3 | * x86 SMP booting functions |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
7 | * Copyright 2001 Andi Kleen, SuSE Labs. |
8 | * | |
9 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
10 | * whom a great many thanks are extended. | |
11 | * | |
12 | * Thanks to Intel for making available several different Pentium, | |
13 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
14 | * Original development of Linux SMP code supported by Caldera. | |
15 | * | |
4cedb334 GOC |
16 | * Fixes |
17 | * Felix Koop : NR_CPUS used properly | |
18 | * Jose Renau : Handle single CPU case. | |
19 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
20 | * Greg Wright : Fix for kernel stacks panic. | |
21 | * Erich Boleyn : MP v1.4 and additional changes. | |
22 | * Matthias Sattler : Changes for 2.1 kernel map. | |
23 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
24 | * Michael Chastain : Change trampoline.S to gnu as. | |
25 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
26 | * Ingo Molnar : Added APIC timers, based on code | |
27 | * from Jose Renau | |
28 | * Ingo Molnar : various cleanups and rewrites | |
29 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
30 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
31 | * Andi Kleen : Changed for SMP boot into long mode. | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
35 | * Andi Kleen : Converted to new state machine. | |
36 | * Ashok Raj : CPU hotplug support | |
37 | * Glauber Costa : i386 and x86_64 integration | |
38 | */ | |
39 | ||
c767a54b JP |
40 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
186f4360 | 44 | #include <linux/export.h> |
70708a18 | 45 | #include <linux/sched.h> |
105ab3d8 | 46 | #include <linux/sched/topology.h> |
ef8bd77f | 47 | #include <linux/sched/hotplug.h> |
68db0cf1 | 48 | #include <linux/sched/task_stack.h> |
69c18c15 | 49 | #include <linux/percpu.h> |
57c8a661 | 50 | #include <linux/memblock.h> |
cb3c8b90 GOC |
51 | #include <linux/err.h> |
52 | #include <linux/nmi.h> | |
69575d38 | 53 | #include <linux/tboot.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
98fa15f3 | 56 | #include <linux/numa.h> |
65fddcfc | 57 | #include <linux/pgtable.h> |
e2b0d619 | 58 | #include <linux/overflow.h> |
9c7d9017 | 59 | #include <linux/syscore_ops.h> |
69c18c15 | 60 | |
8aef135c | 61 | #include <asm/acpi.h> |
cb3c8b90 | 62 | #include <asm/desc.h> |
69c18c15 GC |
63 | #include <asm/nmi.h> |
64 | #include <asm/irq.h> | |
48927bbb | 65 | #include <asm/realmode.h> |
69c18c15 GC |
66 | #include <asm/cpu.h> |
67 | #include <asm/numa.h> | |
cb3c8b90 GOC |
68 | #include <asm/tlbflush.h> |
69 | #include <asm/mtrr.h> | |
ea530692 | 70 | #include <asm/mwait.h> |
7b6aa335 | 71 | #include <asm/apic.h> |
7167d08e | 72 | #include <asm/io_apic.h> |
78f7f1e5 | 73 | #include <asm/fpu/internal.h> |
569712b2 | 74 | #include <asm/setup.h> |
bdbcdd48 | 75 | #include <asm/uv/uv.h> |
cb3c8b90 | 76 | #include <linux/mc146818rtc.h> |
b81bb373 | 77 | #include <asm/i8259.h> |
646e29a1 | 78 | #include <asm/misc.h> |
9043442b | 79 | #include <asm/qspinlock.h> |
1340ccfa AS |
80 | #include <asm/intel-family.h> |
81 | #include <asm/cpu_device_id.h> | |
1f50ddb4 | 82 | #include <asm/spec-ctrl.h> |
447ae316 | 83 | #include <asm/hw_irq.h> |
c9a1ff31 | 84 | #include <asm/stackprotector.h> |
48927bbb | 85 | |
41ea6672 NF |
86 | #ifdef CONFIG_ACPI_CPPC_LIB |
87 | #include <acpi/cppc_acpi.h> | |
88 | #endif | |
89 | ||
a355352b | 90 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
93 | ||
94 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
96 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
97 | ||
2e4c54da LB |
98 | /* representing HT, core, and die siblings of each logical CPU */ |
99 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); | |
100 | EXPORT_PER_CPU_SYMBOL(cpu_die_map); | |
101 | ||
0816b0f0 | 102 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 103 | |
a355352b | 104 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 105 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 106 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 107 | |
1f12e32f | 108 | /* Logical package management. We might want to allocate that dynamically */ |
1f12e32f TG |
109 | unsigned int __max_logical_packages __read_mostly; |
110 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 111 | static unsigned int logical_packages __read_mostly; |
212bf4fd | 112 | static unsigned int logical_die __read_mostly; |
1f12e32f | 113 | |
70b8301f | 114 | /* Maximum number of SMT threads on any online core */ |
947134d9 | 115 | int __read_mostly __max_smt_threads = 1; |
70b8301f | 116 | |
7d25127c TC |
117 | /* Flag to indicate if a complete sched domain rebuild is required */ |
118 | bool x86_topology_update; | |
119 | ||
120 | int arch_update_cpu_topology(void) | |
121 | { | |
122 | int retval = x86_topology_update; | |
123 | ||
124 | x86_topology_update = false; | |
125 | return retval; | |
126 | } | |
127 | ||
f77aa308 TG |
128 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&rtc_lock, flags); | |
133 | CMOS_WRITE(0xa, 0xf); | |
134 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
135 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
136 | start_eip >> 4; | |
f77aa308 TG |
137 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
138 | start_eip & 0xf; | |
f77aa308 TG |
139 | } |
140 | ||
141 | static inline void smpboot_restore_warm_reset_vector(void) | |
142 | { | |
143 | unsigned long flags; | |
144 | ||
f77aa308 TG |
145 | /* |
146 | * Paranoid: Set warm reset code and vector here back | |
147 | * to default values. | |
148 | */ | |
149 | spin_lock_irqsave(&rtc_lock, flags); | |
150 | CMOS_WRITE(0, 0xf); | |
151 | spin_unlock_irqrestore(&rtc_lock, flags); | |
152 | ||
153 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
154 | } | |
155 | ||
41ea6672 | 156 | static void init_freq_invariance(bool secondary, bool cppc_ready); |
1567c3e3 | 157 | |
cb3c8b90 | 158 | /* |
30106c17 FY |
159 | * Report back to the Boot Processor during boot time or to the caller processor |
160 | * during CPU online. | |
cb3c8b90 | 161 | */ |
148f9bb8 | 162 | static void smp_callin(void) |
cb3c8b90 | 163 | { |
f91fecc0 | 164 | int cpuid; |
cb3c8b90 GOC |
165 | |
166 | /* | |
167 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
168 | * cpu_callout_mask guarantees we don't get here before |
169 | * an INIT_deassert IPI reaches our local APIC, so it is | |
170 | * now safe to touch our local APIC. | |
cb3c8b90 | 171 | */ |
e1c467e6 | 172 | cpuid = smp_processor_id(); |
cb3c8b90 | 173 | |
cb3c8b90 GOC |
174 | /* |
175 | * the boot CPU has finished the init stage and is spinning | |
176 | * on callin_map until we finish. We are free to set up this | |
177 | * CPU, first the APIC. (this is probably redundant on most | |
178 | * boards) | |
179 | */ | |
05f7e46d | 180 | apic_ap_setup(); |
cb3c8b90 | 181 | |
b565201c JS |
182 | /* |
183 | * Save our processor parameters. Note: this information | |
184 | * is needed for clock calibration. | |
185 | */ | |
186 | smp_store_cpu_info(cpuid); | |
187 | ||
76ce7cfe PT |
188 | /* |
189 | * The topology information must be up to date before | |
190 | * calibrate_delay() and notify_cpu_starting(). | |
191 | */ | |
192 | set_cpu_sibling_map(raw_smp_processor_id()); | |
193 | ||
41ea6672 | 194 | init_freq_invariance(true, false); |
1567c3e3 | 195 | |
cb3c8b90 GOC |
196 | /* |
197 | * Get our bogomips. | |
b565201c JS |
198 | * Update loops_per_jiffy in cpu_data. Previous call to |
199 | * smp_store_cpu_info() stored a value that is close but not as | |
200 | * accurate as the value just calculated. | |
cb3c8b90 | 201 | */ |
cb3c8b90 | 202 | calibrate_delay(); |
b565201c | 203 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 204 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 205 | |
5ef428c4 AK |
206 | wmb(); |
207 | ||
85257024 PZ |
208 | notify_cpu_starting(cpuid); |
209 | ||
cb3c8b90 GOC |
210 | /* |
211 | * Allow the master to continue. | |
212 | */ | |
c2d1cec1 | 213 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
214 | } |
215 | ||
e1c467e6 FY |
216 | static int cpu0_logical_apicid; |
217 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
218 | /* |
219 | * Activate a secondary processor. | |
220 | */ | |
148f9bb8 | 221 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
222 | { |
223 | /* | |
c7ad5ad2 AL |
224 | * Don't put *anything* except direct CPU state initialization |
225 | * before cpu_init(), SMP booting is too fragile that we want to | |
226 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 227 | */ |
7652ac92 | 228 | cr4_init(); |
e1c467e6 | 229 | |
fd89a137 | 230 | #ifdef CONFIG_X86_32 |
b40827fa | 231 | /* switch away from the initial page table */ |
fd89a137 JR |
232 | load_cr3(swapper_pg_dir); |
233 | __flush_tlb_all(); | |
234 | #endif | |
520d0308 | 235 | cpu_init_exception_handling(); |
4ba55e65 | 236 | cpu_init(); |
29368e09 | 237 | rcu_cpu_starting(raw_smp_processor_id()); |
4ba55e65 AL |
238 | x86_cpuinit.early_percpu_clock_init(); |
239 | preempt_disable(); | |
240 | smp_callin(); | |
241 | ||
242 | enable_start_cpu0 = 0; | |
243 | ||
bbc2ff6a GOC |
244 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
245 | barrier(); | |
246 | /* | |
a1652bb8 | 247 | * Check TSC synchronization with the boot CPU: |
bbc2ff6a GOC |
248 | */ |
249 | check_tsc_sync_target(); | |
250 | ||
1f50ddb4 TG |
251 | speculative_store_bypass_ht_init(); |
252 | ||
bbc2ff6a | 253 | /* |
8ed4f3e6 TG |
254 | * Lock vector_lock, set CPU online and bring the vector |
255 | * allocator online. Online must be set with vector_lock held | |
256 | * to prevent a concurrent irq setup/teardown from seeing a | |
257 | * half valid vector space. | |
bbc2ff6a | 258 | */ |
d388e5fd | 259 | lock_vector_lock(); |
c2d1cec1 | 260 | set_cpu_online(smp_processor_id(), true); |
8ed4f3e6 | 261 | lapic_online(); |
d388e5fd | 262 | unlock_vector_lock(); |
2a442c9c | 263 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 264 | x86_platform.nmi_init(); |
bbc2ff6a | 265 | |
0cefa5b9 MS |
266 | /* enable local interrupts */ |
267 | local_irq_enable(); | |
268 | ||
736decac | 269 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
270 | |
271 | wmb(); | |
fc6d73d6 | 272 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
273 | } |
274 | ||
6a4d2657 TG |
275 | /** |
276 | * topology_is_primary_thread - Check whether CPU is the primary SMT thread | |
277 | * @cpu: CPU to check | |
278 | */ | |
279 | bool topology_is_primary_thread(unsigned int cpu) | |
280 | { | |
281 | return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); | |
282 | } | |
283 | ||
f048c399 TG |
284 | /** |
285 | * topology_smt_supported - Check whether SMT is supported by the CPUs | |
286 | */ | |
287 | bool topology_smt_supported(void) | |
288 | { | |
289 | return smp_num_siblings > 1; | |
290 | } | |
291 | ||
30bb9811 AK |
292 | /** |
293 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
294 | * | |
295 | * Returns logical package id or -1 if not found | |
296 | */ | |
297 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
298 | { | |
299 | int cpu; | |
300 | ||
301 | for_each_possible_cpu(cpu) { | |
302 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
303 | ||
304 | if (c->initialized && c->phys_proc_id == phys_pkg) | |
305 | return c->logical_proc_id; | |
306 | } | |
307 | return -1; | |
308 | } | |
309 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
212bf4fd LB |
310 | /** |
311 | * topology_phys_to_logical_die - Map a physical die id to logical | |
312 | * | |
313 | * Returns logical die id or -1 if not found | |
314 | */ | |
315 | int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) | |
316 | { | |
317 | int cpu; | |
318 | int proc_id = cpu_data(cur_cpu).phys_proc_id; | |
319 | ||
320 | for_each_possible_cpu(cpu) { | |
321 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
322 | ||
323 | if (c->initialized && c->cpu_die_id == die_id && | |
324 | c->phys_proc_id == proc_id) | |
325 | return c->logical_die_id; | |
326 | } | |
327 | return -1; | |
328 | } | |
329 | EXPORT_SYMBOL(topology_phys_to_logical_die); | |
30bb9811 | 330 | |
9d85eb91 TG |
331 | /** |
332 | * topology_update_package_map - Update the physical to logical package map | |
333 | * @pkg: The physical package id as retrieved via CPUID | |
334 | * @cpu: The cpu for which this is updated | |
335 | */ | |
336 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 337 | { |
30bb9811 | 338 | int new; |
1f12e32f | 339 | |
30bb9811 AK |
340 | /* Already available somewhere? */ |
341 | new = topology_phys_to_logical_pkg(pkg); | |
342 | if (new >= 0) | |
1f12e32f TG |
343 | goto found; |
344 | ||
7b0501b1 | 345 | new = logical_packages++; |
9d85eb91 TG |
346 | if (new != pkg) { |
347 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
348 | cpu, pkg, new); | |
349 | } | |
1f12e32f | 350 | found: |
30bb9811 | 351 | cpu_data(cpu).logical_proc_id = new; |
1f12e32f TG |
352 | return 0; |
353 | } | |
212bf4fd LB |
354 | /** |
355 | * topology_update_die_map - Update the physical to logical die map | |
356 | * @die: The die id as retrieved via CPUID | |
357 | * @cpu: The cpu for which this is updated | |
358 | */ | |
359 | int topology_update_die_map(unsigned int die, unsigned int cpu) | |
360 | { | |
361 | int new; | |
362 | ||
363 | /* Already available somewhere? */ | |
364 | new = topology_phys_to_logical_die(die, cpu); | |
365 | if (new >= 0) | |
366 | goto found; | |
367 | ||
368 | new = logical_die++; | |
369 | if (new != die) { | |
370 | pr_info("CPU %u Converting physical %u to logical die %u\n", | |
371 | cpu, die, new); | |
372 | } | |
373 | found: | |
374 | cpu_data(cpu).logical_die_id = new; | |
375 | return 0; | |
376 | } | |
1f12e32f | 377 | |
30106c17 FY |
378 | void __init smp_store_boot_cpu_info(void) |
379 | { | |
380 | int id = 0; /* CPU 0 */ | |
381 | struct cpuinfo_x86 *c = &cpu_data(id); | |
382 | ||
383 | *c = boot_cpu_data; | |
384 | c->cpu_index = id; | |
b4c0a732 | 385 | topology_update_package_map(c->phys_proc_id, id); |
212bf4fd | 386 | topology_update_die_map(c->cpu_die_id, id); |
30bb9811 | 387 | c->initialized = true; |
30106c17 FY |
388 | } |
389 | ||
1d89a7f0 GOC |
390 | /* |
391 | * The bootstrap kernel entry code has set these up. Save them for | |
392 | * a given CPU | |
393 | */ | |
148f9bb8 | 394 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
395 | { |
396 | struct cpuinfo_x86 *c = &cpu_data(id); | |
397 | ||
30bb9811 AK |
398 | /* Copy boot_cpu_data only on the first bringup */ |
399 | if (!c->initialized) | |
400 | *c = boot_cpu_data; | |
1d89a7f0 | 401 | c->cpu_index = id; |
30106c17 FY |
402 | /* |
403 | * During boot time, CPU0 has this setup already. Save the info when | |
404 | * bringing up AP or offlined CPU0. | |
405 | */ | |
406 | identify_secondary_cpu(c); | |
30bb9811 | 407 | c->initialized = true; |
1d89a7f0 GOC |
408 | } |
409 | ||
cebf15eb DH |
410 | static bool |
411 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
412 | { | |
413 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
414 | ||
415 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
416 | } | |
417 | ||
148f9bb8 | 418 | static bool |
316ad248 | 419 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 420 | { |
316ad248 PZ |
421 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
422 | ||
cebf15eb | 423 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
424 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
425 | "[node: %d != %d]. Ignoring dependency.\n", | |
426 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
427 | } | |
428 | ||
7d79a7bd | 429 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 430 | do { \ |
7d79a7bd BG |
431 | cpumask_set_cpu((c1), mfunc(c2)); \ |
432 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
433 | } while (0) |
434 | ||
148f9bb8 | 435 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 436 | { |
362f924b | 437 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
438 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
439 | ||
440 | if (c->phys_proc_id == o->phys_proc_id && | |
7745f03e | 441 | c->cpu_die_id == o->cpu_die_id && |
79a8b9aa BP |
442 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
443 | if (c->cpu_core_id == o->cpu_core_id) | |
444 | return topology_sane(c, o, "smt"); | |
445 | ||
446 | if ((c->cu_id != 0xff) && | |
447 | (o->cu_id != 0xff) && | |
448 | (c->cu_id == o->cu_id)) | |
449 | return topology_sane(c, o, "smt"); | |
450 | } | |
316ad248 PZ |
451 | |
452 | } else if (c->phys_proc_id == o->phys_proc_id && | |
7745f03e | 453 | c->cpu_die_id == o->cpu_die_id && |
316ad248 PZ |
454 | c->cpu_core_id == o->cpu_core_id) { |
455 | return topology_sane(c, o, "smt"); | |
456 | } | |
457 | ||
458 | return false; | |
459 | } | |
460 | ||
1340ccfa AS |
461 | /* |
462 | * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. | |
463 | * | |
464 | * These are Intel CPUs that enumerate an LLC that is shared by | |
465 | * multiple NUMA nodes. The LLC on these systems is shared for | |
466 | * off-package data access but private to the NUMA node (half | |
467 | * of the package) for on-package access. | |
468 | * | |
469 | * CPUID (the source of the information about the LLC) can only | |
470 | * enumerate the cache as being shared *or* unshared, but not | |
471 | * this particular configuration. The CPU in this case enumerates | |
472 | * the cache to be shared across the entire package (spanning both | |
473 | * NUMA nodes). | |
474 | */ | |
475 | ||
476 | static const struct x86_cpu_id snc_cpu[] = { | |
adefe55e | 477 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), |
1340ccfa AS |
478 | {} |
479 | }; | |
480 | ||
148f9bb8 | 481 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
482 | { |
483 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
484 | ||
1340ccfa AS |
485 | /* Do not match if we do not have a valid APICID for cpu: */ |
486 | if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) | |
487 | return false; | |
316ad248 | 488 | |
1340ccfa AS |
489 | /* Do not match if LLC id does not match: */ |
490 | if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) | |
491 | return false; | |
492 | ||
493 | /* | |
494 | * Allow the SNC topology without warning. Return of false | |
495 | * means 'c' does not share the LLC of 'o'. This will be | |
496 | * reflected to userspace. | |
497 | */ | |
498 | if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) | |
499 | return false; | |
500 | ||
501 | return topology_sane(c, o, "llc"); | |
d4fbe4f0 AH |
502 | } |
503 | ||
cebf15eb DH |
504 | /* |
505 | * Unlike the other levels, we do not enforce keeping a | |
506 | * multicore group inside a NUMA node. If this happens, we will | |
507 | * discard the MC level of the topology later. | |
508 | */ | |
169d0869 | 509 | static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 510 | { |
cebf15eb DH |
511 | if (c->phys_proc_id == o->phys_proc_id) |
512 | return true; | |
316ad248 PZ |
513 | return false; |
514 | } | |
1d89a7f0 | 515 | |
2e4c54da LB |
516 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
517 | { | |
518 | if ((c->phys_proc_id == o->phys_proc_id) && | |
519 | (c->cpu_die_id == o->cpu_die_id)) | |
520 | return true; | |
521 | return false; | |
522 | } | |
523 | ||
524 | ||
d3d37d85 TC |
525 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
526 | static inline int x86_sched_itmt_flags(void) | |
527 | { | |
528 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
529 | } | |
530 | ||
531 | #ifdef CONFIG_SCHED_MC | |
532 | static int x86_core_flags(void) | |
533 | { | |
534 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
535 | } | |
536 | #endif | |
537 | #ifdef CONFIG_SCHED_SMT | |
538 | static int x86_smt_flags(void) | |
539 | { | |
540 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
541 | } | |
542 | #endif | |
543 | #endif | |
544 | ||
8f37961c | 545 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 546 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 547 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
548 | #endif |
549 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 550 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
551 | #endif |
552 | { NULL, }, | |
553 | }; | |
8f37961c TC |
554 | |
555 | static struct sched_domain_topology_level x86_topology[] = { | |
556 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 557 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
558 | #endif |
559 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 560 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
561 | #endif |
562 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
563 | { NULL, }, | |
564 | }; | |
565 | ||
cebf15eb | 566 | /* |
8f37961c | 567 | * Set if a package/die has multiple NUMA nodes inside. |
1340ccfa AS |
568 | * AMD Magny-Cours, Intel Cluster-on-Die, and Intel |
569 | * Sub-NUMA Clustering have this. | |
cebf15eb | 570 | */ |
8f37961c | 571 | static bool x86_has_numa_in_package; |
cebf15eb | 572 | |
148f9bb8 | 573 | void set_cpu_sibling_map(int cpu) |
768d9505 | 574 | { |
316ad248 | 575 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 576 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 577 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 578 | struct cpuinfo_x86 *o; |
70b8301f | 579 | int i, threads; |
768d9505 | 580 | |
c2d1cec1 | 581 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 582 | |
b0bc225d | 583 | if (!has_mp) { |
7d79a7bd | 584 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 585 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 586 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
2e4c54da | 587 | cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); |
768d9505 GC |
588 | c->booted_cores = 1; |
589 | return; | |
590 | } | |
591 | ||
c2d1cec1 | 592 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
593 | o = &cpu_data(i); |
594 | ||
595 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 596 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 597 | |
b0bc225d | 598 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 599 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 600 | |
ceb1cbac KB |
601 | } |
602 | ||
603 | /* | |
604 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 605 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
606 | */ |
607 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
608 | o = &cpu_data(i); | |
609 | ||
169d0869 | 610 | if ((i == cpu) || (has_mp && match_pkg(c, o))) { |
7d79a7bd | 611 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 612 | |
768d9505 GC |
613 | /* |
614 | * Does this new cpu bringup a new core? | |
615 | */ | |
7d79a7bd BG |
616 | if (cpumask_weight( |
617 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
618 | /* |
619 | * for each core in package, increment | |
620 | * the booted_cores for this new cpu | |
621 | */ | |
7d79a7bd BG |
622 | if (cpumask_first( |
623 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
624 | c->booted_cores++; |
625 | /* | |
626 | * increment the core count for all | |
627 | * the other cpus in this package | |
628 | */ | |
629 | if (i != cpu) | |
630 | cpu_data(i).booted_cores++; | |
631 | } else if (i != cpu && !c->booted_cores) | |
632 | c->booted_cores = cpu_data(i).booted_cores; | |
633 | } | |
169d0869 | 634 | if (match_pkg(c, o) && !topology_same_node(c, o)) |
8f37961c | 635 | x86_has_numa_in_package = true; |
2e4c54da LB |
636 | |
637 | if ((i == cpu) || (has_mp && match_die(c, o))) | |
638 | link_mask(topology_die_cpumask, cpu, i); | |
768d9505 | 639 | } |
70b8301f AK |
640 | |
641 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
642 | if (threads > __max_smt_threads) | |
643 | __max_smt_threads = threads; | |
768d9505 GC |
644 | } |
645 | ||
70708a18 | 646 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 647 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 648 | { |
9f646389 | 649 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
650 | } |
651 | ||
a4928cff | 652 | static void impress_friends(void) |
904541e2 GOC |
653 | { |
654 | int cpu; | |
655 | unsigned long bogosum = 0; | |
656 | /* | |
657 | * Allow the user to impress friends. | |
658 | */ | |
c767a54b | 659 | pr_debug("Before bogomips\n"); |
904541e2 | 660 | for_each_possible_cpu(cpu) |
c2d1cec1 | 661 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 662 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 663 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 664 | num_online_cpus(), |
904541e2 GOC |
665 | bogosum/(500000/HZ), |
666 | (bogosum/(5000/HZ))%100); | |
667 | ||
c767a54b | 668 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
669 | } |
670 | ||
569712b2 | 671 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
672 | { |
673 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 674 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
675 | int timeout; |
676 | u32 status; | |
677 | ||
c767a54b | 678 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
679 | |
680 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 681 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
682 | |
683 | /* | |
684 | * Wait for idle. | |
685 | */ | |
686 | status = safe_apic_wait_icr_idle(); | |
687 | if (status) | |
c767a54b | 688 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 689 | |
1b374e4d | 690 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
691 | |
692 | timeout = 0; | |
693 | do { | |
694 | udelay(100); | |
695 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
696 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
697 | ||
698 | switch (status) { | |
699 | case APIC_ICR_RR_VALID: | |
700 | status = apic_read(APIC_RRR); | |
c767a54b | 701 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
702 | break; |
703 | default: | |
c767a54b | 704 | pr_cont("failed\n"); |
cb3c8b90 GOC |
705 | } |
706 | } | |
707 | } | |
708 | ||
d68921f9 LB |
709 | /* |
710 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
711 | * that there should be a 10ms delay between the BSP asserting INIT | |
712 | * and de-asserting INIT, when starting a remote processor. | |
713 | * But that slows boot and resume on modern processors, which include | |
714 | * many cores and don't require that delay. | |
715 | * | |
716 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 717 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
718 | */ |
719 | #define UDELAY_10MS_DEFAULT 10000 | |
720 | ||
656279a1 | 721 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
722 | |
723 | static int __init cpu_init_udelay(char *str) | |
724 | { | |
725 | get_option(&str, &init_udelay); | |
726 | ||
727 | return 0; | |
728 | } | |
729 | early_param("cpu_init_udelay", cpu_init_udelay); | |
730 | ||
1a744cb3 LB |
731 | static void __init smp_quirk_init_udelay(void) |
732 | { | |
733 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 734 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
735 | return; |
736 | ||
737 | /* if modern processor, use no delay */ | |
738 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
0b13bec7 | 739 | ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || |
656279a1 | 740 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 741 | init_udelay = 0; |
656279a1 LB |
742 | return; |
743 | } | |
f1ccd249 LB |
744 | /* else, use legacy delay */ |
745 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
746 | } |
747 | ||
cb3c8b90 GOC |
748 | /* |
749 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
750 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
751 | * won't ... remember to clear down the APIC, etc later. | |
752 | */ | |
148f9bb8 | 753 | int |
e1c467e6 | 754 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 | 755 | { |
8c44963b | 756 | u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; |
cb3c8b90 GOC |
757 | unsigned long send_status, accept_status = 0; |
758 | int maxlvt; | |
759 | ||
760 | /* Target chip */ | |
cb3c8b90 GOC |
761 | /* Boot on the stack */ |
762 | /* Kick the second */ | |
e57d04e5 | 763 | apic_icr_write(APIC_DM_NMI | dm, apicid); |
cb3c8b90 | 764 | |
cfc1b9a6 | 765 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
766 | send_status = safe_apic_wait_icr_idle(); |
767 | ||
768 | /* | |
769 | * Give the other CPU some time to accept the IPI. | |
770 | */ | |
771 | udelay(200); | |
cff9ab2b | 772 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
773 | maxlvt = lapic_get_maxlvt(); |
774 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
775 | apic_write(APIC_ESR, 0); | |
776 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
777 | } | |
c767a54b | 778 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
779 | |
780 | if (send_status) | |
c767a54b | 781 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 782 | if (accept_status) |
c767a54b | 783 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
784 | |
785 | return (send_status | accept_status); | |
786 | } | |
cb3c8b90 | 787 | |
148f9bb8 | 788 | static int |
569712b2 | 789 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 790 | { |
f5d6a52f | 791 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
792 | int maxlvt, num_starts, j; |
793 | ||
593f4a78 MR |
794 | maxlvt = lapic_get_maxlvt(); |
795 | ||
cb3c8b90 GOC |
796 | /* |
797 | * Be paranoid about clearing APIC errors. | |
798 | */ | |
cff9ab2b | 799 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
800 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
801 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
802 | apic_read(APIC_ESR); |
803 | } | |
804 | ||
c767a54b | 805 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
806 | |
807 | /* | |
808 | * Turn INIT on target chip | |
809 | */ | |
cb3c8b90 GOC |
810 | /* |
811 | * Send IPI | |
812 | */ | |
1b374e4d SS |
813 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
814 | phys_apicid); | |
cb3c8b90 | 815 | |
cfc1b9a6 | 816 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
817 | send_status = safe_apic_wait_icr_idle(); |
818 | ||
7cb68598 | 819 | udelay(init_udelay); |
cb3c8b90 | 820 | |
c767a54b | 821 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
822 | |
823 | /* Target chip */ | |
cb3c8b90 | 824 | /* Send IPI */ |
1b374e4d | 825 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 826 | |
cfc1b9a6 | 827 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
828 | send_status = safe_apic_wait_icr_idle(); |
829 | ||
830 | mb(); | |
cb3c8b90 GOC |
831 | |
832 | /* | |
833 | * Should we send STARTUP IPIs ? | |
834 | * | |
835 | * Determine this based on the APIC version. | |
836 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
837 | */ | |
cff9ab2b | 838 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
839 | num_starts = 2; |
840 | else | |
841 | num_starts = 0; | |
842 | ||
cb3c8b90 GOC |
843 | /* |
844 | * Run STARTUP IPI loop. | |
845 | */ | |
c767a54b | 846 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 847 | |
cb3c8b90 | 848 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 849 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
850 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
851 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 852 | apic_read(APIC_ESR); |
c767a54b | 853 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
854 | |
855 | /* | |
856 | * STARTUP IPI | |
857 | */ | |
858 | ||
859 | /* Target chip */ | |
cb3c8b90 GOC |
860 | /* Boot on the stack */ |
861 | /* Kick the second */ | |
1b374e4d SS |
862 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
863 | phys_apicid); | |
cb3c8b90 GOC |
864 | |
865 | /* | |
866 | * Give the other CPU some time to accept the IPI. | |
867 | */ | |
fcafddec LB |
868 | if (init_udelay == 0) |
869 | udelay(10); | |
870 | else | |
a9bcaa02 | 871 | udelay(300); |
cb3c8b90 | 872 | |
c767a54b | 873 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 874 | |
cfc1b9a6 | 875 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
876 | send_status = safe_apic_wait_icr_idle(); |
877 | ||
878 | /* | |
879 | * Give the other CPU some time to accept the IPI. | |
880 | */ | |
fcafddec LB |
881 | if (init_udelay == 0) |
882 | udelay(10); | |
883 | else | |
a9bcaa02 | 884 | udelay(200); |
cb3c8b90 | 885 | |
593f4a78 | 886 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 887 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
888 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
889 | if (send_status || accept_status) | |
890 | break; | |
891 | } | |
c767a54b | 892 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
893 | |
894 | if (send_status) | |
c767a54b | 895 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 896 | if (accept_status) |
c767a54b | 897 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
898 | |
899 | return (send_status | accept_status); | |
900 | } | |
cb3c8b90 | 901 | |
2eaad1fd | 902 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 903 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd | 904 | { |
98fa15f3 | 905 | static int current_node = NUMA_NO_NODE; |
4adc8b71 | 906 | int node = early_cpu_to_node(cpu); |
a17bce4d | 907 | static int width, node_width; |
646e29a1 BP |
908 | |
909 | if (!width) | |
910 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 911 | |
a17bce4d BP |
912 | if (!node_width) |
913 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
914 | ||
915 | if (cpu == 1) | |
916 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
917 | ||
719b3680 | 918 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
919 | if (node != current_node) { |
920 | if (current_node > (-1)) | |
a17bce4d | 921 | pr_cont("\n"); |
2eaad1fd | 922 | current_node = node; |
a17bce4d BP |
923 | |
924 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
925 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 926 | } |
646e29a1 BP |
927 | |
928 | /* Add padding for the BSP */ | |
929 | if (cpu == 1) | |
930 | pr_cont("%*s", width + 1, " "); | |
931 | ||
932 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
933 | ||
2eaad1fd MT |
934 | } else |
935 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
936 | node, cpu, apicid); | |
937 | } | |
938 | ||
e1c467e6 FY |
939 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
940 | { | |
941 | int cpu; | |
942 | ||
943 | cpu = smp_processor_id(); | |
944 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
945 | return NMI_HANDLED; | |
946 | ||
947 | return NMI_DONE; | |
948 | } | |
949 | ||
950 | /* | |
951 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
952 | * | |
953 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
954 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
955 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
956 | * | |
957 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
958 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
959 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
960 | * real platform and request are available. | |
961 | */ | |
148f9bb8 | 962 | static int |
e1c467e6 FY |
963 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
964 | int *cpu0_nmi_registered) | |
965 | { | |
966 | int id; | |
967 | int boot_error; | |
968 | ||
ea7bdc65 JK |
969 | preempt_disable(); |
970 | ||
e1c467e6 FY |
971 | /* |
972 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
973 | */ | |
ea7bdc65 JK |
974 | if (cpu) { |
975 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
976 | goto out; | |
977 | } | |
e1c467e6 FY |
978 | |
979 | /* | |
980 | * Wake up BSP by nmi. | |
981 | * | |
982 | * Register a NMI handler to help wake up CPU0. | |
983 | */ | |
984 | boot_error = register_nmi_handler(NMI_LOCAL, | |
985 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
986 | ||
987 | if (!boot_error) { | |
988 | enable_start_cpu0 = 1; | |
989 | *cpu0_nmi_registered = 1; | |
8c44963b | 990 | id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; |
e1c467e6 FY |
991 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); |
992 | } | |
ea7bdc65 JK |
993 | |
994 | out: | |
995 | preempt_enable(); | |
e1c467e6 FY |
996 | |
997 | return boot_error; | |
998 | } | |
999 | ||
66c7ceb4 | 1000 | int common_cpu_up(unsigned int cpu, struct task_struct *idle) |
3f85483b | 1001 | { |
66c7ceb4 TG |
1002 | int ret; |
1003 | ||
3f85483b BO |
1004 | /* Just in case we booted with a single CPU. */ |
1005 | alternatives_enable_smp(); | |
1006 | ||
1007 | per_cpu(current_task, cpu) = idle; | |
c9a1ff31 | 1008 | cpu_init_stack_canary(cpu, idle); |
3f85483b | 1009 | |
66c7ceb4 TG |
1010 | /* Initialize the interrupt stack(s) */ |
1011 | ret = irq_init_percpu_irqstack(cpu); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | ||
3f85483b BO |
1015 | #ifdef CONFIG_X86_32 |
1016 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
cd493a6d | 1017 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 1018 | #else |
3f85483b BO |
1019 | initial_gs = per_cpu_offset(cpu); |
1020 | #endif | |
66c7ceb4 | 1021 | return 0; |
3f85483b BO |
1022 | } |
1023 | ||
cb3c8b90 GOC |
1024 | /* |
1025 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
1026 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
1027 | * Returns zero if CPU booted OK, else error code from |
1028 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 1029 | */ |
10e66760 VK |
1030 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
1031 | int *cpu0_nmi_registered) | |
cb3c8b90 | 1032 | { |
48927bbb | 1033 | /* start_ip had better be page-aligned! */ |
f37240f1 | 1034 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 1035 | |
cb3c8b90 | 1036 | unsigned long boot_error = 0; |
ce4b1b16 | 1037 | unsigned long timeout; |
cb3c8b90 | 1038 | |
b9b1a9c3 | 1039 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 1040 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 1041 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 1042 | initial_stack = idle->thread.sp; |
cb3c8b90 | 1043 | |
613e396b | 1044 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 1045 | init_espfix_ap(cpu); |
20d5e4a9 | 1046 | |
2eaad1fd MT |
1047 | /* So we see what's up */ |
1048 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
1049 | |
1050 | /* | |
1051 | * This grunge runs the startup process for | |
1052 | * the targeted processor. | |
1053 | */ | |
1054 | ||
e348caef | 1055 | if (x86_platform.legacy.warm_reset) { |
cb3c8b90 | 1056 | |
cfc1b9a6 | 1057 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 1058 | |
34d05591 JS |
1059 | smpboot_setup_warm_reset_vector(start_ip); |
1060 | /* | |
1061 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1062 | */ |
cff9ab2b | 1063 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1064 | apic_write(APIC_ESR, 0); |
1065 | apic_read(APIC_ESR); | |
1066 | } | |
34d05591 | 1067 | } |
cb3c8b90 | 1068 | |
ce4b1b16 IM |
1069 | /* |
1070 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1071 | * cpu_initialized_mask set if previous attempt to online | |
1072 | * it timed-out. Clear cpu_initialized_mask so that after | |
1073 | * INIT/SIPI it could start with a clean state. | |
1074 | */ | |
1075 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1076 | smp_mb(); | |
1077 | ||
cb3c8b90 | 1078 | /* |
e1c467e6 FY |
1079 | * Wake up a CPU in difference cases: |
1080 | * - Use the method in the APIC driver if it's defined | |
1081 | * Otherwise, | |
1082 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1083 | */ |
1f5bcabf IM |
1084 | if (apic->wakeup_secondary_cpu) |
1085 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1086 | else | |
e1c467e6 | 1087 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 1088 | cpu0_nmi_registered); |
cb3c8b90 GOC |
1089 | |
1090 | if (!boot_error) { | |
1091 | /* | |
6e38f1e7 | 1092 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1093 | */ |
ce4b1b16 IM |
1094 | boot_error = -1; |
1095 | timeout = jiffies + 10*HZ; | |
1096 | while (time_before(jiffies, timeout)) { | |
1097 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1098 | /* | |
1099 | * Tell AP to proceed with initialization | |
1100 | */ | |
1101 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1102 | boot_error = 0; | |
1103 | break; | |
1104 | } | |
ce4b1b16 IM |
1105 | schedule(); |
1106 | } | |
1107 | } | |
cb3c8b90 | 1108 | |
ce4b1b16 | 1109 | if (!boot_error) { |
cb3c8b90 | 1110 | /* |
ce4b1b16 | 1111 | * Wait till AP completes initial initialization |
cb3c8b90 | 1112 | */ |
ce4b1b16 | 1113 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1114 | /* |
1115 | * Allow other tasks to run while we wait for the | |
1116 | * AP to come online. This also gives a chance | |
1117 | * for the MTRR work(triggered by the AP coming online) | |
1118 | * to be completed in the stop machine context. | |
1119 | */ | |
1120 | schedule(); | |
cb3c8b90 | 1121 | } |
cb3c8b90 GOC |
1122 | } |
1123 | ||
e348caef | 1124 | if (x86_platform.legacy.warm_reset) { |
02421f98 YL |
1125 | /* |
1126 | * Cleanup possible dangling ends... | |
1127 | */ | |
1128 | smpboot_restore_warm_reset_vector(); | |
1129 | } | |
e1c467e6 | 1130 | |
cb3c8b90 GOC |
1131 | return boot_error; |
1132 | } | |
1133 | ||
148f9bb8 | 1134 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1135 | { |
a21769a4 | 1136 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1137 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1138 | unsigned long flags; |
10e66760 | 1139 | int err, ret = 0; |
cb3c8b90 | 1140 | |
7a10e2a9 | 1141 | lockdep_assert_irqs_enabled(); |
cb3c8b90 | 1142 | |
cfc1b9a6 | 1143 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1144 | |
30106c17 | 1145 | if (apicid == BAD_APICID || |
c284b42a | 1146 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1147 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1148 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1149 | return -EINVAL; |
1150 | } | |
1151 | ||
1152 | /* | |
1153 | * Already booted CPU? | |
1154 | */ | |
c2d1cec1 | 1155 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1156 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1157 | return -ENOSYS; |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * Save current MTRR state in case it was changed since early boot | |
1162 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1163 | */ | |
1164 | mtrr_save_state(); | |
1165 | ||
2a442c9c PM |
1166 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1167 | err = cpu_check_up_prepare(cpu); | |
1168 | if (err && err != -EBUSY) | |
1169 | return err; | |
cb3c8b90 | 1170 | |
644c1541 | 1171 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1172 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1173 | |
66c7ceb4 TG |
1174 | err = common_cpu_up(cpu, tidle); |
1175 | if (err) | |
1176 | return err; | |
3f85483b | 1177 | |
10e66760 | 1178 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1179 | if (err) { |
feef1e8e | 1180 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1181 | ret = -EIO; |
1182 | goto unreg_nmi; | |
cb3c8b90 GOC |
1183 | } |
1184 | ||
1185 | /* | |
1186 | * Check TSC synchronization with the AP (keep irqs disabled | |
1187 | * while doing so): | |
1188 | */ | |
1189 | local_irq_save(flags); | |
1190 | check_tsc_sync_source(cpu); | |
1191 | local_irq_restore(flags); | |
1192 | ||
7c04e64a | 1193 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1194 | cpu_relax(); |
1195 | touch_nmi_watchdog(); | |
1196 | } | |
1197 | ||
10e66760 VK |
1198 | unreg_nmi: |
1199 | /* | |
1200 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1201 | * to avoid impact of possible long unregister time. | |
1202 | */ | |
1203 | if (cpu0_nmi_registered) | |
1204 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1205 | ||
1206 | return ret; | |
cb3c8b90 GOC |
1207 | } |
1208 | ||
7167d08e HK |
1209 | /** |
1210 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1211 | */ | |
1212 | void arch_disable_smp_support(void) | |
1213 | { | |
1214 | disable_ioapic_support(); | |
1215 | } | |
1216 | ||
8aef135c GOC |
1217 | /* |
1218 | * Fall back to non SMP mode after errors. | |
1219 | * | |
1220 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1221 | */ | |
1222 | static __init void disable_smp(void) | |
1223 | { | |
613c25ef TG |
1224 | pr_info("SMP disabled\n"); |
1225 | ||
ef4c59a4 TG |
1226 | disable_ioapic_support(); |
1227 | ||
4f062896 RR |
1228 | init_cpu_present(cpumask_of(0)); |
1229 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1230 | |
8aef135c | 1231 | if (smp_found_config) |
b6df1b8b | 1232 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1233 | else |
b6df1b8b | 1234 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1235 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1236 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
2e4c54da | 1237 | cpumask_set_cpu(0, topology_die_cpumask(0)); |
8aef135c GOC |
1238 | } |
1239 | ||
1240 | /* | |
1241 | * Various sanity checks. | |
1242 | */ | |
4f45ed9f | 1243 | static void __init smp_sanity_check(void) |
8aef135c | 1244 | { |
ac23d4ee | 1245 | preempt_disable(); |
a58f03b0 | 1246 | |
1ff2f20d | 1247 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1248 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1249 | unsigned int cpu; | |
1250 | unsigned nr; | |
1251 | ||
c767a54b JP |
1252 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1253 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1254 | |
1255 | nr = 0; | |
1256 | for_each_present_cpu(cpu) { | |
1257 | if (nr >= 8) | |
c2d1cec1 | 1258 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1259 | nr++; |
1260 | } | |
1261 | ||
1262 | nr = 0; | |
1263 | for_each_possible_cpu(cpu) { | |
1264 | if (nr >= 8) | |
c2d1cec1 | 1265 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1266 | nr++; |
1267 | } | |
1268 | ||
1269 | nr_cpu_ids = 8; | |
1270 | } | |
1271 | #endif | |
1272 | ||
8aef135c | 1273 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1274 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1275 | hard_smp_processor_id()); |
1276 | ||
8aef135c GOC |
1277 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1278 | } | |
1279 | ||
8aef135c GOC |
1280 | /* |
1281 | * Should not be necessary because the MP table should list the boot | |
1282 | * CPU too, but we do it for the sake of robustness anyway. | |
1283 | */ | |
a27a6210 | 1284 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1285 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1286 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1287 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1288 | } | |
ac23d4ee | 1289 | preempt_enable(); |
8aef135c GOC |
1290 | } |
1291 | ||
1292 | static void __init smp_cpu_index_default(void) | |
1293 | { | |
1294 | int i; | |
1295 | struct cpuinfo_x86 *c; | |
1296 | ||
7c04e64a | 1297 | for_each_possible_cpu(i) { |
8aef135c GOC |
1298 | c = &cpu_data(i); |
1299 | /* mark all to hotplug */ | |
9628937d | 1300 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1301 | } |
1302 | } | |
1303 | ||
4b1244b4 DL |
1304 | static void __init smp_get_logical_apicid(void) |
1305 | { | |
1306 | if (x2apic_mode) | |
1307 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1308 | else | |
1309 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1310 | } | |
1311 | ||
8aef135c | 1312 | /* |
935356ce DL |
1313 | * Prepare for SMP bootup. |
1314 | * @max_cpus: configured maximum number of CPUs, It is a legacy parameter | |
1315 | * for common interface support. | |
8aef135c GOC |
1316 | */ |
1317 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1318 | { | |
7ad728f9 RR |
1319 | unsigned int i; |
1320 | ||
8aef135c | 1321 | smp_cpu_index_default(); |
792363d2 | 1322 | |
8aef135c GOC |
1323 | /* |
1324 | * Setup boot CPU information | |
1325 | */ | |
30106c17 | 1326 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1327 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1328 | mb(); | |
bd22a2f1 | 1329 | |
7ad728f9 | 1330 | for_each_possible_cpu(i) { |
79f55997 LZ |
1331 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1332 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
2e4c54da | 1333 | zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); |
b3d7336d | 1334 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1335 | } |
8f37961c TC |
1336 | |
1337 | /* | |
1338 | * Set 'default' x86 topology, this matches default_topology() in that | |
1339 | * it has NUMA nodes as a topology level. See also | |
1340 | * native_smp_cpus_done(). | |
1341 | * | |
1342 | * Must be done before set_cpus_sibling_map() is ran. | |
1343 | */ | |
1344 | set_sched_topology(x86_topology); | |
1345 | ||
8aef135c | 1346 | set_cpu_sibling_map(0); |
41ea6672 | 1347 | init_freq_invariance(false, false); |
4f45ed9f DL |
1348 | smp_sanity_check(); |
1349 | ||
1350 | switch (apic_intr_mode) { | |
1351 | case APIC_PIC: | |
1352 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
613c25ef TG |
1353 | disable_smp(); |
1354 | return; | |
4f45ed9f | 1355 | case APIC_SYMMETRIC_IO_NO_ROUTING: |
613c25ef | 1356 | disable_smp(); |
a2510d15 DL |
1357 | /* Setup local timer */ |
1358 | x86_init.timers.setup_percpu_clockev(); | |
250a1ac6 | 1359 | return; |
4f45ed9f DL |
1360 | case APIC_VIRTUAL_WIRE: |
1361 | case APIC_SYMMETRIC_IO: | |
613c25ef | 1362 | break; |
8aef135c GOC |
1363 | } |
1364 | ||
a2510d15 DL |
1365 | /* Setup local timer */ |
1366 | x86_init.timers.setup_percpu_clockev(); | |
8aef135c | 1367 | |
4b1244b4 | 1368 | smp_get_logical_apicid(); |
ef4c59a4 | 1369 | |
d54ff31d | 1370 | pr_info("CPU0: "); |
8aef135c | 1371 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1372 | |
9ec808a0 | 1373 | uv_system_init(); |
d0af9eed SS |
1374 | |
1375 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1376 | |
1377 | smp_quirk_init_udelay(); | |
1f50ddb4 TG |
1378 | |
1379 | speculative_store_bypass_ht_init(); | |
8aef135c | 1380 | } |
d0af9eed | 1381 | |
56555855 | 1382 | void arch_thaw_secondary_cpus_begin(void) |
d0af9eed SS |
1383 | { |
1384 | set_mtrr_aps_delayed_init(); | |
1385 | } | |
1386 | ||
56555855 | 1387 | void arch_thaw_secondary_cpus_end(void) |
d0af9eed SS |
1388 | { |
1389 | mtrr_aps_init(); | |
1390 | } | |
1391 | ||
a8db8453 GOC |
1392 | /* |
1393 | * Early setup to make printk work. | |
1394 | */ | |
1395 | void __init native_smp_prepare_boot_cpu(void) | |
1396 | { | |
1397 | int me = smp_processor_id(); | |
552be871 | 1398 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1399 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1400 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1401 | cpu_set_state_online(me); |
090d54bc | 1402 | native_pv_lock_init(); |
a8db8453 GOC |
1403 | } |
1404 | ||
63e708f8 | 1405 | void __init calculate_max_logical_packages(void) |
83f7eb9c | 1406 | { |
b4c0a732 PB |
1407 | int ncpus; |
1408 | ||
b4c0a732 PB |
1409 | /* |
1410 | * Today neither Intel nor AMD support heterogenous systems so | |
1411 | * extrapolate the boot cpu's data to all packages. | |
1412 | */ | |
947134d9 | 1413 | ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); |
aa02ef09 | 1414 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
b4c0a732 | 1415 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
63e708f8 PB |
1416 | } |
1417 | ||
1418 | void __init native_smp_cpus_done(unsigned int max_cpus) | |
1419 | { | |
1420 | pr_debug("Boot done\n"); | |
1421 | ||
1422 | calculate_max_logical_packages(); | |
83f7eb9c | 1423 | |
8f37961c TC |
1424 | if (x86_has_numa_in_package) |
1425 | set_sched_topology(x86_numa_in_package_topology); | |
1426 | ||
99e8b9ca | 1427 | nmi_selftest(); |
83f7eb9c | 1428 | impress_friends(); |
d0af9eed | 1429 | mtrr_aps_init(); |
83f7eb9c GOC |
1430 | } |
1431 | ||
3b11ce7f MT |
1432 | static int __initdata setup_possible_cpus = -1; |
1433 | static int __init _setup_possible_cpus(char *str) | |
1434 | { | |
1435 | get_option(&str, &setup_possible_cpus); | |
1436 | return 0; | |
1437 | } | |
1438 | early_param("possible_cpus", _setup_possible_cpus); | |
1439 | ||
1440 | ||
68a1c3f8 | 1441 | /* |
4f062896 | 1442 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 | 1443 | * are onlined, or offlined. The reason is per-cpu data-structures |
4d1d0977 | 1444 | * are allocated by some modules at init time, and don't expect to |
68a1c3f8 | 1445 | * do this dynamically on cpu arrival/departure. |
4f062896 | 1446 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1447 | * In case when cpu_hotplug is not compiled, then we resort to current |
1448 | * behaviour, which is cpu_possible == cpu_present. | |
1449 | * - Ashok Raj | |
1450 | * | |
1451 | * Three ways to find out the number of additional hotplug CPUs: | |
1452 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1453 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1454 | * - Otherwise don't reserve additional CPUs. |
1455 | * We do this because additional CPUs waste a lot of memory. | |
1456 | * -AK | |
1457 | */ | |
1458 | __init void prefill_possible_map(void) | |
1459 | { | |
cb48bb59 | 1460 | int i, possible; |
68a1c3f8 | 1461 | |
2a51fe08 PB |
1462 | /* No boot processor was found in mptable or ACPI MADT */ |
1463 | if (!num_processors) { | |
ff856051 VS |
1464 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1465 | int apicid = boot_cpu_physical_apicid; | |
1466 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1467 | |
ff856051 | 1468 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1469 | |
ff856051 VS |
1470 | /* Make sure boot cpu is enumerated */ |
1471 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1472 | apic->apic_id_valid(apicid)) | |
1473 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1474 | } | |
2a51fe08 PB |
1475 | |
1476 | if (!num_processors) | |
1477 | num_processors = 1; | |
1478 | } | |
329513a3 | 1479 | |
5f2eb550 JB |
1480 | i = setup_max_cpus ?: 1; |
1481 | if (setup_possible_cpus == -1) { | |
1482 | possible = num_processors; | |
1483 | #ifdef CONFIG_HOTPLUG_CPU | |
1484 | if (setup_max_cpus) | |
1485 | possible += disabled_cpus; | |
1486 | #else | |
1487 | if (possible > i) | |
1488 | possible = i; | |
1489 | #endif | |
1490 | } else | |
3b11ce7f MT |
1491 | possible = setup_possible_cpus; |
1492 | ||
730cf272 MT |
1493 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1494 | ||
2b633e3f YL |
1495 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1496 | if (possible > nr_cpu_ids) { | |
9b130ad5 | 1497 | pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", |
2b633e3f YL |
1498 | possible, nr_cpu_ids); |
1499 | possible = nr_cpu_ids; | |
3b11ce7f | 1500 | } |
68a1c3f8 | 1501 | |
5f2eb550 JB |
1502 | #ifdef CONFIG_HOTPLUG_CPU |
1503 | if (!setup_max_cpus) | |
1504 | #endif | |
1505 | if (possible > i) { | |
c767a54b | 1506 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1507 | possible, setup_max_cpus); |
1508 | possible = i; | |
1509 | } | |
1510 | ||
427d77a3 TG |
1511 | nr_cpu_ids = possible; |
1512 | ||
c767a54b | 1513 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1514 | possible, max_t(int, possible - num_processors, 0)); |
1515 | ||
427d77a3 TG |
1516 | reset_cpu_possible_mask(); |
1517 | ||
68a1c3f8 | 1518 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1519 | set_cpu_possible(i, true); |
68a1c3f8 | 1520 | } |
69c18c15 | 1521 | |
14adf855 CE |
1522 | #ifdef CONFIG_HOTPLUG_CPU |
1523 | ||
70b8301f AK |
1524 | /* Recompute SMT state for all CPUs on offline */ |
1525 | static void recompute_smt_state(void) | |
1526 | { | |
1527 | int max_threads, cpu; | |
1528 | ||
1529 | max_threads = 0; | |
1530 | for_each_online_cpu (cpu) { | |
1531 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1532 | ||
1533 | if (threads > max_threads) | |
1534 | max_threads = threads; | |
1535 | } | |
1536 | __max_smt_threads = max_threads; | |
1537 | } | |
1538 | ||
14adf855 CE |
1539 | static void remove_siblinginfo(int cpu) |
1540 | { | |
1541 | int sibling; | |
1542 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1543 | ||
7d79a7bd BG |
1544 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1545 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1546 | /*/ |
1547 | * last thread sibling in this cpu core going down | |
1548 | */ | |
7d79a7bd | 1549 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1550 | cpu_data(sibling).booted_cores--; |
1551 | } | |
1552 | ||
2e4c54da LB |
1553 | for_each_cpu(sibling, topology_die_cpumask(cpu)) |
1554 | cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); | |
7d79a7bd BG |
1555 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1556 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1557 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1558 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1559 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1560 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1561 | cpumask_clear(topology_core_cpumask(cpu)); | |
2e4c54da | 1562 | cpumask_clear(topology_die_cpumask(cpu)); |
14adf855 | 1563 | c->cpu_core_id = 0; |
45967493 | 1564 | c->booted_cores = 0; |
c2d1cec1 | 1565 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1566 | recompute_smt_state(); |
14adf855 CE |
1567 | } |
1568 | ||
4daa832d | 1569 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1570 | { |
c2d1cec1 MT |
1571 | set_cpu_online(cpu, false); |
1572 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1573 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1574 | /* was set by cpu_init() */ |
c2d1cec1 | 1575 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1576 | numa_remove_cpu(cpu); |
69c18c15 GC |
1577 | } |
1578 | ||
8227dce7 | 1579 | void cpu_disable_common(void) |
69c18c15 GC |
1580 | { |
1581 | int cpu = smp_processor_id(); | |
69c18c15 | 1582 | |
69c18c15 GC |
1583 | remove_siblinginfo(cpu); |
1584 | ||
1585 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1586 | lock_vector_lock(); |
69c18c15 | 1587 | remove_cpu_from_maps(cpu); |
d388e5fd | 1588 | unlock_vector_lock(); |
d7b381bb | 1589 | fixup_irqs(); |
0fa115da | 1590 | lapic_offline(); |
8227dce7 AN |
1591 | } |
1592 | ||
1593 | int native_cpu_disable(void) | |
1594 | { | |
da6139e4 PB |
1595 | int ret; |
1596 | ||
2cffad7b | 1597 | ret = lapic_can_unplug_cpu(); |
da6139e4 PB |
1598 | if (ret) |
1599 | return ret; | |
1600 | ||
8227dce7 | 1601 | cpu_disable_common(); |
2ed53c0d | 1602 | |
52d6b926 AR |
1603 | /* |
1604 | * Disable the local APIC. Otherwise IPI broadcasts will reach | |
1605 | * it. It still responds normally to INIT, NMI, SMI, and SIPI | |
1606 | * messages. | |
1607 | * | |
1608 | * Disabling the APIC must happen after cpu_disable_common() | |
1609 | * which invokes fixup_irqs(). | |
1610 | * | |
1611 | * Disabling the APIC preserves already set bits in IRR, but | |
1612 | * an interrupt arriving after disabling the local APIC does not | |
1613 | * set the corresponding IRR bit. | |
1614 | * | |
1615 | * fixup_irqs() scans IRR for set bits so it can raise a not | |
1616 | * yet handled interrupt on the new destination CPU via an IPI | |
1617 | * but obviously it can't do so for IRR bits which are not set. | |
1618 | * IOW, interrupts arriving after disabling the local APIC will | |
1619 | * be lost. | |
1620 | */ | |
1621 | apic_soft_disable(); | |
1622 | ||
69c18c15 GC |
1623 | return 0; |
1624 | } | |
1625 | ||
2a442c9c | 1626 | int common_cpu_die(unsigned int cpu) |
54279552 | 1627 | { |
2a442c9c | 1628 | int ret = 0; |
54279552 | 1629 | |
69c18c15 | 1630 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1631 | |
2ed53c0d | 1632 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1633 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1634 | if (system_state == SYSTEM_RUNNING) |
1635 | pr_info("CPU %u is now offline\n", cpu); | |
1636 | } else { | |
1637 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1638 | ret = -1; |
69c18c15 | 1639 | } |
2a442c9c PM |
1640 | |
1641 | return ret; | |
1642 | } | |
1643 | ||
1644 | void native_cpu_die(unsigned int cpu) | |
1645 | { | |
1646 | common_cpu_die(cpu); | |
69c18c15 | 1647 | } |
a21f5d88 AN |
1648 | |
1649 | void play_dead_common(void) | |
1650 | { | |
1651 | idle_task_exit(); | |
a21f5d88 | 1652 | |
a21f5d88 | 1653 | /* Ack it */ |
2a442c9c | 1654 | (void)cpu_report_death(); |
a21f5d88 AN |
1655 | |
1656 | /* | |
1657 | * With physical CPU hotplug, we should halt the cpu | |
1658 | */ | |
1659 | local_irq_disable(); | |
1660 | } | |
1661 | ||
fae1cb57 | 1662 | bool wakeup_cpu0(void) |
e1c467e6 FY |
1663 | { |
1664 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1665 | return true; | |
1666 | ||
1667 | return false; | |
1668 | } | |
1669 | ||
ea530692 PA |
1670 | /* |
1671 | * We need to flush the caches before going to sleep, lest we have | |
1672 | * dirty data in our caches when we come back up. | |
1673 | */ | |
1674 | static inline void mwait_play_dead(void) | |
1675 | { | |
1676 | unsigned int eax, ebx, ecx, edx; | |
1677 | unsigned int highest_cstate = 0; | |
1678 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1679 | void *mwait_ptr; |
576cfb40 | 1680 | int i; |
ea530692 | 1681 | |
0b13bec7 PW |
1682 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
1683 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) | |
da6fa7ef | 1684 | return; |
69fb3676 | 1685 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1686 | return; |
840d2830 | 1687 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1688 | return; |
7b543a53 | 1689 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1690 | return; |
1691 | ||
1692 | eax = CPUID_MWAIT_LEAF; | |
1693 | ecx = 0; | |
1694 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1695 | ||
1696 | /* | |
1697 | * eax will be 0 if EDX enumeration is not valid. | |
1698 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1699 | */ | |
1700 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1701 | eax = 0; | |
1702 | } else { | |
1703 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1704 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1705 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1706 | highest_cstate = i; | |
1707 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1708 | } | |
1709 | } | |
1710 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1711 | (highest_subcstate - 1); | |
1712 | } | |
1713 | ||
ce5f6824 PA |
1714 | /* |
1715 | * This should be a memory location in a cache line which is | |
1716 | * unlikely to be touched by other processors. The actual | |
1717 | * content is immaterial as it is not actually modified in any way. | |
1718 | */ | |
1719 | mwait_ptr = ¤t_thread_info()->flags; | |
1720 | ||
a68e5c94 PA |
1721 | wbinvd(); |
1722 | ||
ea530692 | 1723 | while (1) { |
ce5f6824 PA |
1724 | /* |
1725 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1726 | * the Xeon 7400 series. It's not clear it is actually | |
1727 | * needed, but it should be harmless in either case. | |
1728 | * The WBINVD is insufficient due to the spurious-wakeup | |
1729 | * case where we return around the loop. | |
1730 | */ | |
7d590cca | 1731 | mb(); |
ce5f6824 | 1732 | clflush(mwait_ptr); |
7d590cca | 1733 | mb(); |
ce5f6824 | 1734 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1735 | mb(); |
1736 | __mwait(eax, 0); | |
e1c467e6 FY |
1737 | /* |
1738 | * If NMI wants to wake up CPU0, start CPU0. | |
1739 | */ | |
1740 | if (wakeup_cpu0()) | |
1741 | start_cpu0(); | |
ea530692 PA |
1742 | } |
1743 | } | |
1744 | ||
406f992e | 1745 | void hlt_play_dead(void) |
ea530692 | 1746 | { |
7b543a53 | 1747 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1748 | wbinvd(); |
1749 | ||
ea530692 | 1750 | while (1) { |
ea530692 | 1751 | native_halt(); |
e1c467e6 FY |
1752 | /* |
1753 | * If NMI wants to wake up CPU0, start CPU0. | |
1754 | */ | |
1755 | if (wakeup_cpu0()) | |
1756 | start_cpu0(); | |
ea530692 PA |
1757 | } |
1758 | } | |
1759 | ||
a21f5d88 AN |
1760 | void native_play_dead(void) |
1761 | { | |
1762 | play_dead_common(); | |
86886e55 | 1763 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1764 | |
1765 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1766 | if (cpuidle_play_dead()) |
1767 | hlt_play_dead(); | |
a21f5d88 AN |
1768 | } |
1769 | ||
69c18c15 | 1770 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1771 | int native_cpu_disable(void) |
69c18c15 GC |
1772 | { |
1773 | return -ENOSYS; | |
1774 | } | |
1775 | ||
93be71b6 | 1776 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1777 | { |
1778 | /* We said "no" in __cpu_disable */ | |
1779 | BUG(); | |
1780 | } | |
a21f5d88 AN |
1781 | |
1782 | void native_play_dead(void) | |
1783 | { | |
1784 | BUG(); | |
1785 | } | |
1786 | ||
68a1c3f8 | 1787 | #endif |
1567c3e3 | 1788 | |
e2b0d619 | 1789 | #ifdef CONFIG_X86_64 |
1567c3e3 GG |
1790 | /* |
1791 | * APERF/MPERF frequency ratio computation. | |
1792 | * | |
1793 | * The scheduler wants to do frequency invariant accounting and needs a <1 | |
1794 | * ratio to account for the 'current' frequency, corresponding to | |
1795 | * freq_curr / freq_max. | |
1796 | * | |
1797 | * Since the frequency freq_curr on x86 is controlled by micro-controller and | |
1798 | * our P-state setting is little more than a request/hint, we need to observe | |
1799 | * the effective frequency 'BusyMHz', i.e. the average frequency over a time | |
1800 | * interval after discarding idle time. This is given by: | |
1801 | * | |
1802 | * BusyMHz = delta_APERF / delta_MPERF * freq_base | |
1803 | * | |
1804 | * where freq_base is the max non-turbo P-state. | |
1805 | * | |
1806 | * The freq_max term has to be set to a somewhat arbitrary value, because we | |
1807 | * can't know which turbo states will be available at a given point in time: | |
1808 | * it all depends on the thermal headroom of the entire package. We set it to | |
1809 | * the turbo level with 4 cores active. | |
1810 | * | |
1811 | * Benchmarks show that's a good compromise between the 1C turbo ratio | |
1812 | * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, | |
1813 | * which would ignore the entire turbo range (a conspicuous part, making | |
1814 | * freq_curr/freq_max always maxed out). | |
1815 | * | |
eacf0474 GG |
1816 | * An exception to the heuristic above is the Atom uarch, where we choose the |
1817 | * highest turbo level for freq_max since Atom's are generally oriented towards | |
1818 | * power efficiency. | |
1819 | * | |
1567c3e3 GG |
1820 | * Setting freq_max to anything less than the 1C turbo ratio makes the ratio |
1821 | * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. | |
1822 | */ | |
1823 | ||
1824 | DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); | |
1825 | ||
1826 | static DEFINE_PER_CPU(u64, arch_prev_aperf); | |
1827 | static DEFINE_PER_CPU(u64, arch_prev_mperf); | |
918229cd | 1828 | static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; |
1567c3e3 GG |
1829 | static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; |
1830 | ||
918229cd GG |
1831 | void arch_set_max_freq_ratio(bool turbo_disabled) |
1832 | { | |
1833 | arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : | |
1834 | arch_turbo_freq_ratio; | |
1835 | } | |
d11a1d08 | 1836 | EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio); |
918229cd | 1837 | |
1567c3e3 GG |
1838 | static bool turbo_disabled(void) |
1839 | { | |
1840 | u64 misc_en; | |
1841 | int err; | |
1842 | ||
1843 | err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); | |
1844 | if (err) | |
1845 | return false; | |
1846 | ||
1847 | return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
1848 | } | |
1849 | ||
298c6f99 GG |
1850 | static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) |
1851 | { | |
1852 | int err; | |
1853 | ||
1854 | err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); | |
1855 | if (err) | |
1856 | return false; | |
1857 | ||
1858 | err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); | |
1859 | if (err) | |
1860 | return false; | |
1861 | ||
1862 | *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ | |
1863 | *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ | |
1864 | ||
1865 | return true; | |
1866 | } | |
1867 | ||
1567c3e3 GG |
1868 | #include <asm/cpu_device_id.h> |
1869 | #include <asm/intel-family.h> | |
1870 | ||
2fa9a3cf BP |
1871 | #define X86_MATCH(model) \ |
1872 | X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ | |
1873 | INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) | |
1567c3e3 GG |
1874 | |
1875 | static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { | |
2fa9a3cf BP |
1876 | X86_MATCH(XEON_PHI_KNL), |
1877 | X86_MATCH(XEON_PHI_KNM), | |
1567c3e3 GG |
1878 | {} |
1879 | }; | |
1880 | ||
1881 | static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { | |
2fa9a3cf | 1882 | X86_MATCH(SKYLAKE_X), |
1567c3e3 GG |
1883 | {} |
1884 | }; | |
1885 | ||
1886 | static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { | |
2fa9a3cf BP |
1887 | X86_MATCH(ATOM_GOLDMONT), |
1888 | X86_MATCH(ATOM_GOLDMONT_D), | |
1889 | X86_MATCH(ATOM_GOLDMONT_PLUS), | |
1567c3e3 GG |
1890 | {} |
1891 | }; | |
1892 | ||
8bea0dfb GG |
1893 | static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, |
1894 | int num_delta_fratio) | |
1895 | { | |
1896 | int fratio, delta_fratio, found; | |
1897 | int err, i; | |
1898 | u64 msr; | |
1899 | ||
8bea0dfb GG |
1900 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); |
1901 | if (err) | |
1902 | return false; | |
1903 | ||
1904 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ | |
1905 | ||
1906 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); | |
1907 | if (err) | |
1908 | return false; | |
1909 | ||
1910 | fratio = (msr >> 8) & 0xFF; | |
1911 | i = 16; | |
1912 | found = 0; | |
1913 | do { | |
1914 | if (found >= num_delta_fratio) { | |
1915 | *turbo_freq = fratio; | |
1916 | return true; | |
1917 | } | |
1918 | ||
1919 | delta_fratio = (msr >> (i + 5)) & 0x7; | |
1920 | ||
1921 | if (delta_fratio) { | |
1922 | found += 1; | |
1923 | fratio -= delta_fratio; | |
1924 | } | |
1925 | ||
1926 | i += 8; | |
1927 | } while (i < 64); | |
1928 | ||
1929 | return true; | |
1930 | } | |
1931 | ||
2a0abc59 GG |
1932 | static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) |
1933 | { | |
1934 | u64 ratios, counts; | |
1935 | u32 group_size; | |
1936 | int err, i; | |
1937 | ||
1938 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); | |
1939 | if (err) | |
1940 | return false; | |
1941 | ||
1942 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ | |
1943 | ||
1944 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); | |
1945 | if (err) | |
1946 | return false; | |
1947 | ||
1948 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); | |
1949 | if (err) | |
1950 | return false; | |
1951 | ||
1952 | for (i = 0; i < 64; i += 8) { | |
1953 | group_size = (counts >> i) & 0xFF; | |
1954 | if (group_size >= size) { | |
1955 | *turbo_freq = (ratios >> i) & 0xFF; | |
1956 | return true; | |
1957 | } | |
1958 | } | |
1959 | ||
1960 | return false; | |
1961 | } | |
1962 | ||
1963 | static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) | |
1567c3e3 | 1964 | { |
23ccee22 | 1965 | u64 msr; |
1567c3e3 GG |
1966 | int err; |
1967 | ||
2a0abc59 | 1968 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); |
1567c3e3 GG |
1969 | if (err) |
1970 | return false; | |
1971 | ||
23ccee22 | 1972 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); |
1567c3e3 GG |
1973 | if (err) |
1974 | return false; | |
1975 | ||
23ccee22 GG |
1976 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ |
1977 | *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */ | |
1978 | ||
1979 | /* The CPU may have less than 4 cores */ | |
1980 | if (!*turbo_freq) | |
1981 | *turbo_freq = msr & 0xFF; /* 1C turbo */ | |
1567c3e3 | 1982 | |
1567c3e3 GG |
1983 | return true; |
1984 | } | |
1985 | ||
1986 | static bool intel_set_max_freq_ratio(void) | |
1987 | { | |
918229cd | 1988 | u64 base_freq, turbo_freq; |
f4291df1 | 1989 | u64 turbo_ratio; |
2a0abc59 | 1990 | |
298c6f99 GG |
1991 | if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) |
1992 | goto out; | |
1993 | ||
eacf0474 GG |
1994 | if (x86_match_cpu(has_glm_turbo_ratio_limits) && |
1995 | skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) | |
1996 | goto out; | |
1997 | ||
db441bd9 GG |
1998 | if (x86_match_cpu(has_knl_turbo_ratio_limits) && |
1999 | knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) | |
8bea0dfb GG |
2000 | goto out; |
2001 | ||
2a0abc59 GG |
2002 | if (x86_match_cpu(has_skx_turbo_ratio_limits) && |
2003 | skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) | |
2004 | goto out; | |
2005 | ||
2006 | if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) | |
2007 | goto out; | |
1567c3e3 GG |
2008 | |
2009 | return false; | |
2a0abc59 GG |
2010 | |
2011 | out: | |
9a6c2c3c GG |
2012 | /* |
2013 | * Some hypervisors advertise X86_FEATURE_APERFMPERF | |
2014 | * but then fill all MSR's with zeroes. | |
51beea88 GG |
2015 | * Some CPUs have turbo boost but don't declare any turbo ratio |
2016 | * in MSR_TURBO_RATIO_LIMIT. | |
9a6c2c3c | 2017 | */ |
51beea88 GG |
2018 | if (!base_freq || !turbo_freq) { |
2019 | pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n"); | |
9a6c2c3c GG |
2020 | return false; |
2021 | } | |
2022 | ||
f4291df1 GG |
2023 | turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq); |
2024 | if (!turbo_ratio) { | |
2025 | pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n"); | |
2026 | return false; | |
2027 | } | |
2028 | ||
2029 | arch_turbo_freq_ratio = turbo_ratio; | |
918229cd | 2030 | arch_set_max_freq_ratio(turbo_disabled()); |
f4291df1 | 2031 | |
2a0abc59 | 2032 | return true; |
1567c3e3 GG |
2033 | } |
2034 | ||
41ea6672 NF |
2035 | #ifdef CONFIG_ACPI_CPPC_LIB |
2036 | static bool amd_set_max_freq_ratio(void) | |
2037 | { | |
2038 | struct cppc_perf_caps perf_caps; | |
2039 | u64 highest_perf, nominal_perf; | |
2040 | u64 perf_ratio; | |
2041 | int rc; | |
2042 | ||
2043 | rc = cppc_get_perf_caps(0, &perf_caps); | |
2044 | if (rc) { | |
2045 | pr_debug("Could not retrieve perf counters (%d)\n", rc); | |
2046 | return false; | |
2047 | } | |
2048 | ||
2049 | highest_perf = perf_caps.highest_perf; | |
2050 | nominal_perf = perf_caps.nominal_perf; | |
2051 | ||
2052 | if (!highest_perf || !nominal_perf) { | |
2053 | pr_debug("Could not retrieve highest or nominal performance\n"); | |
2054 | return false; | |
2055 | } | |
2056 | ||
2057 | perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf); | |
976df7e5 GG |
2058 | /* midpoint between max_boost and max_P */ |
2059 | perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1; | |
41ea6672 NF |
2060 | if (!perf_ratio) { |
2061 | pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n"); | |
2062 | return false; | |
2063 | } | |
2064 | ||
2065 | arch_turbo_freq_ratio = perf_ratio; | |
2066 | arch_set_max_freq_ratio(false); | |
2067 | ||
2068 | return true; | |
2069 | } | |
2070 | #else | |
2071 | static bool amd_set_max_freq_ratio(void) | |
2072 | { | |
2073 | return false; | |
2074 | } | |
2075 | #endif | |
2076 | ||
b56e7d45 | 2077 | static void init_counter_refs(void) |
1567c3e3 GG |
2078 | { |
2079 | u64 aperf, mperf; | |
2080 | ||
2081 | rdmsrl(MSR_IA32_APERF, aperf); | |
2082 | rdmsrl(MSR_IA32_MPERF, mperf); | |
2083 | ||
2084 | this_cpu_write(arch_prev_aperf, aperf); | |
2085 | this_cpu_write(arch_prev_mperf, mperf); | |
2086 | } | |
2087 | ||
9c7d9017 RW |
2088 | #ifdef CONFIG_PM_SLEEP |
2089 | static struct syscore_ops freq_invariance_syscore_ops = { | |
2090 | .resume = init_counter_refs, | |
2091 | }; | |
2092 | ||
2093 | static void register_freq_invariance_syscore_ops(void) | |
2094 | { | |
2095 | /* Bail out if registered already. */ | |
2096 | if (freq_invariance_syscore_ops.node.prev) | |
2097 | return; | |
2098 | ||
2099 | register_syscore_ops(&freq_invariance_syscore_ops); | |
2100 | } | |
2101 | #else | |
2102 | static inline void register_freq_invariance_syscore_ops(void) {} | |
2103 | #endif | |
2104 | ||
41ea6672 | 2105 | static void init_freq_invariance(bool secondary, bool cppc_ready) |
1567c3e3 GG |
2106 | { |
2107 | bool ret = false; | |
2108 | ||
b56e7d45 | 2109 | if (!boot_cpu_has(X86_FEATURE_APERFMPERF)) |
1567c3e3 GG |
2110 | return; |
2111 | ||
b56e7d45 PZI |
2112 | if (secondary) { |
2113 | if (static_branch_likely(&arch_scale_freq_key)) { | |
2114 | init_counter_refs(); | |
2115 | } | |
2116 | return; | |
2117 | } | |
2118 | ||
1567c3e3 GG |
2119 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2120 | ret = intel_set_max_freq_ratio(); | |
41ea6672 NF |
2121 | else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { |
2122 | if (!cppc_ready) { | |
2123 | return; | |
2124 | } | |
2125 | ret = amd_set_max_freq_ratio(); | |
2126 | } | |
1567c3e3 GG |
2127 | |
2128 | if (ret) { | |
b56e7d45 | 2129 | init_counter_refs(); |
1567c3e3 | 2130 | static_branch_enable(&arch_scale_freq_key); |
9c7d9017 | 2131 | register_freq_invariance_syscore_ops(); |
3149cd55 | 2132 | pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); |
1567c3e3 GG |
2133 | } else { |
2134 | pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); | |
2135 | } | |
2136 | } | |
2137 | ||
41ea6672 NF |
2138 | #ifdef CONFIG_ACPI_CPPC_LIB |
2139 | static DEFINE_MUTEX(freq_invariance_lock); | |
2140 | ||
2141 | void init_freq_invariance_cppc(void) | |
2142 | { | |
2143 | static bool secondary; | |
2144 | ||
2145 | mutex_lock(&freq_invariance_lock); | |
2146 | ||
2147 | init_freq_invariance(secondary, true); | |
2148 | secondary = true; | |
2149 | ||
2150 | mutex_unlock(&freq_invariance_lock); | |
2151 | } | |
2152 | #endif | |
2153 | ||
e2b0d619 GG |
2154 | static void disable_freq_invariance_workfn(struct work_struct *work) |
2155 | { | |
2156 | static_branch_disable(&arch_scale_freq_key); | |
2157 | } | |
2158 | ||
2159 | static DECLARE_WORK(disable_freq_invariance_work, | |
2160 | disable_freq_invariance_workfn); | |
2161 | ||
1567c3e3 GG |
2162 | DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; |
2163 | ||
2164 | void arch_scale_freq_tick(void) | |
2165 | { | |
e2b0d619 | 2166 | u64 freq_scale = SCHED_CAPACITY_SCALE; |
1567c3e3 GG |
2167 | u64 aperf, mperf; |
2168 | u64 acnt, mcnt; | |
2169 | ||
2170 | if (!arch_scale_freq_invariant()) | |
2171 | return; | |
2172 | ||
2173 | rdmsrl(MSR_IA32_APERF, aperf); | |
2174 | rdmsrl(MSR_IA32_MPERF, mperf); | |
2175 | ||
2176 | acnt = aperf - this_cpu_read(arch_prev_aperf); | |
2177 | mcnt = mperf - this_cpu_read(arch_prev_mperf); | |
1567c3e3 GG |
2178 | |
2179 | this_cpu_write(arch_prev_aperf, aperf); | |
2180 | this_cpu_write(arch_prev_mperf, mperf); | |
2181 | ||
e2b0d619 GG |
2182 | if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt)) |
2183 | goto error; | |
2184 | ||
2185 | if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt) | |
2186 | goto error; | |
1567c3e3 GG |
2187 | |
2188 | freq_scale = div64_u64(acnt, mcnt); | |
e2b0d619 GG |
2189 | if (!freq_scale) |
2190 | goto error; | |
1567c3e3 GG |
2191 | |
2192 | if (freq_scale > SCHED_CAPACITY_SCALE) | |
2193 | freq_scale = SCHED_CAPACITY_SCALE; | |
2194 | ||
2195 | this_cpu_write(arch_freq_scale, freq_scale); | |
e2b0d619 GG |
2196 | return; |
2197 | ||
2198 | error: | |
2199 | pr_warn("Scheduler frequency invariance went wobbly, disabling!\n"); | |
2200 | schedule_work(&disable_freq_invariance_work); | |
2201 | } | |
2202 | #else | |
41ea6672 | 2203 | static inline void init_freq_invariance(bool secondary, bool cppc_ready) |
e2b0d619 | 2204 | { |
1567c3e3 | 2205 | } |
e2b0d619 | 2206 | #endif /* CONFIG_X86_64 */ |