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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
186f4360 | 46 | #include <linux/export.h> |
70708a18 | 47 | #include <linux/sched.h> |
105ab3d8 | 48 | #include <linux/sched/topology.h> |
ef8bd77f | 49 | #include <linux/sched/hotplug.h> |
68db0cf1 | 50 | #include <linux/sched/task_stack.h> |
69c18c15 | 51 | #include <linux/percpu.h> |
91718e8d | 52 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
53 | #include <linux/err.h> |
54 | #include <linux/nmi.h> | |
69575d38 | 55 | #include <linux/tboot.h> |
35f720c5 | 56 | #include <linux/stackprotector.h> |
5a0e3ad6 | 57 | #include <linux/gfp.h> |
1a022e3f | 58 | #include <linux/cpuidle.h> |
69c18c15 | 59 | |
8aef135c | 60 | #include <asm/acpi.h> |
cb3c8b90 | 61 | #include <asm/desc.h> |
69c18c15 GC |
62 | #include <asm/nmi.h> |
63 | #include <asm/irq.h> | |
48927bbb | 64 | #include <asm/realmode.h> |
69c18c15 GC |
65 | #include <asm/cpu.h> |
66 | #include <asm/numa.h> | |
cb3c8b90 GOC |
67 | #include <asm/pgtable.h> |
68 | #include <asm/tlbflush.h> | |
69 | #include <asm/mtrr.h> | |
ea530692 | 70 | #include <asm/mwait.h> |
7b6aa335 | 71 | #include <asm/apic.h> |
7167d08e | 72 | #include <asm/io_apic.h> |
78f7f1e5 | 73 | #include <asm/fpu/internal.h> |
569712b2 | 74 | #include <asm/setup.h> |
bdbcdd48 | 75 | #include <asm/uv/uv.h> |
cb3c8b90 | 76 | #include <linux/mc146818rtc.h> |
b81bb373 | 77 | #include <asm/i8259.h> |
48927bbb | 78 | #include <asm/realmode.h> |
646e29a1 | 79 | #include <asm/misc.h> |
9043442b | 80 | #include <asm/qspinlock.h> |
3f6a3b03 | 81 | #include <asm/spec-ctrl.h> |
f901f138 | 82 | #include <asm/hw_irq.h> |
48927bbb | 83 | |
a355352b | 84 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 85 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
86 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
87 | ||
88 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 89 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
90 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
91 | ||
0816b0f0 | 92 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 93 | |
a355352b | 94 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 95 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 96 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 97 | |
1f12e32f | 98 | /* Logical package management. We might want to allocate that dynamically */ |
1f12e32f TG |
99 | unsigned int __max_logical_packages __read_mostly; |
100 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 101 | static unsigned int logical_packages __read_mostly; |
1f12e32f | 102 | |
70b8301f | 103 | /* Maximum number of SMT threads on any online core */ |
947134d9 | 104 | int __read_mostly __max_smt_threads = 1; |
70b8301f | 105 | |
7d25127c TC |
106 | /* Flag to indicate if a complete sched domain rebuild is required */ |
107 | bool x86_topology_update; | |
108 | ||
109 | int arch_update_cpu_topology(void) | |
110 | { | |
111 | int retval = x86_topology_update; | |
112 | ||
113 | x86_topology_update = false; | |
114 | return retval; | |
115 | } | |
116 | ||
f77aa308 TG |
117 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
118 | { | |
119 | unsigned long flags; | |
120 | ||
121 | spin_lock_irqsave(&rtc_lock, flags); | |
122 | CMOS_WRITE(0xa, 0xf); | |
123 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
124 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
125 | start_eip >> 4; | |
f77aa308 TG |
126 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
127 | start_eip & 0xf; | |
f77aa308 TG |
128 | } |
129 | ||
130 | static inline void smpboot_restore_warm_reset_vector(void) | |
131 | { | |
132 | unsigned long flags; | |
133 | ||
f77aa308 TG |
134 | /* |
135 | * Paranoid: Set warm reset code and vector here back | |
136 | * to default values. | |
137 | */ | |
138 | spin_lock_irqsave(&rtc_lock, flags); | |
139 | CMOS_WRITE(0, 0xf); | |
140 | spin_unlock_irqrestore(&rtc_lock, flags); | |
141 | ||
142 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
143 | } | |
144 | ||
cb3c8b90 | 145 | /* |
30106c17 FY |
146 | * Report back to the Boot Processor during boot time or to the caller processor |
147 | * during CPU online. | |
cb3c8b90 | 148 | */ |
148f9bb8 | 149 | static void smp_callin(void) |
cb3c8b90 GOC |
150 | { |
151 | int cpuid, phys_id; | |
cb3c8b90 GOC |
152 | |
153 | /* | |
154 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
155 | * cpu_callout_mask guarantees we don't get here before |
156 | * an INIT_deassert IPI reaches our local APIC, so it is | |
157 | * now safe to touch our local APIC. | |
cb3c8b90 | 158 | */ |
e1c467e6 | 159 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
160 | |
161 | /* | |
162 | * (This works even if the APIC is not enabled.) | |
163 | */ | |
4c9961d5 | 164 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
165 | |
166 | /* | |
167 | * the boot CPU has finished the init stage and is spinning | |
168 | * on callin_map until we finish. We are free to set up this | |
169 | * CPU, first the APIC. (this is probably redundant on most | |
170 | * boards) | |
171 | */ | |
05f7e46d | 172 | apic_ap_setup(); |
cb3c8b90 | 173 | |
b565201c JS |
174 | /* |
175 | * Save our processor parameters. Note: this information | |
176 | * is needed for clock calibration. | |
177 | */ | |
178 | smp_store_cpu_info(cpuid); | |
179 | ||
76ce7cfe PT |
180 | /* |
181 | * The topology information must be up to date before | |
182 | * calibrate_delay() and notify_cpu_starting(). | |
183 | */ | |
184 | set_cpu_sibling_map(raw_smp_processor_id()); | |
185 | ||
cb3c8b90 GOC |
186 | /* |
187 | * Get our bogomips. | |
b565201c JS |
188 | * Update loops_per_jiffy in cpu_data. Previous call to |
189 | * smp_store_cpu_info() stored a value that is close but not as | |
190 | * accurate as the value just calculated. | |
cb3c8b90 | 191 | */ |
cb3c8b90 | 192 | calibrate_delay(); |
b565201c | 193 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 194 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 195 | |
5ef428c4 AK |
196 | wmb(); |
197 | ||
85257024 PZ |
198 | notify_cpu_starting(cpuid); |
199 | ||
cb3c8b90 GOC |
200 | /* |
201 | * Allow the master to continue. | |
202 | */ | |
c2d1cec1 | 203 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
204 | } |
205 | ||
e1c467e6 FY |
206 | static int cpu0_logical_apicid; |
207 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
208 | /* |
209 | * Activate a secondary processor. | |
210 | */ | |
148f9bb8 | 211 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
212 | { |
213 | /* | |
c7ad5ad2 AL |
214 | * Don't put *anything* except direct CPU state initialization |
215 | * before cpu_init(), SMP booting is too fragile that we want to | |
216 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 217 | */ |
c7ad5ad2 AL |
218 | if (boot_cpu_has(X86_FEATURE_PCID)) |
219 | __write_cr4(__read_cr4() | X86_CR4_PCIDE); | |
e1c467e6 | 220 | |
fd89a137 | 221 | #ifdef CONFIG_X86_32 |
b40827fa | 222 | /* switch away from the initial page table */ |
fd89a137 | 223 | load_cr3(swapper_pg_dir); |
b0c8508d ZD |
224 | /* |
225 | * Initialize the CR4 shadow before doing anything that could | |
226 | * try to read it. | |
227 | */ | |
228 | cr4_init_shadow(); | |
fd89a137 JR |
229 | __flush_tlb_all(); |
230 | #endif | |
55d2d0ad | 231 | load_current_idt(); |
4ba55e65 AL |
232 | cpu_init(); |
233 | x86_cpuinit.early_percpu_clock_init(); | |
234 | preempt_disable(); | |
235 | smp_callin(); | |
236 | ||
237 | enable_start_cpu0 = 0; | |
238 | ||
bbc2ff6a GOC |
239 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
240 | barrier(); | |
241 | /* | |
a1652bb8 | 242 | * Check TSC synchronization with the boot CPU: |
bbc2ff6a GOC |
243 | */ |
244 | check_tsc_sync_target(); | |
245 | ||
3f6a3b03 TG |
246 | speculative_store_bypass_ht_init(); |
247 | ||
bbc2ff6a | 248 | /* |
8ed4f3e6 TG |
249 | * Lock vector_lock, set CPU online and bring the vector |
250 | * allocator online. Online must be set with vector_lock held | |
251 | * to prevent a concurrent irq setup/teardown from seeing a | |
252 | * half valid vector space. | |
bbc2ff6a | 253 | */ |
d388e5fd | 254 | lock_vector_lock(); |
c2d1cec1 | 255 | set_cpu_online(smp_processor_id(), true); |
8ed4f3e6 | 256 | lapic_online(); |
d388e5fd | 257 | unlock_vector_lock(); |
2a442c9c | 258 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 259 | x86_platform.nmi_init(); |
bbc2ff6a | 260 | |
0cefa5b9 MS |
261 | /* enable local interrupts */ |
262 | local_irq_enable(); | |
263 | ||
35f720c5 JP |
264 | /* to prevent fake stack check failure in clock setup */ |
265 | boot_init_stack_canary(); | |
0cefa5b9 | 266 | |
736decac | 267 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
268 | |
269 | wmb(); | |
fc6d73d6 | 270 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
271 | } |
272 | ||
b133f8e9 TG |
273 | /** |
274 | * topology_is_primary_thread - Check whether CPU is the primary SMT thread | |
275 | * @cpu: CPU to check | |
276 | */ | |
277 | bool topology_is_primary_thread(unsigned int cpu) | |
278 | { | |
279 | return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); | |
280 | } | |
281 | ||
b6d27ae9 TG |
282 | /** |
283 | * topology_smt_supported - Check whether SMT is supported by the CPUs | |
284 | */ | |
285 | bool topology_smt_supported(void) | |
286 | { | |
287 | return smp_num_siblings > 1; | |
288 | } | |
289 | ||
30bb9811 AK |
290 | /** |
291 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
292 | * | |
293 | * Returns logical package id or -1 if not found | |
294 | */ | |
295 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
296 | { | |
297 | int cpu; | |
298 | ||
299 | for_each_possible_cpu(cpu) { | |
300 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
301 | ||
302 | if (c->initialized && c->phys_proc_id == phys_pkg) | |
303 | return c->logical_proc_id; | |
304 | } | |
305 | return -1; | |
306 | } | |
307 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
308 | ||
9d85eb91 TG |
309 | /** |
310 | * topology_update_package_map - Update the physical to logical package map | |
311 | * @pkg: The physical package id as retrieved via CPUID | |
312 | * @cpu: The cpu for which this is updated | |
313 | */ | |
314 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 315 | { |
30bb9811 | 316 | int new; |
1f12e32f | 317 | |
30bb9811 AK |
318 | /* Already available somewhere? */ |
319 | new = topology_phys_to_logical_pkg(pkg); | |
320 | if (new >= 0) | |
1f12e32f TG |
321 | goto found; |
322 | ||
7b0501b1 | 323 | new = logical_packages++; |
9d85eb91 TG |
324 | if (new != pkg) { |
325 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
326 | cpu, pkg, new); | |
327 | } | |
1f12e32f | 328 | found: |
30bb9811 | 329 | cpu_data(cpu).logical_proc_id = new; |
1f12e32f TG |
330 | return 0; |
331 | } | |
332 | ||
30106c17 FY |
333 | void __init smp_store_boot_cpu_info(void) |
334 | { | |
335 | int id = 0; /* CPU 0 */ | |
336 | struct cpuinfo_x86 *c = &cpu_data(id); | |
337 | ||
338 | *c = boot_cpu_data; | |
339 | c->cpu_index = id; | |
b4c0a732 | 340 | topology_update_package_map(c->phys_proc_id, id); |
30bb9811 | 341 | c->initialized = true; |
30106c17 FY |
342 | } |
343 | ||
1d89a7f0 GOC |
344 | /* |
345 | * The bootstrap kernel entry code has set these up. Save them for | |
346 | * a given CPU | |
347 | */ | |
148f9bb8 | 348 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
349 | { |
350 | struct cpuinfo_x86 *c = &cpu_data(id); | |
351 | ||
30bb9811 AK |
352 | /* Copy boot_cpu_data only on the first bringup */ |
353 | if (!c->initialized) | |
354 | *c = boot_cpu_data; | |
1d89a7f0 | 355 | c->cpu_index = id; |
30106c17 FY |
356 | /* |
357 | * During boot time, CPU0 has this setup already. Save the info when | |
358 | * bringing up AP or offlined CPU0. | |
359 | */ | |
360 | identify_secondary_cpu(c); | |
30bb9811 | 361 | c->initialized = true; |
1d89a7f0 GOC |
362 | } |
363 | ||
cebf15eb DH |
364 | static bool |
365 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
366 | { | |
367 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
368 | ||
369 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
370 | } | |
371 | ||
148f9bb8 | 372 | static bool |
316ad248 | 373 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 374 | { |
316ad248 PZ |
375 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
376 | ||
cebf15eb | 377 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
378 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
379 | "[node: %d != %d]. Ignoring dependency.\n", | |
380 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
381 | } | |
382 | ||
7d79a7bd | 383 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 384 | do { \ |
7d79a7bd BG |
385 | cpumask_set_cpu((c1), mfunc(c2)); \ |
386 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
387 | } while (0) |
388 | ||
148f9bb8 | 389 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 390 | { |
362f924b | 391 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
392 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
393 | ||
394 | if (c->phys_proc_id == o->phys_proc_id && | |
79a8b9aa BP |
395 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
396 | if (c->cpu_core_id == o->cpu_core_id) | |
397 | return topology_sane(c, o, "smt"); | |
398 | ||
399 | if ((c->cu_id != 0xff) && | |
400 | (o->cu_id != 0xff) && | |
401 | (c->cu_id == o->cu_id)) | |
402 | return topology_sane(c, o, "smt"); | |
403 | } | |
316ad248 PZ |
404 | |
405 | } else if (c->phys_proc_id == o->phys_proc_id && | |
406 | c->cpu_core_id == o->cpu_core_id) { | |
407 | return topology_sane(c, o, "smt"); | |
408 | } | |
409 | ||
410 | return false; | |
411 | } | |
412 | ||
148f9bb8 | 413 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
414 | { |
415 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
416 | ||
417 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
418 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
419 | return topology_sane(c, o, "llc"); | |
420 | ||
421 | return false; | |
d4fbe4f0 AH |
422 | } |
423 | ||
cebf15eb DH |
424 | /* |
425 | * Unlike the other levels, we do not enforce keeping a | |
426 | * multicore group inside a NUMA node. If this happens, we will | |
427 | * discard the MC level of the topology later. | |
428 | */ | |
429 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 430 | { |
cebf15eb DH |
431 | if (c->phys_proc_id == o->phys_proc_id) |
432 | return true; | |
316ad248 PZ |
433 | return false; |
434 | } | |
1d89a7f0 | 435 | |
d3d37d85 TC |
436 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
437 | static inline int x86_sched_itmt_flags(void) | |
438 | { | |
439 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
440 | } | |
441 | ||
442 | #ifdef CONFIG_SCHED_MC | |
443 | static int x86_core_flags(void) | |
444 | { | |
445 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
446 | } | |
447 | #endif | |
448 | #ifdef CONFIG_SCHED_SMT | |
449 | static int x86_smt_flags(void) | |
450 | { | |
451 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
452 | } | |
453 | #endif | |
454 | #endif | |
455 | ||
8f37961c | 456 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 457 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 458 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
459 | #endif |
460 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 461 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
462 | #endif |
463 | { NULL, }, | |
464 | }; | |
8f37961c TC |
465 | |
466 | static struct sched_domain_topology_level x86_topology[] = { | |
467 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 468 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
469 | #endif |
470 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 471 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
472 | #endif |
473 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
474 | { NULL, }, | |
475 | }; | |
476 | ||
cebf15eb | 477 | /* |
8f37961c TC |
478 | * Set if a package/die has multiple NUMA nodes inside. |
479 | * AMD Magny-Cours and Intel Cluster-on-Die have this. | |
cebf15eb | 480 | */ |
8f37961c | 481 | static bool x86_has_numa_in_package; |
cebf15eb | 482 | |
148f9bb8 | 483 | void set_cpu_sibling_map(int cpu) |
768d9505 | 484 | { |
316ad248 | 485 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 486 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 487 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 488 | struct cpuinfo_x86 *o; |
70b8301f | 489 | int i, threads; |
768d9505 | 490 | |
c2d1cec1 | 491 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 492 | |
b0bc225d | 493 | if (!has_mp) { |
7d79a7bd | 494 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 495 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 496 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
497 | c->booted_cores = 1; |
498 | return; | |
499 | } | |
500 | ||
c2d1cec1 | 501 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
502 | o = &cpu_data(i); |
503 | ||
504 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 505 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 506 | |
b0bc225d | 507 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 508 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 509 | |
ceb1cbac KB |
510 | } |
511 | ||
512 | /* | |
513 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 514 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
515 | */ |
516 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
517 | o = &cpu_data(i); | |
518 | ||
cebf15eb | 519 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 520 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 521 | |
768d9505 GC |
522 | /* |
523 | * Does this new cpu bringup a new core? | |
524 | */ | |
7d79a7bd BG |
525 | if (cpumask_weight( |
526 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
527 | /* |
528 | * for each core in package, increment | |
529 | * the booted_cores for this new cpu | |
530 | */ | |
7d79a7bd BG |
531 | if (cpumask_first( |
532 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
533 | c->booted_cores++; |
534 | /* | |
535 | * increment the core count for all | |
536 | * the other cpus in this package | |
537 | */ | |
538 | if (i != cpu) | |
539 | cpu_data(i).booted_cores++; | |
540 | } else if (i != cpu && !c->booted_cores) | |
541 | c->booted_cores = cpu_data(i).booted_cores; | |
542 | } | |
728e5653 | 543 | if (match_die(c, o) && !topology_same_node(c, o)) |
8f37961c | 544 | x86_has_numa_in_package = true; |
768d9505 | 545 | } |
70b8301f AK |
546 | |
547 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
548 | if (threads > __max_smt_threads) | |
549 | __max_smt_threads = threads; | |
768d9505 GC |
550 | } |
551 | ||
70708a18 | 552 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 553 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 554 | { |
9f646389 | 555 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
556 | } |
557 | ||
a4928cff | 558 | static void impress_friends(void) |
904541e2 GOC |
559 | { |
560 | int cpu; | |
561 | unsigned long bogosum = 0; | |
562 | /* | |
563 | * Allow the user to impress friends. | |
564 | */ | |
c767a54b | 565 | pr_debug("Before bogomips\n"); |
904541e2 | 566 | for_each_possible_cpu(cpu) |
c2d1cec1 | 567 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 568 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 569 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 570 | num_online_cpus(), |
904541e2 GOC |
571 | bogosum/(500000/HZ), |
572 | (bogosum/(5000/HZ))%100); | |
573 | ||
c767a54b | 574 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
575 | } |
576 | ||
569712b2 | 577 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
578 | { |
579 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 580 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
581 | int timeout; |
582 | u32 status; | |
583 | ||
c767a54b | 584 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
585 | |
586 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 587 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
588 | |
589 | /* | |
590 | * Wait for idle. | |
591 | */ | |
592 | status = safe_apic_wait_icr_idle(); | |
593 | if (status) | |
c767a54b | 594 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 595 | |
1b374e4d | 596 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
597 | |
598 | timeout = 0; | |
599 | do { | |
600 | udelay(100); | |
601 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
602 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
603 | ||
604 | switch (status) { | |
605 | case APIC_ICR_RR_VALID: | |
606 | status = apic_read(APIC_RRR); | |
c767a54b | 607 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
608 | break; |
609 | default: | |
c767a54b | 610 | pr_cont("failed\n"); |
cb3c8b90 GOC |
611 | } |
612 | } | |
613 | } | |
614 | ||
d68921f9 LB |
615 | /* |
616 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
617 | * that there should be a 10ms delay between the BSP asserting INIT | |
618 | * and de-asserting INIT, when starting a remote processor. | |
619 | * But that slows boot and resume on modern processors, which include | |
620 | * many cores and don't require that delay. | |
621 | * | |
622 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 623 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
624 | */ |
625 | #define UDELAY_10MS_DEFAULT 10000 | |
626 | ||
656279a1 | 627 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
628 | |
629 | static int __init cpu_init_udelay(char *str) | |
630 | { | |
631 | get_option(&str, &init_udelay); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | early_param("cpu_init_udelay", cpu_init_udelay); | |
636 | ||
1a744cb3 LB |
637 | static void __init smp_quirk_init_udelay(void) |
638 | { | |
639 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 640 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
641 | return; |
642 | ||
643 | /* if modern processor, use no delay */ | |
644 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 645 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 646 | init_udelay = 0; |
656279a1 LB |
647 | return; |
648 | } | |
f1ccd249 LB |
649 | /* else, use legacy delay */ |
650 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
651 | } |
652 | ||
cb3c8b90 GOC |
653 | /* |
654 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
655 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
656 | * won't ... remember to clear down the APIC, etc later. | |
657 | */ | |
148f9bb8 | 658 | int |
e1c467e6 | 659 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
660 | { |
661 | unsigned long send_status, accept_status = 0; | |
662 | int maxlvt; | |
663 | ||
664 | /* Target chip */ | |
cb3c8b90 GOC |
665 | /* Boot on the stack */ |
666 | /* Kick the second */ | |
e1c467e6 | 667 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 668 | |
cfc1b9a6 | 669 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
670 | send_status = safe_apic_wait_icr_idle(); |
671 | ||
672 | /* | |
673 | * Give the other CPU some time to accept the IPI. | |
674 | */ | |
675 | udelay(200); | |
cff9ab2b | 676 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
677 | maxlvt = lapic_get_maxlvt(); |
678 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
679 | apic_write(APIC_ESR, 0); | |
680 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
681 | } | |
c767a54b | 682 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
683 | |
684 | if (send_status) | |
c767a54b | 685 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 686 | if (accept_status) |
c767a54b | 687 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
688 | |
689 | return (send_status | accept_status); | |
690 | } | |
cb3c8b90 | 691 | |
148f9bb8 | 692 | static int |
569712b2 | 693 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 694 | { |
f5d6a52f | 695 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
696 | int maxlvt, num_starts, j; |
697 | ||
593f4a78 MR |
698 | maxlvt = lapic_get_maxlvt(); |
699 | ||
cb3c8b90 GOC |
700 | /* |
701 | * Be paranoid about clearing APIC errors. | |
702 | */ | |
cff9ab2b | 703 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
704 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
705 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
706 | apic_read(APIC_ESR); |
707 | } | |
708 | ||
c767a54b | 709 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
710 | |
711 | /* | |
712 | * Turn INIT on target chip | |
713 | */ | |
cb3c8b90 GOC |
714 | /* |
715 | * Send IPI | |
716 | */ | |
1b374e4d SS |
717 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
718 | phys_apicid); | |
cb3c8b90 | 719 | |
cfc1b9a6 | 720 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
721 | send_status = safe_apic_wait_icr_idle(); |
722 | ||
7cb68598 | 723 | udelay(init_udelay); |
cb3c8b90 | 724 | |
c767a54b | 725 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
726 | |
727 | /* Target chip */ | |
cb3c8b90 | 728 | /* Send IPI */ |
1b374e4d | 729 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 730 | |
cfc1b9a6 | 731 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
732 | send_status = safe_apic_wait_icr_idle(); |
733 | ||
734 | mb(); | |
cb3c8b90 GOC |
735 | |
736 | /* | |
737 | * Should we send STARTUP IPIs ? | |
738 | * | |
739 | * Determine this based on the APIC version. | |
740 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
741 | */ | |
cff9ab2b | 742 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
743 | num_starts = 2; |
744 | else | |
745 | num_starts = 0; | |
746 | ||
cb3c8b90 GOC |
747 | /* |
748 | * Run STARTUP IPI loop. | |
749 | */ | |
c767a54b | 750 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 751 | |
cb3c8b90 | 752 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 753 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
754 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
755 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 756 | apic_read(APIC_ESR); |
c767a54b | 757 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
758 | |
759 | /* | |
760 | * STARTUP IPI | |
761 | */ | |
762 | ||
763 | /* Target chip */ | |
cb3c8b90 GOC |
764 | /* Boot on the stack */ |
765 | /* Kick the second */ | |
1b374e4d SS |
766 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
767 | phys_apicid); | |
cb3c8b90 GOC |
768 | |
769 | /* | |
770 | * Give the other CPU some time to accept the IPI. | |
771 | */ | |
fcafddec LB |
772 | if (init_udelay == 0) |
773 | udelay(10); | |
774 | else | |
a9bcaa02 | 775 | udelay(300); |
cb3c8b90 | 776 | |
c767a54b | 777 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 778 | |
cfc1b9a6 | 779 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
780 | send_status = safe_apic_wait_icr_idle(); |
781 | ||
782 | /* | |
783 | * Give the other CPU some time to accept the IPI. | |
784 | */ | |
fcafddec LB |
785 | if (init_udelay == 0) |
786 | udelay(10); | |
787 | else | |
a9bcaa02 | 788 | udelay(200); |
cb3c8b90 | 789 | |
593f4a78 | 790 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 791 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
792 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
793 | if (send_status || accept_status) | |
794 | break; | |
795 | } | |
c767a54b | 796 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
797 | |
798 | if (send_status) | |
c767a54b | 799 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 800 | if (accept_status) |
c767a54b | 801 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
802 | |
803 | return (send_status | accept_status); | |
804 | } | |
cb3c8b90 | 805 | |
2eaad1fd | 806 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 807 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
808 | { |
809 | static int current_node = -1; | |
4adc8b71 | 810 | int node = early_cpu_to_node(cpu); |
a17bce4d | 811 | static int width, node_width; |
646e29a1 BP |
812 | |
813 | if (!width) | |
814 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 815 | |
a17bce4d BP |
816 | if (!node_width) |
817 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
818 | ||
819 | if (cpu == 1) | |
820 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
821 | ||
719b3680 | 822 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
823 | if (node != current_node) { |
824 | if (current_node > (-1)) | |
a17bce4d | 825 | pr_cont("\n"); |
2eaad1fd | 826 | current_node = node; |
a17bce4d BP |
827 | |
828 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
829 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 830 | } |
646e29a1 BP |
831 | |
832 | /* Add padding for the BSP */ | |
833 | if (cpu == 1) | |
834 | pr_cont("%*s", width + 1, " "); | |
835 | ||
836 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
837 | ||
2eaad1fd MT |
838 | } else |
839 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
840 | node, cpu, apicid); | |
841 | } | |
842 | ||
e1c467e6 FY |
843 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
844 | { | |
845 | int cpu; | |
846 | ||
847 | cpu = smp_processor_id(); | |
848 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
849 | return NMI_HANDLED; | |
850 | ||
851 | return NMI_DONE; | |
852 | } | |
853 | ||
854 | /* | |
855 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
856 | * | |
857 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
858 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
859 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
860 | * | |
861 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
862 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
863 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
864 | * real platform and request are available. | |
865 | */ | |
148f9bb8 | 866 | static int |
e1c467e6 FY |
867 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
868 | int *cpu0_nmi_registered) | |
869 | { | |
870 | int id; | |
871 | int boot_error; | |
872 | ||
ea7bdc65 JK |
873 | preempt_disable(); |
874 | ||
e1c467e6 FY |
875 | /* |
876 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
877 | */ | |
ea7bdc65 JK |
878 | if (cpu) { |
879 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
880 | goto out; | |
881 | } | |
e1c467e6 FY |
882 | |
883 | /* | |
884 | * Wake up BSP by nmi. | |
885 | * | |
886 | * Register a NMI handler to help wake up CPU0. | |
887 | */ | |
888 | boot_error = register_nmi_handler(NMI_LOCAL, | |
889 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
890 | ||
891 | if (!boot_error) { | |
892 | enable_start_cpu0 = 1; | |
893 | *cpu0_nmi_registered = 1; | |
894 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
895 | id = cpu0_logical_apicid; | |
896 | else | |
897 | id = apicid; | |
898 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
899 | } | |
ea7bdc65 JK |
900 | |
901 | out: | |
902 | preempt_enable(); | |
e1c467e6 FY |
903 | |
904 | return boot_error; | |
905 | } | |
906 | ||
3f85483b BO |
907 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
908 | { | |
909 | /* Just in case we booted with a single CPU. */ | |
910 | alternatives_enable_smp(); | |
911 | ||
912 | per_cpu(current_task, cpu) = idle; | |
913 | ||
914 | #ifdef CONFIG_X86_32 | |
915 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
916 | irq_ctx_init(cpu); | |
cd493a6d | 917 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 918 | #else |
3f85483b BO |
919 | initial_gs = per_cpu_offset(cpu); |
920 | #endif | |
3f85483b BO |
921 | } |
922 | ||
cb3c8b90 GOC |
923 | /* |
924 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
925 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
926 | * Returns zero if CPU booted OK, else error code from |
927 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 928 | */ |
10e66760 VK |
929 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
930 | int *cpu0_nmi_registered) | |
cb3c8b90 | 931 | { |
48927bbb | 932 | volatile u32 *trampoline_status = |
b429dbf6 | 933 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 934 | /* start_ip had better be page-aligned! */ |
f37240f1 | 935 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 936 | |
cb3c8b90 | 937 | unsigned long boot_error = 0; |
ce4b1b16 | 938 | unsigned long timeout; |
cb3c8b90 | 939 | |
b9b1a9c3 | 940 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 941 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 942 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 943 | initial_stack = idle->thread.sp; |
cb3c8b90 | 944 | |
613e396b | 945 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 946 | init_espfix_ap(cpu); |
20d5e4a9 | 947 | |
2eaad1fd MT |
948 | /* So we see what's up */ |
949 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
950 | |
951 | /* | |
952 | * This grunge runs the startup process for | |
953 | * the targeted processor. | |
954 | */ | |
955 | ||
34d05591 | 956 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 957 | |
cfc1b9a6 | 958 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 959 | |
34d05591 JS |
960 | smpboot_setup_warm_reset_vector(start_ip); |
961 | /* | |
962 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 963 | */ |
cff9ab2b | 964 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
965 | apic_write(APIC_ESR, 0); |
966 | apic_read(APIC_ESR); | |
967 | } | |
34d05591 | 968 | } |
cb3c8b90 | 969 | |
ce4b1b16 IM |
970 | /* |
971 | * AP might wait on cpu_callout_mask in cpu_init() with | |
972 | * cpu_initialized_mask set if previous attempt to online | |
973 | * it timed-out. Clear cpu_initialized_mask so that after | |
974 | * INIT/SIPI it could start with a clean state. | |
975 | */ | |
976 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
977 | smp_mb(); | |
978 | ||
cb3c8b90 | 979 | /* |
e1c467e6 FY |
980 | * Wake up a CPU in difference cases: |
981 | * - Use the method in the APIC driver if it's defined | |
982 | * Otherwise, | |
983 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 984 | */ |
1f5bcabf IM |
985 | if (apic->wakeup_secondary_cpu) |
986 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
987 | else | |
e1c467e6 | 988 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 989 | cpu0_nmi_registered); |
cb3c8b90 GOC |
990 | |
991 | if (!boot_error) { | |
992 | /* | |
6e38f1e7 | 993 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 994 | */ |
ce4b1b16 IM |
995 | boot_error = -1; |
996 | timeout = jiffies + 10*HZ; | |
997 | while (time_before(jiffies, timeout)) { | |
998 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
999 | /* | |
1000 | * Tell AP to proceed with initialization | |
1001 | */ | |
1002 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1003 | boot_error = 0; | |
1004 | break; | |
1005 | } | |
ce4b1b16 IM |
1006 | schedule(); |
1007 | } | |
1008 | } | |
cb3c8b90 | 1009 | |
ce4b1b16 | 1010 | if (!boot_error) { |
cb3c8b90 | 1011 | /* |
ce4b1b16 | 1012 | * Wait till AP completes initial initialization |
cb3c8b90 | 1013 | */ |
ce4b1b16 | 1014 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1015 | /* |
1016 | * Allow other tasks to run while we wait for the | |
1017 | * AP to come online. This also gives a chance | |
1018 | * for the MTRR work(triggered by the AP coming online) | |
1019 | * to be completed in the stop machine context. | |
1020 | */ | |
1021 | schedule(); | |
cb3c8b90 | 1022 | } |
cb3c8b90 GOC |
1023 | } |
1024 | ||
1025 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1026 | *trampoline_status = 0; |
cb3c8b90 | 1027 | |
02421f98 YL |
1028 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1029 | /* | |
1030 | * Cleanup possible dangling ends... | |
1031 | */ | |
1032 | smpboot_restore_warm_reset_vector(); | |
1033 | } | |
e1c467e6 | 1034 | |
cb3c8b90 GOC |
1035 | return boot_error; |
1036 | } | |
1037 | ||
148f9bb8 | 1038 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1039 | { |
a21769a4 | 1040 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1041 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1042 | unsigned long flags; |
10e66760 | 1043 | int err, ret = 0; |
cb3c8b90 | 1044 | |
7a10e2a9 | 1045 | lockdep_assert_irqs_enabled(); |
cb3c8b90 | 1046 | |
cfc1b9a6 | 1047 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1048 | |
30106c17 | 1049 | if (apicid == BAD_APICID || |
c284b42a | 1050 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1051 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1052 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1053 | return -EINVAL; |
1054 | } | |
1055 | ||
1056 | /* | |
1057 | * Already booted CPU? | |
1058 | */ | |
c2d1cec1 | 1059 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1060 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1061 | return -ENOSYS; |
1062 | } | |
1063 | ||
1064 | /* | |
1065 | * Save current MTRR state in case it was changed since early boot | |
1066 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1067 | */ | |
1068 | mtrr_save_state(); | |
1069 | ||
2a442c9c PM |
1070 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1071 | err = cpu_check_up_prepare(cpu); | |
1072 | if (err && err != -EBUSY) | |
1073 | return err; | |
cb3c8b90 | 1074 | |
644c1541 | 1075 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1076 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1077 | |
3f85483b BO |
1078 | common_cpu_up(cpu, tidle); |
1079 | ||
10e66760 | 1080 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1081 | if (err) { |
feef1e8e | 1082 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1083 | ret = -EIO; |
1084 | goto unreg_nmi; | |
cb3c8b90 GOC |
1085 | } |
1086 | ||
1087 | /* | |
1088 | * Check TSC synchronization with the AP (keep irqs disabled | |
1089 | * while doing so): | |
1090 | */ | |
1091 | local_irq_save(flags); | |
1092 | check_tsc_sync_source(cpu); | |
1093 | local_irq_restore(flags); | |
1094 | ||
7c04e64a | 1095 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1096 | cpu_relax(); |
1097 | touch_nmi_watchdog(); | |
1098 | } | |
1099 | ||
10e66760 VK |
1100 | unreg_nmi: |
1101 | /* | |
1102 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1103 | * to avoid impact of possible long unregister time. | |
1104 | */ | |
1105 | if (cpu0_nmi_registered) | |
1106 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1107 | ||
1108 | return ret; | |
cb3c8b90 GOC |
1109 | } |
1110 | ||
7167d08e HK |
1111 | /** |
1112 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1113 | */ | |
1114 | void arch_disable_smp_support(void) | |
1115 | { | |
1116 | disable_ioapic_support(); | |
1117 | } | |
1118 | ||
8aef135c GOC |
1119 | /* |
1120 | * Fall back to non SMP mode after errors. | |
1121 | * | |
1122 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1123 | */ | |
1124 | static __init void disable_smp(void) | |
1125 | { | |
613c25ef TG |
1126 | pr_info("SMP disabled\n"); |
1127 | ||
ef4c59a4 TG |
1128 | disable_ioapic_support(); |
1129 | ||
4f062896 RR |
1130 | init_cpu_present(cpumask_of(0)); |
1131 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1132 | |
8aef135c | 1133 | if (smp_found_config) |
b6df1b8b | 1134 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1135 | else |
b6df1b8b | 1136 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1137 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1138 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1139 | } |
1140 | ||
1141 | /* | |
1142 | * Various sanity checks. | |
1143 | */ | |
4f45ed9f | 1144 | static void __init smp_sanity_check(void) |
8aef135c | 1145 | { |
ac23d4ee | 1146 | preempt_disable(); |
a58f03b0 | 1147 | |
1ff2f20d | 1148 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1149 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1150 | unsigned int cpu; | |
1151 | unsigned nr; | |
1152 | ||
c767a54b JP |
1153 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1154 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1155 | |
1156 | nr = 0; | |
1157 | for_each_present_cpu(cpu) { | |
1158 | if (nr >= 8) | |
c2d1cec1 | 1159 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1160 | nr++; |
1161 | } | |
1162 | ||
1163 | nr = 0; | |
1164 | for_each_possible_cpu(cpu) { | |
1165 | if (nr >= 8) | |
c2d1cec1 | 1166 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1167 | nr++; |
1168 | } | |
1169 | ||
1170 | nr_cpu_ids = 8; | |
1171 | } | |
1172 | #endif | |
1173 | ||
8aef135c | 1174 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1175 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1176 | hard_smp_processor_id()); |
1177 | ||
8aef135c GOC |
1178 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1179 | } | |
1180 | ||
8aef135c GOC |
1181 | /* |
1182 | * Should not be necessary because the MP table should list the boot | |
1183 | * CPU too, but we do it for the sake of robustness anyway. | |
1184 | */ | |
a27a6210 | 1185 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1186 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1187 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1188 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1189 | } | |
ac23d4ee | 1190 | preempt_enable(); |
8aef135c GOC |
1191 | } |
1192 | ||
1193 | static void __init smp_cpu_index_default(void) | |
1194 | { | |
1195 | int i; | |
1196 | struct cpuinfo_x86 *c; | |
1197 | ||
7c04e64a | 1198 | for_each_possible_cpu(i) { |
8aef135c GOC |
1199 | c = &cpu_data(i); |
1200 | /* mark all to hotplug */ | |
9628937d | 1201 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1202 | } |
1203 | } | |
1204 | ||
4b1244b4 DL |
1205 | static void __init smp_get_logical_apicid(void) |
1206 | { | |
1207 | if (x2apic_mode) | |
1208 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1209 | else | |
1210 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1211 | } | |
1212 | ||
8aef135c | 1213 | /* |
935356ce DL |
1214 | * Prepare for SMP bootup. |
1215 | * @max_cpus: configured maximum number of CPUs, It is a legacy parameter | |
1216 | * for common interface support. | |
8aef135c GOC |
1217 | */ |
1218 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1219 | { | |
7ad728f9 RR |
1220 | unsigned int i; |
1221 | ||
8aef135c | 1222 | smp_cpu_index_default(); |
792363d2 | 1223 | |
8aef135c GOC |
1224 | /* |
1225 | * Setup boot CPU information | |
1226 | */ | |
30106c17 | 1227 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1228 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1229 | mb(); | |
bd22a2f1 | 1230 | |
7ad728f9 | 1231 | for_each_possible_cpu(i) { |
79f55997 LZ |
1232 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1233 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1234 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1235 | } |
8f37961c TC |
1236 | |
1237 | /* | |
1238 | * Set 'default' x86 topology, this matches default_topology() in that | |
1239 | * it has NUMA nodes as a topology level. See also | |
1240 | * native_smp_cpus_done(). | |
1241 | * | |
1242 | * Must be done before set_cpus_sibling_map() is ran. | |
1243 | */ | |
1244 | set_sched_topology(x86_topology); | |
1245 | ||
8aef135c GOC |
1246 | set_cpu_sibling_map(0); |
1247 | ||
4f45ed9f DL |
1248 | smp_sanity_check(); |
1249 | ||
1250 | switch (apic_intr_mode) { | |
1251 | case APIC_PIC: | |
1252 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
613c25ef TG |
1253 | disable_smp(); |
1254 | return; | |
4f45ed9f | 1255 | case APIC_SYMMETRIC_IO_NO_ROUTING: |
613c25ef | 1256 | disable_smp(); |
a2510d15 DL |
1257 | /* Setup local timer */ |
1258 | x86_init.timers.setup_percpu_clockev(); | |
250a1ac6 | 1259 | return; |
4f45ed9f DL |
1260 | case APIC_VIRTUAL_WIRE: |
1261 | case APIC_SYMMETRIC_IO: | |
613c25ef | 1262 | break; |
8aef135c GOC |
1263 | } |
1264 | ||
a2510d15 DL |
1265 | /* Setup local timer */ |
1266 | x86_init.timers.setup_percpu_clockev(); | |
8aef135c | 1267 | |
4b1244b4 | 1268 | smp_get_logical_apicid(); |
ef4c59a4 | 1269 | |
d54ff31d | 1270 | pr_info("CPU0: "); |
8aef135c | 1271 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1272 | |
ca5d376e DL |
1273 | native_pv_lock_init(); |
1274 | ||
9ec808a0 | 1275 | uv_system_init(); |
d0af9eed SS |
1276 | |
1277 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1278 | |
1279 | smp_quirk_init_udelay(); | |
3f6a3b03 TG |
1280 | |
1281 | speculative_store_bypass_ht_init(); | |
8aef135c | 1282 | } |
d0af9eed SS |
1283 | |
1284 | void arch_enable_nonboot_cpus_begin(void) | |
1285 | { | |
1286 | set_mtrr_aps_delayed_init(); | |
1287 | } | |
1288 | ||
1289 | void arch_enable_nonboot_cpus_end(void) | |
1290 | { | |
1291 | mtrr_aps_init(); | |
1292 | } | |
1293 | ||
a8db8453 GOC |
1294 | /* |
1295 | * Early setup to make printk work. | |
1296 | */ | |
1297 | void __init native_smp_prepare_boot_cpu(void) | |
1298 | { | |
1299 | int me = smp_processor_id(); | |
552be871 | 1300 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1301 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1302 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1303 | cpu_set_state_online(me); |
a8db8453 GOC |
1304 | } |
1305 | ||
c6b99a00 | 1306 | void __init calculate_max_logical_packages(void) |
83f7eb9c | 1307 | { |
b4c0a732 PB |
1308 | int ncpus; |
1309 | ||
b4c0a732 PB |
1310 | /* |
1311 | * Today neither Intel nor AMD support heterogenous systems so | |
1312 | * extrapolate the boot cpu's data to all packages. | |
1313 | */ | |
947134d9 | 1314 | ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); |
fdd42ae1 | 1315 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
b4c0a732 | 1316 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
c6b99a00 PB |
1317 | } |
1318 | ||
1319 | void __init native_smp_cpus_done(unsigned int max_cpus) | |
1320 | { | |
1321 | pr_debug("Boot done\n"); | |
1322 | ||
1323 | calculate_max_logical_packages(); | |
83f7eb9c | 1324 | |
8f37961c TC |
1325 | if (x86_has_numa_in_package) |
1326 | set_sched_topology(x86_numa_in_package_topology); | |
1327 | ||
99e8b9ca | 1328 | nmi_selftest(); |
83f7eb9c | 1329 | impress_friends(); |
d0af9eed | 1330 | mtrr_aps_init(); |
83f7eb9c GOC |
1331 | } |
1332 | ||
3b11ce7f MT |
1333 | static int __initdata setup_possible_cpus = -1; |
1334 | static int __init _setup_possible_cpus(char *str) | |
1335 | { | |
1336 | get_option(&str, &setup_possible_cpus); | |
1337 | return 0; | |
1338 | } | |
1339 | early_param("possible_cpus", _setup_possible_cpus); | |
1340 | ||
1341 | ||
68a1c3f8 | 1342 | /* |
4f062896 | 1343 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1344 | * are onlined, or offlined. The reason is per-cpu data-structures |
1345 | * are allocated by some modules at init time, and dont expect to | |
1346 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1347 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1348 | * In case when cpu_hotplug is not compiled, then we resort to current |
1349 | * behaviour, which is cpu_possible == cpu_present. | |
1350 | * - Ashok Raj | |
1351 | * | |
1352 | * Three ways to find out the number of additional hotplug CPUs: | |
1353 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1354 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1355 | * - Otherwise don't reserve additional CPUs. |
1356 | * We do this because additional CPUs waste a lot of memory. | |
1357 | * -AK | |
1358 | */ | |
1359 | __init void prefill_possible_map(void) | |
1360 | { | |
cb48bb59 | 1361 | int i, possible; |
68a1c3f8 | 1362 | |
2a51fe08 PB |
1363 | /* No boot processor was found in mptable or ACPI MADT */ |
1364 | if (!num_processors) { | |
ff856051 VS |
1365 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1366 | int apicid = boot_cpu_physical_apicid; | |
1367 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1368 | |
ff856051 | 1369 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1370 | |
ff856051 VS |
1371 | /* Make sure boot cpu is enumerated */ |
1372 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1373 | apic->apic_id_valid(apicid)) | |
1374 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1375 | } | |
2a51fe08 PB |
1376 | |
1377 | if (!num_processors) | |
1378 | num_processors = 1; | |
1379 | } | |
329513a3 | 1380 | |
5f2eb550 JB |
1381 | i = setup_max_cpus ?: 1; |
1382 | if (setup_possible_cpus == -1) { | |
1383 | possible = num_processors; | |
1384 | #ifdef CONFIG_HOTPLUG_CPU | |
1385 | if (setup_max_cpus) | |
1386 | possible += disabled_cpus; | |
1387 | #else | |
1388 | if (possible > i) | |
1389 | possible = i; | |
1390 | #endif | |
1391 | } else | |
3b11ce7f MT |
1392 | possible = setup_possible_cpus; |
1393 | ||
730cf272 MT |
1394 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1395 | ||
2b633e3f YL |
1396 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1397 | if (possible > nr_cpu_ids) { | |
9b130ad5 | 1398 | pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", |
2b633e3f YL |
1399 | possible, nr_cpu_ids); |
1400 | possible = nr_cpu_ids; | |
3b11ce7f | 1401 | } |
68a1c3f8 | 1402 | |
5f2eb550 JB |
1403 | #ifdef CONFIG_HOTPLUG_CPU |
1404 | if (!setup_max_cpus) | |
1405 | #endif | |
1406 | if (possible > i) { | |
c767a54b | 1407 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1408 | possible, setup_max_cpus); |
1409 | possible = i; | |
1410 | } | |
1411 | ||
427d77a3 TG |
1412 | nr_cpu_ids = possible; |
1413 | ||
c767a54b | 1414 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1415 | possible, max_t(int, possible - num_processors, 0)); |
1416 | ||
427d77a3 TG |
1417 | reset_cpu_possible_mask(); |
1418 | ||
68a1c3f8 | 1419 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1420 | set_cpu_possible(i, true); |
68a1c3f8 | 1421 | } |
69c18c15 | 1422 | |
14adf855 CE |
1423 | #ifdef CONFIG_HOTPLUG_CPU |
1424 | ||
70b8301f AK |
1425 | /* Recompute SMT state for all CPUs on offline */ |
1426 | static void recompute_smt_state(void) | |
1427 | { | |
1428 | int max_threads, cpu; | |
1429 | ||
1430 | max_threads = 0; | |
1431 | for_each_online_cpu (cpu) { | |
1432 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1433 | ||
1434 | if (threads > max_threads) | |
1435 | max_threads = threads; | |
1436 | } | |
1437 | __max_smt_threads = max_threads; | |
1438 | } | |
1439 | ||
14adf855 CE |
1440 | static void remove_siblinginfo(int cpu) |
1441 | { | |
1442 | int sibling; | |
1443 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1444 | ||
7d79a7bd BG |
1445 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1446 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1447 | /*/ |
1448 | * last thread sibling in this cpu core going down | |
1449 | */ | |
7d79a7bd | 1450 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1451 | cpu_data(sibling).booted_cores--; |
1452 | } | |
1453 | ||
7d79a7bd BG |
1454 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1455 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1456 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1457 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1458 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1459 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1460 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 | 1461 | c->cpu_core_id = 0; |
8378c418 | 1462 | c->booted_cores = 0; |
c2d1cec1 | 1463 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1464 | recompute_smt_state(); |
14adf855 CE |
1465 | } |
1466 | ||
4daa832d | 1467 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1468 | { |
c2d1cec1 MT |
1469 | set_cpu_online(cpu, false); |
1470 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1471 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1472 | /* was set by cpu_init() */ |
c2d1cec1 | 1473 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1474 | numa_remove_cpu(cpu); |
69c18c15 GC |
1475 | } |
1476 | ||
8227dce7 | 1477 | void cpu_disable_common(void) |
69c18c15 GC |
1478 | { |
1479 | int cpu = smp_processor_id(); | |
69c18c15 | 1480 | |
69c18c15 GC |
1481 | remove_siblinginfo(cpu); |
1482 | ||
1483 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1484 | lock_vector_lock(); |
69c18c15 | 1485 | remove_cpu_from_maps(cpu); |
d388e5fd | 1486 | unlock_vector_lock(); |
d7b381bb | 1487 | fixup_irqs(); |
0fa115da | 1488 | lapic_offline(); |
8227dce7 AN |
1489 | } |
1490 | ||
1491 | int native_cpu_disable(void) | |
1492 | { | |
da6139e4 PB |
1493 | int ret; |
1494 | ||
2cffad7b | 1495 | ret = lapic_can_unplug_cpu(); |
da6139e4 PB |
1496 | if (ret) |
1497 | return ret; | |
1498 | ||
8227dce7 | 1499 | clear_local_APIC(); |
8227dce7 | 1500 | cpu_disable_common(); |
2ed53c0d | 1501 | |
69c18c15 GC |
1502 | return 0; |
1503 | } | |
1504 | ||
2a442c9c | 1505 | int common_cpu_die(unsigned int cpu) |
54279552 | 1506 | { |
2a442c9c | 1507 | int ret = 0; |
54279552 | 1508 | |
69c18c15 | 1509 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1510 | |
2ed53c0d | 1511 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1512 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1513 | if (system_state == SYSTEM_RUNNING) |
1514 | pr_info("CPU %u is now offline\n", cpu); | |
1515 | } else { | |
1516 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1517 | ret = -1; |
69c18c15 | 1518 | } |
2a442c9c PM |
1519 | |
1520 | return ret; | |
1521 | } | |
1522 | ||
1523 | void native_cpu_die(unsigned int cpu) | |
1524 | { | |
1525 | common_cpu_die(cpu); | |
69c18c15 | 1526 | } |
a21f5d88 AN |
1527 | |
1528 | void play_dead_common(void) | |
1529 | { | |
1530 | idle_task_exit(); | |
a21f5d88 | 1531 | |
a21f5d88 | 1532 | /* Ack it */ |
2a442c9c | 1533 | (void)cpu_report_death(); |
a21f5d88 AN |
1534 | |
1535 | /* | |
1536 | * With physical CPU hotplug, we should halt the cpu | |
1537 | */ | |
1538 | local_irq_disable(); | |
1539 | } | |
1540 | ||
e1c467e6 FY |
1541 | static bool wakeup_cpu0(void) |
1542 | { | |
1543 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1544 | return true; | |
1545 | ||
1546 | return false; | |
1547 | } | |
1548 | ||
ea530692 PA |
1549 | /* |
1550 | * We need to flush the caches before going to sleep, lest we have | |
1551 | * dirty data in our caches when we come back up. | |
1552 | */ | |
1553 | static inline void mwait_play_dead(void) | |
1554 | { | |
1555 | unsigned int eax, ebx, ecx, edx; | |
1556 | unsigned int highest_cstate = 0; | |
1557 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1558 | void *mwait_ptr; |
576cfb40 | 1559 | int i; |
ea530692 | 1560 | |
98ca5f7f YG |
1561 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
1562 | return; | |
69fb3676 | 1563 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1564 | return; |
840d2830 | 1565 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1566 | return; |
7b543a53 | 1567 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1568 | return; |
1569 | ||
1570 | eax = CPUID_MWAIT_LEAF; | |
1571 | ecx = 0; | |
1572 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1573 | ||
1574 | /* | |
1575 | * eax will be 0 if EDX enumeration is not valid. | |
1576 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1577 | */ | |
1578 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1579 | eax = 0; | |
1580 | } else { | |
1581 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1582 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1583 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1584 | highest_cstate = i; | |
1585 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1586 | } | |
1587 | } | |
1588 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1589 | (highest_subcstate - 1); | |
1590 | } | |
1591 | ||
ce5f6824 PA |
1592 | /* |
1593 | * This should be a memory location in a cache line which is | |
1594 | * unlikely to be touched by other processors. The actual | |
1595 | * content is immaterial as it is not actually modified in any way. | |
1596 | */ | |
1597 | mwait_ptr = ¤t_thread_info()->flags; | |
1598 | ||
a68e5c94 PA |
1599 | wbinvd(); |
1600 | ||
ea530692 | 1601 | while (1) { |
ce5f6824 PA |
1602 | /* |
1603 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1604 | * the Xeon 7400 series. It's not clear it is actually | |
1605 | * needed, but it should be harmless in either case. | |
1606 | * The WBINVD is insufficient due to the spurious-wakeup | |
1607 | * case where we return around the loop. | |
1608 | */ | |
7d590cca | 1609 | mb(); |
ce5f6824 | 1610 | clflush(mwait_ptr); |
7d590cca | 1611 | mb(); |
ce5f6824 | 1612 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1613 | mb(); |
1614 | __mwait(eax, 0); | |
e1c467e6 FY |
1615 | /* |
1616 | * If NMI wants to wake up CPU0, start CPU0. | |
1617 | */ | |
1618 | if (wakeup_cpu0()) | |
1619 | start_cpu0(); | |
ea530692 PA |
1620 | } |
1621 | } | |
1622 | ||
406f992e | 1623 | void hlt_play_dead(void) |
ea530692 | 1624 | { |
7b543a53 | 1625 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1626 | wbinvd(); |
1627 | ||
ea530692 | 1628 | while (1) { |
ea530692 | 1629 | native_halt(); |
e1c467e6 FY |
1630 | /* |
1631 | * If NMI wants to wake up CPU0, start CPU0. | |
1632 | */ | |
1633 | if (wakeup_cpu0()) | |
1634 | start_cpu0(); | |
ea530692 PA |
1635 | } |
1636 | } | |
1637 | ||
a21f5d88 AN |
1638 | void native_play_dead(void) |
1639 | { | |
1640 | play_dead_common(); | |
86886e55 | 1641 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1642 | |
1643 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1644 | if (cpuidle_play_dead()) |
1645 | hlt_play_dead(); | |
a21f5d88 AN |
1646 | } |
1647 | ||
69c18c15 | 1648 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1649 | int native_cpu_disable(void) |
69c18c15 GC |
1650 | { |
1651 | return -ENOSYS; | |
1652 | } | |
1653 | ||
93be71b6 | 1654 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1655 | { |
1656 | /* We said "no" in __cpu_disable */ | |
1657 | BUG(); | |
1658 | } | |
a21f5d88 AN |
1659 | |
1660 | void native_play_dead(void) | |
1661 | { | |
1662 | BUG(); | |
1663 | } | |
1664 | ||
68a1c3f8 | 1665 | #endif |