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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
1da177e4 | 43 | #include <linux/bootmem.h> |
f3705136 ZM |
44 | #include <linux/notifier.h> |
45 | #include <linux/cpu.h> | |
46 | #include <linux/percpu.h> | |
d04f41e3 | 47 | #include <linux/nmi.h> |
1da177e4 LT |
48 | |
49 | #include <linux/delay.h> | |
50 | #include <linux/mc146818rtc.h> | |
51 | #include <asm/tlbflush.h> | |
52 | #include <asm/desc.h> | |
53 | #include <asm/arch_hooks.h> | |
3e4ff115 | 54 | #include <asm/nmi.h> |
1da177e4 LT |
55 | |
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
7ce0bcfd | 59 | #include <asm/vmi.h> |
2b1f6278 | 60 | #include <asm/mtrr.h> |
1da177e4 | 61 | |
3b419089 | 62 | /* which logical CPU number maps to which CPU (physical APIC ID) */ |
5382e896 | 63 | u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata = |
71fff5e6 | 64 | { [0 ... NR_CPUS-1] = BAD_APICID }; |
3b419089 | 65 | void *x86_cpu_to_apicid_early_ptr; |
5382e896 | 66 | DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID; |
71fff5e6 | 67 | EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
1da177e4 | 68 | |
cbe879fc GOC |
69 | u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata |
70 | = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
71 | void *x86_bios_cpu_apicid_early_ptr; | |
72 | DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID; | |
73 | EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
74 | ||
3b08606d | 75 | u8 apicid_2_node[MAX_APICID]; |
76 | ||
1da177e4 LT |
77 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ |
78 | void *xquad_portio; | |
129f6946 AD |
79 | #ifdef CONFIG_X86_NUMAQ |
80 | EXPORT_SYMBOL(xquad_portio); | |
81 | #endif |